JPH03226823A - Disk controller - Google Patents

Abstract

PURPOSE:To improve the disk transfer speed of a disk controller by transferring alternately data between a first sub-controller group and a second sub-controller at the time of a data transfer between a host interface part and a sub-controller. CONSTITUTION:With respect to each of disk device (3-1) - (3-8), sub-controllers (5-1) - (5-8) for executing the control of write-in and read-out operations of data are provided. In such a state, the host interface part 4 switches successively pass information at every transfer of word data so that the sub-controllers (5-1) - (5-4) are designated at the time of transfer of a first word, the sub- controllers (5-5) - (5-8) are designated at the time of transfer of a second word, and the sub-controllers (5-1) - (5-4) are designated again at the time of transfer of a third word. In such a manner, the data transfer speed of a disk controller 2 can be improved.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a disk control device for transferring data in parallel between a host processor and a plurality of disk devices via a plurality of data buffers. .

[Conventional technology]

In conventional disk control devices, when writing or reading data to or from multiple (N) disk devices, the data transfer word between the host processor and the disk control device is N bytes wide, and the disk control By transferring 1 byte width between the device and each disk device, the transfer capacity is N times the data transfer speed of the disk device]
It is supposed to be done.

[Problem to be solved by the invention]

Conventional disk control devices as described above improve data transfer speed by increasing the width of data transfer between the host processor and the data transfer speed of the disk device. In order to increase the transfer speed of the disk controller, it is possible to increase the transfer word width, but the disadvantage is that it is not possible to increase the data transfer speed easily due to physical limitations. be.

[Means to solve the problem]

The disk control device of the present invention includes a boss 1 to an interface section that exchanges information with a predetermined hide width with a post processor, and a plurality of units that are connected to the host interface section and record data in a fixed length. a plurality of subcomputers 1 to rollers that control write or read operations for each of the disk devices;
- A path decoder that divides the roller into a plurality of sub-controller groups, inputs the path information output from the host interface section, and analyzes whether the roller is selected or not, and a path decoder that analyzes whether the roller is selected or not; The data transfer circuit that transfers 1 byte of data between the host (host) and the interface unit, and all subcontrollers in the subcontroller group to which it belongs prepare for data transfer. a synchronization circuit that confirms completion and notifies the data transfer circuit of the completion; and a data buffer that is connected to the data transfer circuit and stores write data or read data between the data transfer circuit and the corresponding transfer device. have.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram 11772 which does not show one embodiment of the present invention.

In FIG. 1, a disk control device 2 includes a host interface section 2 that controls data transfer of 4-hide width with a post-processor, and disk devices 3-1 to 3-8.
subcontrollers 5-1 to 5-8, each having a data buffer for absorbing a difference in access time, and controlling data writing and reading operations in line with each of the TIF devices 3-1 to 3-8; It is composed of:

When writing data to the disk devices 3-1 to 3-8, the post interface unit 4 receives the write data from the host processor 1 via the data buses 10 to 104, and sends the data to the subcontrollers 5-1 to 3-8. 5-8 to receive the write data, to the path information line 140, and after outputting the write data to the data buses 111 to 114, it is output to the information control line 130, which instructs to receive the data. do. When transferring the first word, specify subcontroller 1 to rollers 5-1 to 5-4, and when transferring the second word, specify subcontroller 5-5.
5-8, and when transferring the third word, specify subcon 1 to rollers 5-1 to 5-4 again. Path information is sequentially switched for each transfer.

FIG. 2 is a block diagram showing details of the sub-controller 5-1 shown in FIG. 1.

As shown in FIG. 2, when the path decoder 6-1 analyzes the path information on the path information line 140 and finds that it is selected, it transmits the data transfer instruction information 161 to the data transfer time ii! Output to 87-1. Synchronous circuit 8-1-
are connected to the subcontrollers 5-1 to 5 via the information line 15].
-4 confirms that it is ready to receive data, and outputs synchronization completion instruction information 201 to the data transfer circuit 7-1. The data transfer circuit 7-1 is
Data reception instruction information 1.30 from the post interface section 4, data transfer instruction information 161 from the path decoder 6-1, and synchronization completion instruction 20 from the synchronization circuit 8-1.
1, it receives 1 hide data from the host interface section 4 via the data bus 1]1, and returns response information to the post interface section 4 via the control line]40. At this time, sub controllers 5-2 to 5
-4 does not return response information. When the response information from the sub-controller 5-1 is returned, the host interface section 4 outputs the path information specifying the sub-controllers 5-5 to 5-8 to the path information line 140, and inputs the next word data to the text. After outputting data to the data buses 111 to 114, data reception instruction information is outputted to the control line 130. The subcontrollers 55 to 5-8 are the host interface unit 4
Receive data according to data reception instruction information from
From subcontroller 5-5 to host interface section 4
response information is returned via control line 140. In this way, the subcontrollers 5-1- to 5-4 and the subcontrollers 5-5 to 5-8 alternately receive one word of data.

When the data transfer circuit 7-1 receives data from the host interface section 4, the data transfer circuit 7-1 transfers the data to the pass line 1 when the write permission information 171 is output from the data buffer 9-1.
Write data is stored in data buffer 9-1 via 81-. When the write data read permission information 211 is output from the data buffer 9-1, the disk control unit 10-1 outputs the pass line 221 from the data buffer 9-1.
The write data is read through the information line 121, and the write data is written into the disk device 3-1 through the information line 121. Sub-controllers 5-2 to 5-8 also operate in the same manner as sub-controller 5-1.

When reading data from the disk devices 3-1 to 3-8, the disk controller 10-1 reads the data from the disk devices 3-1 to 3-8.
The data read from is stored in data buffer 9-1. When data buffer 9-1 stores read data, data read permission information 171. The data transfer circuit 7-
Output to 1. When the data read permission information 171 is output from the data buffer 9-1, the data transfer circuit 7-1 reads the read data via the pass line 181. The data transfer circuit 7-1 receives the data output instruction information 130 from the host interface section 4, the data transfer instruction information 161 from the path decoder 6-1, and the synchronization circuit 8.
Upon receiving the synchronization completion instruction information 201 from control line 1.
The response information is returned via 40. When the response information is returned from the sub controller 5-1, the host interface unit 4 receives the read data output to the data buses 111 to 11-4, and transfers it to the host processor 1 via the data buses 101 to 104. do. Sub controller 5
-1 to 5-4 and subcontrollers 5-5 to 5-8 alternately output one word of data, and the host interface unit 4 sequentially receives these data.

〔Effect of the invention〕

As explained above, in the disk control device of the present invention, when data is transferred between the host interface section and the subcontroller, the first subcontroller group consisting of a plurality of subcontrollers and the first subcontroller group consisting of a plurality of subcontrollers are used. By alternately transferring data to and from the second subcontroller, the data transfer speed of the disk device can be improved, and the data of the disk controller can be transferred to and from the second subcontroller without changing the byte width of the word transferred to the host processor. This has the effect of improving transfer speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing details of the subcontroller of the embodiment of FIG. 1. DESCRIPTION OF SYMBOLS 1... Host processor, 2... Disk control device, 3-1 to 3-8... Disk device, 4... Post interface unit, 5-1 to 5-8... Sub controller, 6 -1...Path decoder, 7-1...Data transfer circuit, 8-1...Synchronization circuit, 9-1...Data buffer, 10-1...Disk control unit.

Claims (1)

[Claims] A host interface unit that exchanges information in a predetermined byte width with a host processor, and a write or read operation for each of a plurality of disk devices connected to the host interface unit and that record data in a fixed length. The controller is equipped with a plurality of sub-controllers that perform control, divides the plurality of sub-controllers into a plurality of sub-controller groups, and inputs path information output from the host interface section to check whether the self-controller is selected or not. a path decoder that analyzes the path decoder, a data transfer circuit that transfers one byte of data to and from the host interface section when the path decoder confirms that it is selected, and the subcontroller group to which the path decoder belongs. writing between a synchronization circuit that confirms that all subcontrollers in the subcontroller have completed data transfer preparations and notifies the data transfer circuit of this fact, and the corresponding disk device that is connected to the data transfer circuit; 1. A disk control device comprising a data buffer for storing data or read data.