JPH0322626A - Fourth order delta/sigma modulator - Google Patents

Abstract

PURPOSE:To compress a low frequency quantized noise to the utmost with stable operation by dividing a DELTA-SIGMA modulator having a fourth order transmission characteristic into a main loop processing a main signal and a sub loop processing quantized noise. CONSTITUTION:First and 2nd integration devices 11, 12 are connected in series and a 1st quantizing device 31, a delay device 41 and adders 21, 22 form a main loop having a 2nd order transmission characteristic. An adder 25 extracts only an error component-Q1 (Z) of the 1st quantizer 31. The sub loop integrates the quantized error in the 2nd order transmission characteristic. The sub loop is provided with 3rd and 4th integration devices 13, 14 connected in series, a 2nd quantizer 32, a feedback use delay device 42 and the adders 23, 24. Since the main loop and the sub loop apply feedback within the 2nd order range only, stable operation is guaranteed.

Description

[Detailed Description of the Invention] [Summary] Regarding a delta-sigma modulator having a fourth-order transfer characteristic, the purpose is to stabilize the operation, and the first integrator integrates a sampled analog input; a second integrator that integrates the output of the first integrator, and a second integrator that quantizes the output of the second integrator and provides negative feedback to the inputs of the first and second integrators. a third integrator that integrates the quantization error of the first quantizer, a fourth integrator that integrates the output of the third integrator, and a fourth integrator that quantizes the output of the fourth integrator. a second quantizer that provides negative feedback to the inputs of the third and fourth integrators; and a first
and a second differentiator, the output of the second differentiator and the B1
The device is configured to include an arithmetic unit that adds the outputs of the subgenizers and generates a digital output.

[Industrial application field]

The present invention relates to a delta-sigma modulator with fourth-order transfer characteristics.

Delta sigma (Δ
-Σ) The modulator is used as a first stage encoder of an oversampling type A/D converter. In recent years, various processors capable of floating point operations have been developed, and high precision A/D converters have become desirable. On the other hand, since the accuracy of the A/D converter depends on its resolution, in order to reduce the quantization error,
/D converter needs to have multiple bits. An oversampling A/D converter encodes an analog signal at a sampling frequency much higher than its Nyquist rate, and limits the frequency of the encoded output to suppress some quantization noise in the low frequency range. We are trying to improve the S/N by limiting the This kind of oversampling type A
If the Δ-Σ modulator used as the first-stage encoder of the /D converter has low quantization noise in the low frequency band, the sampling frequency to achieve the required S/N can be lowered. .

[Conventional technology]

A basic Δ-Σ modulator integrates a sampled analog input, quantizes the output, converts it into a digital output, and provides negative feedback to the input. Using FIG. 3 as an example, there are an adder 21 that subtracts the digital output Y (Z) from the analog human power X (z), an integrator 11 that integrates the output, and a quantizer 31 that quantizes the output. , l sample delay device 4 which provides negative feedback of its output Y (Z)
A single integral type Δ-Σ modulator is constructed by l. Quantizer 31 is shown as an adder that adds a quantization error Q (Z).

If this quantizer 31 has a one-sample delay function, the feedback loop delay device 41 can be omitted. X(Z), Y
(Z) and Q(Z) are the Z-transformed values of the input, output, and quantization error, respectively, and the transfer function of the integrator 11 is expressed as (1-
Z-')-', the transfer function of the single integral Δ-Σ modulator described above is (X(Z)-Z-' ・Y(Z)) (1-Z
-')-' = Y(Z)-Q(Z) From the relationship, Y(Z)=X(Z)+(1-Z-')・Q(Z)
−・−・■. The term (1-Z-') in the above equation has a frequency characteristic that compresses the low frequency range and expands the high frequency range, so
By repeating this integration, the desired low frequency quantization noise Q
(Z) Q influence can be sufficiently reduced.

In FIG. 3, when the adder 22 and the second integrator 12 are connected after the first integrator 11, it becomes a double integration type Δ-Σ modulator,
Its transfer characteristic is y(z)=X(Z)+(1 − Z−')”・
Q(z) −.・−・■. This is the Q of the formula
The term (Z) is further multiplied by (1-Z-'). Similarly, adding the adder 23 and the third integrator 13 results in a triple integration type, and further adding the adder 24 and the fourth integrator l4 results in a quadruple integration type. In the triple integral type transfer characteristic, (1-
The term Z-') becomes cubic and becomes Y(z)=X(z)+(1-Z-')'・Q(z)
m * e + o, and in the quadruple integral type transfer characteristic, the term (1 - Z-') becomes fourth-order, and Y (z) = X (z) + (1-Z-')' - Q ( z)
・−=■.

In this way, as the order of the term (1-Z-') increases, the influence of the quantization noise Q (Z) in the low frequency range becomes smaller and smaller, and the first-stage code of oversampling A/D converters, which are becoming increasingly multi-bit, becomes smaller and smaller. It is convenient as a vessel. That is, the S/N of the A/D converter is required to have a high value, for example, 96 dB for 16 bits and 108 dB for 18 bits. As shown in FIG. 4, the oversampling type A/D converter can improve the S/N by increasing the sampling frequency. However, it is preferable that the sampling frequency be as low as possible from the viewpoint of the switching speed of the device and the cost. A high-order ΔΣ modulator that compresses quantization noise at low frequencies is an A/D
Helps reduce the oversampling frequency of the converter.

[Problem to be solved by the invention]

However, the stability of a series integral Δ-Σ modulator as shown in Figure 3 is said to be limited to the second order, and if the configuration shown in Figure 3 is adopted in the third order or higher, it will oscillate and malfunction. It becomes stable.

The present invention aims to improve this point. [Means for solving the problem] Fig. 1 is a diagram showing the principle of the present invention, in which 11-14 are first to fourth integrators, 21-24 are adders for negative feedback, and 25 is for calculating quantization error. 26 is an adder for final output, 31.
32 is a first and second quantizer, 41 to 44 are l-sample delay devices, and 51.52 is a first and second differentiator.

[Effect]

The first and second integrators 11.12 are connected in series, and together with the first quantizer 31, the delay device 4l, and the adder 21.22, form a main loop having poor-order transfer characteristics. The output F of this main loop is F = x(z)+ (l Z-')" ・Q+(
Z) ””■′, which is the formula Q (Z)
is replaced with the quantization noise Q, (Z) of the l-th quantizer 31. If this first quantizer 31 is realized by a simple combiner, the following relationship will be established between the human power E and the output F. F=E+Ql(Z)...
...■-Ql(Z)=E-F
・・・・・・■ Adder 25 realizes formula ■, and the first
Error ratio Q of the quantizer 31. Extract only (Z).

The sub-loop integrates this quantization error with a second-order transfer characteristic. This sub-loop has third and fourth integrators 13 connected in series.
．． 14, a second quantizer 32, and a delay device 42 for feedback.
and adders 23 and 24. The quantization noise of the second quantizer 32 is Q. (Z), the quantized output G is G=-Q+(z)+(t-z-+)z·Q. (Z)
・・・・・・■. In this sub-loop, first and second differentiators 51 and 52 are placed after the second quantizer 32, and the quantized output G is differentiated twice. If the transfer function of the differentiator 51 and 52 is (1-Z-'), the twice differentiated output H is H= (1
- Z-')"- G = (l Z-')"Q+(Z)+(I Z-'
)'・Qz(Z)・・・・・・■.

When the output H of this sub-loop and the output F of the main loop mentioned above are added by the adder 26, (1-z-'>" -
Ql(Z) and -(1-Z-')"-Ql(Z
) are canceled out, so the final output Y (z) is as follows.

Y(Z)=F+H =x(z)+(t-z-')'・Qz(z)...
...@This equation (2) has the same fourth-order transfer characteristic as the equation (2), so it can be seen that a quadruple integral type Δ-Σ modulator is equivalently realized.

Moreover, in the present invention, since both the main loop and the sub-loop perform feedback only within the second-order range, stable operation is guaranteed. The delay devices 43 and 44 in the main loop are for phase matching with the differentiators 51 and 52 in the sub-loop, and the number of stages of the differentiators 5l and 52 is equal to the number of stages of the integrators 11 and 12 in the main loop. It is a combination. [Embodiment] FIG. 2 is a circuit diagram showing an embodiment of the present invention, in which (A) and (
It is shown separately in B). (A) mainly shows integrators 11 to 14. The integrator 11-14 of this example takes the precaution of injecting charges according to the main signal and the feedback signal from various charge injection sections 61 to 64 into the integration circuit 60 which is a combination of the operational amplifier OP and the feedback capacitor CI. .

The charge injection parts 61 and 63 are main signal charge injection sources for charging and discharging the capacitor C2, and this capacitor Cz and the capacitor C of the integrating circuit 60,
The charge is redistributed between the two.

Four switches ■～■ are attached around the capacitor C.
A switched capacitor circuit is constructed.

Switch ■． ■ and switches ■ and ■ operate in opposite phases as a pair, and the capacitance is C! Establish a charging or discharging path for the In the charge injection parts 6l and 63, switches ■. ■ and ■
,■ are used in the opposite way. The first and second integrators 11.12 of the main loop use a charge injection section 61, and the third integrator 11.12 of the sub-loop
, fourth integrator 13. In l4, a charge injection section 63 is used. Therefore, the main signal is charged and discharged in opposite phases in the main loop and the sub loop.

The charge injection part 62 is the I!th! It is used to feed back the output F of the quantizer 31, and the charge injection section 64 is used to feed back the output F of the second quantizer 32.
It is used to feed back the output G of The charge injection section 62 has two capacitors Cs. Ca and its charge/discharge switch ■～■
, (9IQ, and charging is performed using a constant voltage Vss. The switch OIQ is a switch (2) with opening/closing conditions based on the output F of the first quantizer 31. With this structure, quantization The switch O+f can feed back the output F.
Depends on In other words, when the switches ■■ are turned on at the same time, the capacitor C is charged at Vss, and when the switch ■ is turned on next, only one of the switches ■ and (2) is turned on at the same time.

When the switch O is turned on, the charge is redistributed between the capacitor C4 and the charge is not injected into the integrating circuit 60 side. On the other hand, when the switch O is turned on, the charge is redistributed between the capacitor C+ and the charge is injected into the integrating circuit 60 side.

The charge injection part 64 consists of two capacitors Cs and Ch, and their charging/discharging switches (3),
Charging is also performed using constant voltage Vss. The switches Q and Q are the same as the switch (3) with opening/closing conditions based on the output G of the 21st child converter 32. In this circuit, the switch ■
When ■ is on, capacitor C & is charged, and when switch ■ is turned on, switch Q When turned on, the charge is redistributed to the capacitor CI and the charge is injected into the integrating circuit 60 side.

A charge injection section 62 is used in the first and second integrators 11.12, and a charge injection section 62 is used in the third and fourth integrators 13.14.
Use 4. Since these charge injection units 61 to 64 directly inject charges into the integrating circuit 60, the adder 21 in FIG.
24 can be omitted.

Furthermore, if the charge injection section 62 is used in the third integrator 13, the adder 25 can also be omitted.

FIG. 2(B) shows the first integrator 12 that quantizes the output of the second integrator 12.
The configuration after the quantizer 31 and the 21st childizer 32 that quantizes the output of the fourth integrator 14 is shown. Quantizer 31
．． 32 is a converter, which converts the input IP to the reference value I.
Compare it with M and output the result to the Q terminal. The timing ξ to quantize φ. φ1 is generated by the timing signal generation circuit 71.

The operations of the switches ■ to ■ mentioned above also occur at this timing φ1,
According to φ. However, the operation timings P+ and Pg of the switch (8>+8) are controlled by the first switch control section 72, and the operation timings of the switches e and (E) are controlled by the second switch control section 73.

The first switch control section 72 is a tie selection signal generation circuit 7.
Based on the output φ2 of l and the output F of the first quantizer 31, φ2
The timings P, , P, which are in opposite phases to each other at the timings of
Create. This P+. The level of Pz is inverted when the quantization output F is 1.0. The second switch control unit 73 uses the output φ of the timing signal generation circuit 7l and the output G of the second quantizer 32 to determine the timing P. ．． Output P4. This P,. Pa
The level is inverted at 1 and 0 of the quantized output G.

Differentiators 5l and 52 that differentiate the output G of the second quantizer 32
are composed of a flip-flop FF and an adder A each driven by a clock φ. Further, the corresponding delay devices 43 and 44 on the main loop side are constituted by flip-flops FF which are also driven by the clock φ1. Note that a delay device 45 with half the amount of delay (also an FF
) to perform strict phase matching.

(Effects of the Invention) As described above, according to the present invention, a Δ-Σ modulator having a fourth-order transfer characteristic is divided into a main loop that processes the main signal and a sub-loop that processes quantization noise. Since it is constructed as a second-order Δ-Σ modulator that operates stably, it has the advantage that low-frequency quantization noise can be compressed as much as possible with stable operation as a whole.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, FIG. 3 is a signal line diagram showing an example of a conventional quadruple integral type Δ-Σ modulator, and FIG. The figure is a characteristic diagram of an oversampling type A/D converter. In the figure, 11-14 are integrators, 2l to 26 are adders, and 31
．． 32 is a quantizer, 41 to 44 are delay devices, and 51.52 is a differentiator. Configuration diagram of the embodiment of the present invention jI2 (A) Figure 2 (B)

Claims (1)

[Claims] 1. A first integrator (11) that integrates the sampled analog input, a second integrator (12) that integrates the output of the first integrator, and the second integrator ( a first quantizer (31) that quantizes the output of 12) and provides negative feedback to the inputs of the first and second integrators (11, 12); and a quantization error of the first quantizer (31). A third integrator (13) that integrates the output of the third integrator (13), and a fourth integrator (13) that integrates the output of the third integrator (13)
4); a second quantizer (32) that quantizes the output of the fourth integrator (14) and negatively feeds it back to the inputs of the third and fourth integrators (13, 14); first and second differentiators (51, 52) that differentiate the output of the quantizer (32) twice; and the output of the second differentiator (52) and the first quantizer (31).
) calculation unit (26) that adds the outputs of
A fourth-order delta-sigma modulator comprising: