JPH03225695A - Memory card - Google Patents

Abstract

PURPOSE:To enlarge memory capacity and to prolong holding time by providing memory parts equipped with dynamic and static access memory chips and switching access to the both memory parts according to an address form an external part. CONSTITUTION:The memory parts is formed by a dynamic access memory chip (DRAM chip) group 1 with the large memory capacity and a static access memory chip (SRAM chip) group 2 with the long memory holding time. A bidirectional buffer 10 is connected to the DRAM chip group 1 and the SRAM chip group 2 and connected with an external terminal by an input/output data bit group 1002, it is selected by a DRAM controller 7 or a decoder 9 which chip group 1 or 2 is selected, chip group 1 or 2. Data to be held for a long time is stored in the SRAM and temporary data with large capacity is stored in the DRAM.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to memory cards.

[Conventional technology]

Conventionally, memory cards equipped with this type of RAM (random access memory) have mainly been S (static type) RAM cards, which have a long battery life. Also, as a floppy replacement, a D (dynamic type) RAM card with a large storage capacity was used.

[Problem to be solved by the invention]

The above-mentioned conventional memory cards have the disadvantage that the SRAM card has a small storage capacity, while the DRAM card has the disadvantage of a short battery retention period.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory card which solves the above-mentioned drawbacks, has a large storage capacity, and has a long retention period.

[Means to solve the problem]

The structure of the memory card of the present invention includes a memory section having a dynamic random access memory chip and a static random access memory chip;
A control means and switching of access of both chips,
The present invention is characterized in that it includes means for executing based on an address given from the outside.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a memory card according to an embodiment of the present invention.

In FIG. 1, only the parts related to this embodiment are shown.

The DRAM chip group 1 has an address signal line 501 which is outputted twice from the selector 5, an RAS pulse signal line 801 which accesses the DRAM, and a DRA hi.
From the CAS pulse signal line 703 from the control 7,
be accessed. At this time, the read take or write take flows to the input/output take signal line 1001 via the bidirectional buffer 10. In the SRAM chip group 2, some chips in the chip group 2 are enabled by a chip enable signal line 901 from the decoder 9. The chip in this - section is a chip block defined by the data width of the interface. Upper address bit group 10
The lower bit part of 0 and the lower address bit group 101 are:
Chip group 2 is accessed simultaneously. At this time, similarly to chip group 1, read data or write data flows to the data signal line 1001. Buffer 3 and buffer 4 each store an upper address and a lower address accessed from the outside in response to a timing signal 704 from DRAM controller 7. Upper address signal line 30 from buffer 3 and buffer 4
1 and lower address signal line 401 are output to selector 5. The two-man power selector 5 selects the upper address signal line 301 and the lower address signal line 401 according to the address switching signal 701 from the DRAM controller 7 and outputs the address signal line 501. refresh timer 6
counts the refresh period of the DRAM chip,
A refresh request signal 601 is sent to the DRAM controller 7 every time. The DRAM controller 7 is activated for access by an external access timing signal 102 and a group of upper address bits 100, and writes address 100 to address buffers 3 and 4, respectively.
A timing signal 704 for storing the address 101 and the address 101 is generated. In addition, the RAS signal group γ02 and CA
The address switching signal 70 is activated in accordance with the generation of the S signal group 703.
Generates 1. The decoder 8 decodes the RAS signal group 702 and decodes the RAS signal group 702 to select the DRAM chip group 1.
An AS decode signal 801 is generated. The decoder 9 inputs the upper bit part of the upper address hit group 100, and
It goes in and out of the chip enable signal line 901 of the SRAM chip group 2. The bidirectional buffer 10 has an input/output data line 10
It is connected to the DRAM chip group 1 and the SRAM chip group 2 by the input/output data hit group 1002, and to external terminals by the input/output data hit group 1002.

By the way, whether to access DRAM chip group 1 or S
Whether to access the R, A M chip group 2 is determined by the DRAM controller 7 that inputs the upper address bit group 100.
or determined by the decoder 9.

Battery 11 is used to hold the SRAM.

FIG. 2 is a block diagram of a memory card according to another embodiment of the present invention.

In FIG. 2, this embodiment differs greatly from the previous embodiment in that the DRAM controller 7 is not used. Instead, the controller 12 is installed, and the DRA, M
Controls access to the 3 o'clock address twice.

Control signals 701 and 704 are the same as in the previous embodiment. Also, the RAS signal 801. when accessing the DRAM. CA
The S signal 703 has the same timing as in the embodiment described above, but the feature of this embodiment is that it is sent from outside the memory card. In addition, in this embodiment, the decoder 8 in FIG.
．． The refresh timer 6 is also omitted. In Figure 2,
The same reference numerals as in FIG. 1 indicate similar blocks and similar signal lines.

〔Effect of the invention〕

As explained above, the present invention has a DR in the memory card.
By having AM and SRAM and separating them by address area, the large capacity of DRAM can be utilized when the memory card is connected to the device, and when the memory card is removed from the device, the SRAM This has the advantage that the data inside can be retained for a long period of time by the battery.

That is, in the present invention, the data to be held is accessed in the SRAM address area, and the transient data is accessed in the DRAM.
By accessing the address area of the memory card, the memory card can be used effectively.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a memory card according to one embodiment of the invention, and FIG. 2 is a block diagram showing a memory card according to another embodiment of the invention. 1...DRAM chip group, 2...SRAM
Chip group, 3.4... Buffer, 5...
Selector, 6... Refresh timer, 7...
... DRAM controller, 8, 9 ... Decoder, 10 ... Bidirectional buffer, 11 ... Battery, 12 ... Controller, 100 ...
...Upper address bit group, 101...Lower address bit group, 201...Mark - Battery line, 102...
...Access timing signal, 301...
- Upper address signal line, 401... Lower address signal line, 501... Address signal line, 601...
. . . Refresh request signal, 701 . . . Address switching signal, 702 . . . πAS- signal group,
703...CAS signal group, 801...
π■3-Decode signal, 901... Chip enable signal, 1001... Input/output data line, 1002...
...Input/output data pit group.

Claims (1)

[Claims] 1. A memory section having a dynamic random access memory chip and a static random access memory chip, a control means, and access switching of both chips provided externally. 1. A memory card characterized by comprising: means for executing according to an address assigned to the memory card. 2. The control means uses dynamic random access
The memory card according to claim 1, wherein the memory card controls a memory chip. 3. The control means uses dynamic random access
2. The memory card according to claim 1, wherein access control is performed twice on an address when accessing the memory chip.