JPH03223938A - Return address monitoring circuit for debugging device - Google Patents

Abstract

PURPOSE:To shorten the debugging time by providing a comparator to compare the return address saved in a stack area with the return address written into a storage circuit at call of a subroutine in a return state. CONSTITUTION:A comparator 4 compares in real time and in a return state the return address saved into a stack area at call of the subroutine of a microcomputer 1 to be debugged with the return address written into a storage circuit 9 at call of the subroutine. Thus both return addresses can be compared in real time with each other. As a result, an abnormal operation of the computer 1 is detected during a real time operation and then a program mistake is detected. In such a constitution, the debugging time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program error detection means for a debugging device that executes a program and corrects errors in the program.

[Conventional technology]

FIG. 2 is a configuration diagram showing a conventional debugging device, and shows an example of the configuration of a portion that detects values of an address bus and a data bus in real time.

In Figure 2, ■ is a microcomputer to be debugged, 2 is a device that responds to read/write cycles of the microcomputer (ROM, RAM, peripheral IC, etc.), and 3 is a detection specified by the user operating the debugging device. Comparison data latch 4 latches the desired address bus 5 and data bus 6 values, and address bus 5.4 latches the value of comparison data latch 3 and the microcomputer 1 output. A comparator 7 detects a match with the value on the data bus 6, and 7 is a control bus.

Next, the operation will be explained.

(2) The comparator 4 compares the value of the address bus 5 output by the microcomputer I to access the device 2 with the value set in the comparison data latch 3. When comparing,
If the signals on the control bus 7 output from the microcomputer 1 are also compared, it becomes possible to detect a specific access to a specific address of the microcomputer 1. Next, the coincidence detection signal is used to perform operations such as stopping program execution and starting real-time tracing.

(2) The comparator 4 compares the value of the data bus 6 when the microcomputer 1 reads/writes the device 2 with the value set in the comparison data latch 3. When comparing,
If the signals of the control bus 7 outputted from the microcomputer 1 are also compared, it becomes possible to detect specific access to specific data of the microcomputer 1. Then,
The coincidence detection signal is used to perform operations such as stopping program execution and starting real-time tracing.

(2) By combining (2) and (2) above, it becomes possible to detect operations such as reading and writing specific data to a specific address.

[Problem to be solved by the invention]

In conventional debugging devices, detection of writing of specific data to a specific address 1. Although it was possible to detect a specific access to a specific address, it was impossible to detect a match between the return address saved at the time of a subroutine call and the return address retrieved at the time of return.

The present invention has been made in view of these points, and its purpose is to monitor in real time whether the return address saved by the microcomputer at the time of subroutine call matches the return address retrieved by the microcomputer at the time of return. The purpose is to realize a debugging device.

[Means to solve the problem]

In order to achieve such an object, the present invention compares in real time at the time of return, the return address saved in the stack area at the time of a subroutine call of the microcomputer to be debugged and the return address written to the storage circuit at the time of the subroutine call. A comparison circuit is provided.

[Effect]

In the return address monitoring circuit of the debugging device according to the present invention, the return address saved by the microcomputer at the time of a subroutine call and the return address taken out by the microcomputer at the time of return are compared with the value of data saved to the stack area by the subroutine call instruction. This is done by sequentially storing the value of the address to which the value is written, and comparing the value of the data retrieved by the return command and the value of the address from which the value is read with the stored value.

〔Example〕

FIG. 1 is a block diagram showing a debugging device to which an embodiment of the return address monitoring circuit according to the present invention is applied.

In FIG. 1, only the parts directly related to the detection of matching of return addresses are shown.

In FIG. 1, 1 is a microcomputer to be debugged, 2 is a memory serving as a stack area, 4 is a comparison circuit, 5 is an address bus, 6 is a data bus, 7 is a control bus, 8 is a data bus 6, a control bus An instruction decoder monitors the bus 7 and detects subroutine call instructions and return instructions; 9 a storage circuit that stores data and address values saved by subroutine call instructions; 10 a debug device control unit that controls the entire debug device; It is. The comparison circuit 4 compares the data retrieved from the memory 2 by the return command and the value of its address with the corresponding value in the storage circuit 9.

Next, the operation of this embodiment will be explained with reference to FIG. When the microcomputer 1 executes the subroutine call instruction, the microcomputer 1 saves the return address in the memory 2. At the same time, the instruction decoder 8 detects the execution of the subroutine call instruction, and writes the return address value saved by the microcomputer 1 and the address of the memory used for saving into the storage circuit 9. The memory circuit 9 has a FILO (first in last out) circuit configuration in which the value written first is read out later. Reading from the storage circuit 9 is performed by executing a return command.

Next, when the microcomputer 1 executes the return instruction, it retrieves the return address from the memory 2. At the same time, the instruction decoder 8 detects the execution of the return instruction, and the comparator circuit 4 compares the address value outputted by the microcomputer 1 to retrieve the turn address, the data outputted by the memory 2, and the corresponding value of the storage circuit 9. compare.

If the values do not match, the comparison circuit 4 sends a mismatch detection signal a to the debugging device control section 10. The debugging device control unit 10 performs operations such as stopping the execution of the microcomputer 1, and the debugging device notifies the programmer of the mismatch of return addresses.

In addition, in the above embodiment, only the combination of the routine call instruction and the return instruction is shown, but in addition to this, the combination of the software interrupt instruction and the return instruction from the interrupt, and the hardware interrupt and interrupt caused by internal/external factors. A combination of return instructions from may also be used.

Furthermore, it goes without saying that the above three combinations may be used alone or in combination.

〔Effect of the invention〕

As explained above, the present invention compares the return address saved in the stack area at the time of the subroutine call and the return address written to the storage circuit at the time of the subroutine call in real time at the time of return.
It is possible to detect during real-time operation that the stack pointer changes due to a programming error and the microcomputer operates abnormally after executing a return instruction, and debugging time can be shortened by discovering programming errors. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a debug device to which an embodiment of the return address monitoring circuit according to the present invention is applied, and FIG. 2 is a block diagram showing a conventional debug device. ■...Microcomputer, 2...Memory, 4.
...Comparison circuit, 5...Address bus, 6...Data bus, 7...Control bus, 8...Instruction decoder, 9.
...Storage circuit, 10...Debug device control unit.

Claims (1)

[Claims] In a debugging device that executes a program and corrects program errors, the return address saved in the stack area at the time of a subroutine call of the microcomputer to be debugged and the return address written to the storage circuit at the time of the subroutine call are checked in real time at the time of return. A return address monitoring circuit for a debugging device, characterized by comprising a comparison circuit for comparing.