JPH03220945A - Packet buffer circuit and packet processing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention provides a packet buffer circuit and a packet processing circuit, and more specifically, a write/read control circuit and a packet signal processing circuit of a buffer memory circuit used in a fixed-length packet transmission/switching device. The present invention relates to a circuit configured using elements. In particular, A.T.
The present invention relates to a circuit suitable for processing cell signals using the M (asynchronous transfer mode) method. (Conventional technology 1) Regarding broadband and multimedia in the communication field,
ATM (asynchronous transfer mode) A agreed upon by CCITT (International Telegraph and Telephone Consultative Committee)
Synchronous Transfer Mode
In the "asynchronous transfer mode" method, fixed-length packets called cells are used for transmission/switching.At this time, cell Many buffer memory devices are used for primary storage of Even if it is treated as
The rate is approximately 20 MHz per byte. Furthermore, if you read and write to the buffer memory separately at different times,
High-speed operation of approximately 40 MHz is required. As a result, it is necessary to configure the buffer memory with a high-speed memory element, or to provide some kind of control circuit that reduces the effective operating speed. Conventionally, methods include using dual-port memory as the buffer memory to perform write and read operations at the same time, or preparing two systems of buffer memory and performing write and read operations while switching to different memories. has been used. In addition, regarding the method of preparing two systems of buffer memory, Japanese Patent Application Laid-open No. 1-16195
As with the device described in No. 0, multiple memory blocks that can be read and written independently are prepared, and when reading and writing are performed to the same block, jumps are made between writing blocks to reduce the amount of memory to the minimum required amount. A buffer memory control device that only adds one block to the buffer memory has also been proposed.

[Problems to be Solved by the Invention] The above-mentioned conventional technology aims at simultaneous execution of buffer read/write, both when using a dual port memory or FIFO, and when using a buffer memory control device. , it does not reduce the read/write rate itself. That is, the cell transmission speed directly becomes the read/write speed of the memory element or FIFO, and a high-speed memory element is still required. Further, as a method of lowering the operating speed of a memory element, the data width, ie, the number of parallel bits, is increased to lower the read/write frequency. However, in the case of an ATM cell, since the length of one cell is 53 bytes, it is not possible to widen the data width while maintaining the cell boundaries for consecutive cells. For example, 16
If the bit width is used, the last byte will have no partner to combine with, and the time allowed for access will be halved. This is because the number 53 bytes is a prime number. Therefore, in order to preserve the cell boundaries, the data width of 8 bits or more has no choice but to be 53 bits wide, and it is practically impossible to use an expanded data width. Furthermore, there is a method of adding extra data for aligning packet boundaries, but this requires special locks that are difficult to generate. An object of the present invention is to realize a buffer memory circuit that utilizes packet redundancy to enable processing with a wider data width while preserving boundaries. That is, when processing in units of cells, the circuit is configured such that the first byte signal of the primary cell is processed after the last byte of the cell is processed. Furthermore, by expanding the data width,
An object of the present invention is to realize a buffer memory circuit and a packet processing circuit for processing packet signals, which can be configured with low-speed circuit elements. Another object of the present invention is to enable the use of low-speed memory elements or FIFO memories without changing the amount of memory. Another object of the present invention is to provide a memory control circuit that can be applied without using clocks of different frequencies, which is difficult to create. That is, the purpose is to eliminate the need for a clock generation circuit that generates a clock with a slightly different frequency from the original read/write clock in order to add extra data necessary for alignment of packet boundaries when reading and writing from memory. [Means for Solving the Problems] In order to achieve the above object, the present invention provides a packet buffer circuit for temporarily storing fixed length packets, which includes: a) removing data at a certain position of the packet from the packet; b) a distribution parallelization unit that expands the remaining data of the packet to a data width twice that of the input data (k is an integer of 2 or more); b) while preserving the order relationship of write data and the order relationship of read data; a buffer memory that temporarily stores output data of the distributed parallelization section; C) means for storing said data removed from said packet; d) Set the data width of the output data of the buffer memory above ↓/
a multiplexing unit that reduces the size by k times and secures a space for storing the data read from the means; and e) inserts the data read from the means into the space in the output data of the multiplexing unit. The buffer memory is read and written at a speed 1/k times faster than when the buffer memory is read and written with a data width equal to the data width of the input packet. That is, the remaining data length is set to be an integral multiple of the read/write data width of the buffer memory. If the input data includes a check code at a specific position in the packet, the data to be removed from the packet is part or all of the check code. In that case, even if the means to save the data to be removed is memory,
It may be configured with a calculation circuit that recalculates the code corresponding to the removed check code from the data read from the buffer memory. Furthermore, the buffer memory may be a signal processing circuit as long as the input/output order relationship is maintained.

[Function 1] According to the present invention, the read/write speed of the buffer memory is 1/k of the input/output data speed, and the buffer memory can be constructed of low-speed circuit elements. Since the amount of packet data (remaining data) read and written to the buffer memory is an integral multiple of the read/write data width, packet boundaries are preserved. Furthermore, when the packet is an ATM cell, there are the following advantages. For example, an ATM cell with a length of 53 bytes has a 1-byte header error check code (CR).
C) code is included, so if the check code is removed, the length can be 52 bytes. As a result, if the data width is set to 16 bits, the cell can be handled as 26 words long, and if the data width is set to 32 bits, the cell can be handled as 13 words long. In other words, a 16-bit width reduces the read/write speed by half, and a 32-bit width reduces the read/write speed by half.
The F loading speed can be reduced to 1/4. The removed check code does not need to be read or written to the memory separately; it is essentially included in the header within the cell, and can be created by recalculation from the header read from the buffer memory. [Examples] Examples of the present invention will be described below. FIG. 1 is a block diagram showing the configuration of an embodiment of a packet buffer circuit according to the present invention. The packet buffer circuit consists of an input section, a buffer memory 1, and an output section. On the input side, an n-bit parallel input data signal 101 is combined with an input timing signal 102 indicating the beginning of a packet and input to the distribution parallelization unit 2. The distribution parallelization unit 2 removes the check code from the input packet (input data signal 101), as will be explained in detail with reference to the embodiment shown in FIG. If a check code exists in the middle of a packet, the space after removing the check code is filled up. Furthermore, the distribution parallelization unit 2 removes the check code and at the same time changes the data width of the input data signal 101. Here, the data width is doubled (k is an integer of 2 or more), that is, the output data 107 is kn-bit parallel. The output data 107 whose data width has been doubled is temporarily written to the first-in first-out memory (FIFO memory) 1. At this time, writing to the memory 1 is controlled by the write clock 103 of the FIFO memory 1. The write clock 103 of the FIFO memory 1 has a clock frequency corresponding to the packet length obtained by removing the check code from the packet. The FIFO memory 1 receives an input timing signal 10 to indicate the beginning of the written packet.
2 are also written at the same time, but after being given a delay by the input timing signal delay unit 6 corresponding to the delay of the input data in the distribution parallelization unit 2, they are written to the FIFO memory l. At the output section of the buffer memory circuit, the output data 109 read out according to the read clock 106 of the FIFO memory 1 is returned to the original n-bit parallel signal 112 in the multiplexing section 6. In part 3,
A space is reserved at the position where the check code should be placed. At the same time as the multiplexing unit 3 restores the data width to the original value, the check code recalculation unit 4 recalculates the check code to be added to the output data 109 of the FIFO memory 1. Check code addition section 5
Now, for the packet data signal 112 that has been restored to its original data width by the multiplexer 3, the check code of the input packet data is located at the original position. The check code 111 recalculated by the check code recalculation unit 4 is inserted. As a result, the restored packet data is output from this packet buffer circuit as an output data signal 104. Furthermore, the timing signal 110 indicating the start position of the packet data read out from the FIFO memory 1 is used to generate operation timings of the multiplexing unit 3, check code recalculating unit 4, and check code adding unit 5, and at the same time, A delay commensurate with the processing is given by the output timing signal delay section 7, and output from the present packet buffer circuit as an output timing signal 105. Further, the read clock 106 of the FIFO memory 1 is the write clock 1 of the FIFO memory 1.
03, it has a frequency corresponding to the packet length after removing the check code from the packet data. FIG. 2 shows a timing chart when the above-mentioned packet buffer circuit is applied to an ATM cell. The ATM cell has a cell length of 53 bytes, and the 5th byte contains the CRC code for the 1st to 4th byte headers.
Exists as a check code. In the following explanation, it is assumed that the ATM cells are inputted in 8-bit parallel fashion, and that the integer k indicating the degree of parallelization is k=2. The input data signal to this packet buffer circuit is 1
The data length is 53 bytes per cell. After removing the check code of the fifth byte from this cell, the first two bytes are combined to form 16-bit parallel data, and this data is used as write data in the FIFO memory 1. In other words, the write data in FIFO memory 1 is combined as the 1st and 2nd bytes, 3rd and 4th bytes, 6th and 7th bytes, and 8th and 9th bytes of the original bucket. Parallelize to 16 bits. This write data is temporarily written to FIF○ memory 1, the output data of FIFO memory 1 that has been read is returned to 8-bit parallel data, and a data string is created with a space left so that a check code can be placed in the 5th byte of the returned result. becomes the multiplexer 3 output 112. Furthermore, the output of the check code recalculation section (ECC calculation) 4 is inserted into the fifth byte of the output of the multiplexing section 3, and this is used as the output data signal 104 of the present packet buffer circuit. The output timing signal 104 is given an appropriate delay and is output in synchronization with the output data signal 105. FIG. 3 is a block diagram showing the configuration of another embodiment of the packet buffer circuit according to the present invention. In this example, the first
F of the packet buffer circuit shown in the figure, IFO memory 1
, a random access memory (RAM) 8 , a write address generator 10 , a read address generator 11 .
and an address selection section 9. Since the other parts are substantially the same as those in the embodiment shown in FIG. 1, the same parts are given the same numbers and the explanation will be omitted. The write clock 103 operates a counter in the write address generator 10 and provides the current write address 114 of the RAM 8. Similarly, according to the read clock 106, the read address generator 11
Give read address 115 of M8. The write address 114 and the read address 115 are time-division multiplexed by the address selection section 9 and provided to the RAM 8. As mentioned above, the RAM 8, the write address generation section 10,
Read address generation unit 11. The address selection unit performs the same operation as the FIF◯ memory 1. FIG. 4 is a block diagram showing the configuration of one embodiment of the distribution parallelization section 2 shown in FIGS. 1 and 3. In FIG. The configuration and operation of the distribution parallelization section 2 shown in FIG. 5 will be explained below using the timing chart shown in FIG. The input data signal 101 to the distribution parallelizer 2 is passed to the data selector 22 either as is or after being latched by the D-type flip-flop 21 . Here, the input data signal 101 and the data signal 202 delayed by one clock are selected by the selector 22, and the check code is removed as described below. That is, the data signal 202 delayed by one clock is used before the check code, and the data signal 101 is used after the check code. By switching these data signals, the data signal in the portion where the check code was present is removed, and the space is filled. The output signal 204 of the selector 22 has a frequency that is 1/2 of the clock frequency of the input data (referred to as 1/2 clock).
Each byte is latched by the D flip-flop 23 using a clock 206 in which the polarity of the clock 205 is inverted. At this time, the output 204 of the selector 22 and the D flip-flop 2
The output 207 of 3 is output by the D flip-flop 24,
It is latched again at 1/2 clock 205, so 16
A bit parallelized data signal 107 is obtained. This data signal 107 is written into the FIFO memory 1 using the write clock 103 as described above. FIG. 6 is a block diagram showing the configuration of one embodiment of the multiplexing section 2 shown in FIGS. 1 and 3 above. The multiplexer 2 shown in FIG. 6 will be explained below using the timing chart shown in FIG. Input data 10 from FIFO memory 1 to multiplexer 3
9 is synchronized with the system timing clock by a D flip-flop 31. Thereafter, the data is input to the data selector 32. The 8 bits in the even numbered byte and the 8 bits in the odd numbered byte in the cell are passed separately. The data selector 32 uses the 1/2 clock 301 to output 8 bits for odd numbered bytes and 8 bits for even numbered bytes with a time shift. For the output 303 of the data selector 32, it is determined whether it is output as is or after being delayed by one clock in the D flip-flop 33.
Determined by data selector 34. The control of the data selector 34 is to free up a space for the check code, and the purpose is to delay the data after the check code is inserted by one clock. That is, before the check code, the output 303 of the data selector 32 is used as is, and after the check code, the output 305 of the D flip-flop 33 delayed by one clock is used. The fifth byte, which contains the check code, has the same content as the fourth byte, but the check code is inserted instead. The embodiments of the packet buffer circuit according to the present invention have been described above with particular reference to ATM cell data. As another example, the function that plays the same role as the FIFO memory 1 can be achieved by using a dual port memory or the like.
It can be realized. Furthermore, in the above embodiment, the check code is recalculated on data read from the buffer memory 1, that is, on data whose data width has been expanded. However, even if the check code is calculated after restoring the data width to the original value, the same result can be obtained only by changing the configuration of the check code recalculation circuit. The configuration of an embodiment in such a case is shown in FIG. In the configuration shown in FIG. 8, the calculation target of the check code recalculation unit 4' is not the output data 109 of the FIFO memory 1 but the output 112 of the multiplexing unit 3. This is similar to the embodiment shown in the figure. Furthermore, as shown in FIG. 8, a packet processing circuit is provided between the multiplexer 3 and the check code recalculator 4' for processing the packets, such as reading and writing data in the packets and disassembling/reconfiguring the packets. 12 may also be provided. That is, if the packet processing circuit 12 does not refer to the check code originally added by the check code adding section 5, adding the check code may be delayed. Therefore, the check code can be recalculated and added, for example, at the exit of the module equipped with the present buffer circuit. With such a configuration, for example, the distribution parallelization unit 2, buffer memory 1, and multiplexing unit 3 of this circuit are serially connected as a set, and a packet processing circuit is added between them to perform packet buffering and packet internal processing. It is also possible to perform data processing alternately. Further, by inserting the packet processing circuit 12 before the multiplexing section 3, it is also possible to perform packet processing at a low slew rate. Furthermore, in this application, the buffer memory 1 may not be used and the packet processing circuit may be replaced with a packet processing circuit. By configuring the packet processing circuit in this way, it is possible to reduce the processing slew rate. Furthermore, in the above explanation, the check code is removed (although the embodiment was described, the removed check code is stored in another memory, and by comparing it with the check code recalculated from the output data of the buffer memory, the data stored in the buffer memory is It is possible to check for bit errors that occur in the memory input/output section. In this case, since the separate memory only stores one check code in the e-packet, it is configured as a low-speed memory. Furthermore, such a packet buffer circuit with a comparison function also performs a checking function for bit errors occurring on a transmission path, so that it can serve both the packet buffer function and the bit error checking function. This is because when a check code is recalculated for a packet in which a bit error has occurred, a discrepancy occurs between the check code and the original check code. Furthermore, if a separate memory is prepared, the data removed from the packet is saved, making it possible to remove data other than the check code. That is, the packet length can be adjusted for expanding the data width by removing data at a certain position and storing it in a separate memory. In this case, the access speed of the separate memory can also be lower than the packet slew rate, and the expansion of the data width also reduces the access speed of the original buffer memory.
It is possible to obtain the same effect as when the check code is removed. The embodiments in which the packet buffer circuit is configured have been described above, but one feature of the present bucket buffer circuit is that there is no change in the contents of packets input and output from the packet buffer. Therefore, by creating a semiconductor memory having this circuit in the peripheral logic circuit of the memory cell, it is possible to configure a packet memory LSI with a reduced access speed of internal memory cells, while the external interface is the same as when the present invention is not used. . As a result, it becomes possible to reduce the price of the packet memory LSI. Figure 9 shows a space switch type AT with an input buffer circuit.
A basic configuration diagram of the M exchange is shown. That is, the ATM cells arriving at the input lines 116-1 to 116-m are sent to the space switch 14 through the input buffer circuits 13-1 to 13-m.
is input. The space switch 14 determines the destination based on the address information written in the header of the ATM cell, and outputs the cell to the corresponding outgoing lines 118-1 to 118-m. Here, the input buffers 13-1 to 13-m have the role of preventing cells from colliding and being lost inside the space switch 14 when cells arrive from a plurality of incoming lines. If the buffer memory circuit according to the present invention is used in the input buffers 13-1 to 13-m of an ATM exchange, memory elements with slow operating speeds can be used, and even when a large amount of buffer memory is required, it can be achieved economically. Able to configure equipment.

【Effect of the invention】

According to the present invention, since the data width can be changed without dropping necessary information in the packet, it is possible to reduce the operating speed of the processing circuit for the packet. In other words, if applied to a memory circuit that performs packet buffering, it is possible to use a memory element with several times longer access time or a similarly slow FIFO.
Since memory can be used, the device can be made economically. For example, if applied to the buffer circuit of an ATM cell, the access time can be halved or quartered.
memory buffer can be used. In other words, even for a 150 Mb/s signal, when the width is 8 bits, the processing per word is about 50n.
However, by widening the data width, processing within 100 ns or 200 ns is sufficient. Furthermore, according to the present invention, the actual signal processing speed can be reduced without increasing the amount of memory required. Furthermore, since check codes are not stored, the amount of memory required can be reduced. Furthermore, in the present invention, check codes are removed. Difficult to generate, such as those used in methods that increase extra data for packet boundary alignment. No special lock signal required. According to the present invention, it is possible to easily and inexpensively provide a buffer circuit for an ATM cell used in a wideband I5DN.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the buffer circuit according to the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1, and FIG. 3 is another embodiment of the buffer circuit according to the present invention. FIG. 4 is a circuit diagram of one embodiment of the distribution parallelization section in FIG. 1, FIG. 5 is a timing chart of the distribution parallelization section in FIG. FIG. 7 is a timing chart for explaining the operation of the circuit in FIG. 6, FIG. 8 is a block diagram of still another embodiment of the present invention, and FIG. 9 is a circuit diagram of an embodiment of the present invention. 1 is a block diagram of an input buffer space switch type ATM exchange using a buffer circuit according to the present invention. 1... FIFO memory, 2... Distribution parallelization section, 3... Multiplexing section, 4, 4'...
・Check code recalculation unit 5...Check code addition unit, 6...Input timing signal delay unit, 7...
...Output timing signal delay section. 8...RAM, 9...Address selection section, 10...Write address generation section, 11...
. . . Read address generation section, 12 . . . Packet processing section. 13-1~m...Input buffer, 14...
・・m×m space switch. 21.23.24.31.33 ......D type flip-flop 22...
Data selector, 25...NOT element 32.3
4...Data selector, 101...Input data signal, 102...Input timing signal, 103...
... FIFO memory write clock signal, 104.
...Output data signal, 105...Output timing signal, 106...
...FIFO memory read clock signal. 201...System clock signal, 203...
...Selector control signal, 2.05.301...
... 1/2 clock signal, 304 ... system clock signal, 306 ... selector control signal.

Claims (1)

[Scope of Claims] 1. In a packet buffer circuit that temporarily stores fixed-length packets, data at a certain position of the packet is removed from the packet, and the remaining data of the packet is converted to the input data width of the input data. a distributed parallelization unit that converts the data into data with a data width that is an integral multiple of , a buffer memory that temporarily stores the output data of the distribution parallelization unit while preserving the data order relationship, and data removed from the packets. a data storage means for storing the data; and a multiplexer for returning the data width of the output data of the buffer memory to a width equal to the data width of the input data of the distribution parallelization unit and securing a space for storing the data stored by the data storage means. A packet buffer circuit comprising a converting section and a selecting section for inserting the data stored by the data storage means into the space in the output data of the multiplexing section. 2. The packet buffer circuit according to claim 1, wherein said data storage means is constituted by a circuit that creates the same data as the data removed by said distribution parallelization section from the output of said buffer memory. 3. The packet buffer circuit according to claim 1, wherein said data storage means is constituted by a memory. 4. In a packet buffer circuit that temporarily stores a fixed-length packet containing a check code whose position is fixed, at least a part of the check code of the packet is removed, and the remaining data of the packet is converted into a packet with an input data width of k. (
(k is an integer) times the data width; a buffer memory that stores the output data of the distribution parallelization unit while preserving the order relationship of the written data and the order relationship of the read data; A check code recalculation unit that recalculates the check code for the output data of the buffer memory, and a check code recalculation unit that reduces the data width to 1/k times for the output data of the buffer memory to secure space for the check code. 1. A packet buffer circuit comprising: a multiplexing section that performs the check code recalculation section; and a selection section that inserts the check code from the check code recalculation section into the space secured by the multiplexing section and obtains output data. 5. The packet buffer circuit according to claim 4,
The packet buffer circuit is configured such that the check code recalculation section recalculates the check code on the output data of the multiplexing section instead of the output data of the buffer memory. 6. The packet buffer circuit according to claim 4 or 5 further includes a check code memory for storing the check code removed by the distribution parallelization unit, and a check code recalculated by the check code recalculation unit. and a check code read from the check code memory, and further includes a test circuit for checking for changes or errors in data in the buffer memory. 7. In claim 6, the test circuit further comprises:
A packet buffer circuit that has a bit error inspection function in the transmission path. 8. The packet buffer circuit according to claim 4, wherein the packet is an asynchronous transfer mode (ATM) cell. 9. The packet buffer circuit according to claim 4, wherein the buffer memory is a FIFO memory. 10. In the fourth, fifth, sixth or seventh claim,
The buffer memory includes a random access memory, a write address generator that generates a write address for the random access memory, a read address generator that generates a read address for the random access memory, and an output of the write address generator. and an address selection section for selectively applying the output of the read address generation section to the random access memory. 11. In the fourth, fifth, sixth or seventh claim,
The buffer memory includes a dual-port random access memory, a write address generation section that generates a write address for the random access memory, and a read address generation section that generates a read address for the random access memory. Packet buffer circuit. 12. In a packet buffer circuit that temporarily stores fixed-length packets containing check codes whose positions are fixed, the packet length is adjusted by removing part or all of the check code from the input packet, and the packets are separated. When expanding the data width of the packet while maintaining the above-mentioned data width, reducing the writing/reading speed of the buffer memory, and returning the data width of the output of the buffer memory to the original data width of the packet, the check code is A packet buffer circuit characterized by restoring data from output data of a buffer memory. 13. In a packet buffer circuit that temporarily stores a fixed-length packet containing a check code whose position is fixed, part or all of the check code of the packet is removed, and the remaining data of the packet is means for temporarily storing the output of the data width expanding means while preserving the order relationship of the written data and the order relationship of the read data; means for restoring the data width to the original value and securing a space for storing the result of recalculating the check code; recalculating means for recalculating a new check code for the output data of the storing means; and the space for recalculating the check code. A packet buffer circuit comprising: means for embedding the check code calculated by the recalculation means. 14. In a packet processing circuit that processes a fixed-length packet containing a check code whose position is fixed, at least a part of the check length code of the packet is removed, and the remaining data of the packet is converted into k(k) of the input data width. is an integer); a data processing circuit that processes the output data of the above distribution parallelization section; and a check code recalculation for the output data of the above data processing circuit. a check code recalculation section that reduces the data width to 1/k times the data width of the output data of the data processing circuit to secure a space for the check code; and a selection section for inserting the check code from the check code recalculation section into the space provided by the check code recalculation section to obtain output data.