JPH03220661A - System for communication between processors - Google Patents

Abstract

PURPOSE:To always detect the abnormality of communication between processor within optimum monitor time by transmitting the state of a processing at a receiving destination when receiving a command by the processor at the receiving destination, and an optimum time-out time length corresponding to the kind of the command to the processor at a device source. CONSTITUTION:When the command is issued from a processor 100, the command is set to a CMR register 6 of a processor 1 by a strobe signal 12 and this command is analyzed by a decoder 8 and informed to a control circuit 9. The control circuit 9 recognizes the internal state of the processor 1 at that time point by a status line 2 and corresponding to the received command, the optimum time-out time length is sent out to an RDAT register 10. This data is sent out through a bidirectional bus 3 to the processor 100 and based on the received data (time-out time length), the processor 100 starts time-out time monitor. Thus, the abnormality of communication between processors can be always detected within the optimum monitor time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a communication system between processing units of a computer system consisting of a plurality of processing units, and particularly to a method for monitoring communication abnormalities between processing units. , relates to a communication system between processing devices that monitors a timeout from when a source processing device issues a command to when a destination processing device completes processing of the command and returns a response.

[Conventional technology]

Conventionally, timeout monitoring in this type of communication system has been performed by the source processing device by determining a fixed time based on the maximum processing time, regardless of the state or command of the destination processing device.

[Problem to be solved by the invention]

Timeout monitoring using the conventional communication method described above uses a fixed timeout time, ignoring the status of the receiving processing device and the type of command. Even if the command completes processing, timeout monitoring is set in seconds to avoid false detection of a timeout even if the destination processing device happens to be busy with other processing and cannot respond.

For this reason, it takes time to detect a communication abnormality between processing devices by monitoring the timeout period, and error recovery processing is delayed, resulting in a delay in the execution of related jobs on the computer system.

[Means to solve the problem]

The communication method between processing devices of the present invention is a communication method between processing devices of a computer system consisting of a plurality of processing devices, in which each processing device has a receiving means for receiving commands, and a command set in the receiving means. an analysis means for analyzing the command, a control circuit for calculating a timeout time corresponding to the type of command analyzed by the analysis means and the state of the receiving processing device, and sending the timeout time calculated by the control circuit to the source processing device. When a command is received from the source processing device, the timeout period calculated by the control circuit is reported to the source processing device.

[Effect]

In the present invention, when a command is received by a destination processing device, an optimal timeout period corresponding to the state of the destination processing at that time and the type of command is sent to the source processing device.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, reference numerals 1 and 100 indicate processing units, and the processing units 1 and 100 have an interface consisting of a bidirectional bus 3 and a control line 4.5. Here, the processing device 10
The internal structure of 0 is the same as that of processing device 1, so it is omitted. 2 is a status line.

A CMR register 6 receives commands from the data bus 3, and this CMR register 6 constitutes receiving means for receiving commands. 7 is a WDAT register that receives data from the data bus 3; 8 is a decoder connected to the output of the CMR register T; this decoder 8 constitutes analysis means that analyzes the command set in the above-mentioned receiving means. .

Reference numeral 9 denotes a control circuit that calculates an optimal timeout time length according to the internal state signal of the processing device 1 from the status line 2 and the type of command and code from the decoder 8, and sends the value to the RDAT register 10. The circuit 9 is configured to calculate a timeout time corresponding to the type of command analyzed by the analysis means and the state of the reception processing device.

The RDAT register 10 is a register that holds transmission commands/data and responses, and the RDAT register 10 constitutes a means for transmitting the timeout time calculated by the control circuit 9 to the source processing device □.

Reference numeral 11 denotes an interface control circuit. This interface control circuit 11 controls communication with other processing devices through a control line 4.5, and controls a CMR register 6 and a WDAT register 7.
a system which generated the strobe signals 12 and 13 for the
It is configured to output a strobe signal 14 onto the interface in response to an instruction from the control circuit 9.

When a command is received from the source processing device, the timeout time calculated by the control circuit 9 is reported to the source processing device.

Figure 2 is a time chart used to explain the operation of Figure 1.
-) shows the bidirectional bus 3, 1 (b) is the strobe signal 12, (c) is the strobe signal 14, (d)
shows the strobe signal 13.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2. Here, a case where the transmission source is the processing device 100 and the reception destination is the processing device 1 will be described.

First, when a command is issued from the processing device 100, the command is set in the CMR register 6 of the processing device 1 by a strobe signal 12 (see FIG. 2). This command is then analyzed by the decoder 8 and reported to the control circuit 9. The control circuit 9 recognizes the internal state of the processing device 1 at that time from the status line 2, and determines the optimum timeout time length 'zRD corresponding to the received command.
Send to AT register 10. This data is sent to processing device 100 via bidirectional bus 3. At the same time, a strobe signal 14 (see FIG. 2(c)) is used as a signal to strobe the data on the processing device 100 side.
is generated and sent.

Next, the processing device 100 starts timeout time monitoring based on the received data (timeout time length).

The data associated with the command is subsequently sent from the processing device 100 to the WDAT register 7 of the processing device 1 via the bidirectional bus 3, and the data is sent to the WDAT register T by the strobe signal 13 (see FIG. 2(d)). are set one after another.

If there is no abnormality, the operation within the processing device 1 is completed within the timeout monitoring period, and the response is reported to the processing device 100 from the control circuit 9 through the RDAT register 10 button and the bidirectional bus 3. 100 ends timeout monitoring. Here, if an abnormality occurs in the processing device 1 and a response is not sent back to the processing device 100,
The processing device 100 detects the time delay and immediately performs recovery processing.

〔Effect of the invention〕

As explained above, when a command is received by a destination processing device, the present invention sends an optimal timeout length corresponding to the state of the destination processing at that time and the type of command to the source processing device. This has the effect that communication abnormalities between processing devices can always be detected within an optimal number of hours.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. 1...Processing device, 2...Status line, 3...
...Bidirectional bus, 4,5...Control line, 6...C
MR register, γ...WDAT register, 8...
・Decoder, 9...control circuit, 10...RDA
T register, 11...Interface control circuit, 1
00...Processing device.

Claims (1)

[Claims] In a communication system between processing units in a computer system consisting of a plurality of processing units, each processing unit has a receiving unit for receiving commands, an analyzing unit for analyzing the command set in the receiving unit, and a communication unit for analyzing commands set in the receiving unit. A control circuit that calculates a timeout time corresponding to the type of the analyzed command and the state of the reception processing device, and a means for sending the timeout time calculated by the control circuit to the source processing device, from the source processing device to the source processing device. A communication system between processing devices, characterized in that when a command is received, a timeout time calculated by the control circuit is reported to the source processing device.