JPH0322059B2 - - Google Patents
Info
- Publication number
- JPH0322059B2 JPH0322059B2 JP56113708A JP11370881A JPH0322059B2 JP H0322059 B2 JPH0322059 B2 JP H0322059B2 JP 56113708 A JP56113708 A JP 56113708A JP 11370881 A JP11370881 A JP 11370881A JP H0322059 B2 JPH0322059 B2 JP H0322059B2
- Authority
- JP
- Japan
- Prior art keywords
- glass
- package
- bull
- top surface
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011521 glass Substances 0.000 claims abstract description 41
- 239000000919 ceramic Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000008188 pellet Substances 0.000 claims abstract description 9
- 244000309464 bull Species 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 4
- 238000007747 plating Methods 0.000 abstract description 3
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/50—Encapsulations or containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はパツケージの上面にUVガラスからな
るブルズアイを有する紫外線透過形パツケージの
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in an ultraviolet transmitting package having a bull's eye made of UV glass on the top surface of the package.
所謂Ep−ROM等に紫外線透過形パツケージの
半導体装置は、その機能上パツケージの上面に
UVガラスからなるブルズアイを設けている。と
ころが、第１図に示すように従来のこの種のパツ
ケージでは、セラミツクベースとセラミツクキヤ
ツプを低融点ガラスにて接着しかつリードを突出
形成したパツケージ本体の上面よりも突出するよ
うにしてUVガラスを設けているため、他部品や
その他のものにUVガラスが干渉し易く半導体装
置の信頼度、完成外観に問題が生じる。例えば、
リードのめつき工程でのバレル内で他のパツケー
ジのセラミツクにUVガラスが接触ないし衝突し
てガラスに傷やクラツクが発生し、あるいは顧客
の受入れ工程でのハンドラにおいてパツケージの
上面を滑るような場合に同一モード不良が発生す
る。 Semiconductor devices in ultraviolet-transmissive packages, such as so-called Ep-ROMs, require that the upper surface of the package be protected due to their functionality.
A bull's eye made of UV glass is provided. However, as shown in Figure 1, in this type of conventional package, the ceramic base and ceramic cap are bonded together using low-melting glass, and the UV glass is made to protrude beyond the top surface of the package body, which has protruding leads. Because of this, the UV glass tends to interfere with other parts and objects, causing problems with the reliability of the semiconductor device and the finished appearance. for example,
If the UV glass contacts or collides with the ceramic of another package in the barrel during the lead plating process, causing scratches or cracks on the glass, or if the glass slides on the top surface of the package in the handler during the customer's receiving process. Same mode failure occurs.
したがつて本発明の目的は、ブルズアイ構成す
るUVガラスの断面形状を変更してガラス表面が
パツケージの上面より低い位置となるように構成
することにより、UVガラスと他物品との接触な
いし衝突を防止し、これによりUVガラスの傷、
クラツク、欠け等を防いで高信頼性かつ良外観の
製品を得ることができる紫外線透過形パツケージ
の半導体装置を提供することにある。 Therefore, an object of the present invention is to change the cross-sectional shape of the UV glass constituting the bull's eye so that the glass surface is lower than the top surface of the package, thereby preventing contact or collision between the UV glass and other objects. This prevents UV glass scratches,
An object of the present invention is to provide a semiconductor device in an ultraviolet-transmissive package that can prevent cracks, chips, etc., and provide a product with high reliability and good appearance.
以下、本発明の一実施例を第１図および第２図
に基づいて説明する。 Hereinafter, one embodiment of the present invention will be described based on FIGS. 1 and 2.
図において、２はセラミツクベースであり、そ
の上面中央凹部２ａの底面には半導体ペレツト３
を固着する一方、周辺には外部導出用の複数本の
リード線４を整列配置して低融点ガラス５にて支
持している。これらリード４には前記半導体ペレ
ツト３との間にワイヤ６を接続して導通を図つて
いる。７は前記セラミツクベースの上部を覆うよ
うにして固着するセラミツクキヤツプであり、周
辺において低融点ガラス８により固着し、これに
よりパツケージ本体１を構成している。前記セラ
ミツクキヤツプ７は半導体ペレツト３に対応する
位置に円形の透孔（窓）９を形成し、この孔９内
にはブルズアイガラスとしてのUVガラス１０を
嵌め込んで固着している。そして、本発明ではこ
のUVガラス１０の表面を凹面状に形成し、かつ
その表面がセラミツクキヤツプ７の上面、つまり
パツケージ本体１の上面よりも低い位置になるよ
うに設定しているのである。 In the figure, 2 is a ceramic base, and a semiconductor pellet 3 is placed on the bottom of the central recess 2a on the top surface.
At the same time, a plurality of lead wires 4 for leading out to the outside are aligned and supported by a low melting point glass 5 around the periphery. Wires 6 are connected between these leads 4 and the semiconductor pellet 3 to establish electrical continuity. A ceramic cap 7 is fixed to cover the top of the ceramic base, and is fixed at the periphery by a low melting point glass 8, thereby forming the package body 1. The ceramic cap 7 has a circular hole (window) 9 formed at a position corresponding to the semiconductor pellet 3, and a UV glass 10 as a bull's eye glass is fitted into the hole 9 and fixed therein. In the present invention, the surface of the UV glass 10 is formed into a concave shape, and the surface is set to be lower than the top surface of the ceramic cap 7, that is, the top surface of the package body 1.
この場合、UVガラス１０の表面は平面、凹面
であつてもよいが、その最上面は必ずパツケージ
本体１の上面よりも低い位置になるようにしなけ
ればならない。また、UVガラス１０はセラミツ
クキヤツプ７の孔９内に嵌め込んだ上で低融点ガ
ラス８によるセラミツクキヤツプ７の加熱溶着時
に同時にUVガラス１０の周辺を溶融させること
により固着を行なうことができる。 In this case, the surface of the UV glass 10 may be flat or concave, but the top surface must always be at a position lower than the top surface of the package body 1. Further, the UV glass 10 can be fitted into the hole 9 of the ceramic cap 7 and then fixed by melting the periphery of the UV glass 10 at the same time as the low melting point glass 8 is heat welded to the ceramic cap 7.
以上の構成によればUVガラス１０の表面はパ
ツケージ本体１の上面から突出していないため、
めつき時やその他の処理においてUVガラス１０
が他部品（マガジン、ハンドア、他のパツケー
ジ）に接触ないし衝突することはなく、したがつ
てUVガラスの傷やクラツク、欠け等を防止する
ことができ、信頼性、外観の向上を図り歩留の向
上をも達成できる。また、UVガラス１０と他部
品との接触摩擦により発生する静電気がUVガラ
スからペレツト３上に帯電してソフトエラーを生
じさせることをも防止することができる。 According to the above configuration, the surface of the UV glass 10 does not protrude from the top surface of the package body 1, so
UV glass 10 during plating and other treatments
The UV glass does not come in contact with or collide with other parts (magazine, hand door, other package cages), thus preventing scratches, cracks, chips, etc. on the UV glass, improving reliability and appearance, and improving yield. It is also possible to achieve improvements in Furthermore, it is possible to prevent static electricity generated by contact friction between the UV glass 10 and other parts from being charged on the pellet 3 from the UV glass and causing a soft error.
以上のように本発明の半導体装置によれば、ブ
ルズアイガラスとしてのUVガラスの表面をパツ
ケージ本体の上面よりも低くなるように構成して
いるので、UVガラスが他部品と干渉して傷やク
ラツクが発生することはなくまたペレツトへの帯
電を防止してソフトエラーをも防止することがで
きるので、外観が良好でかつ信頼性を向上するこ
とができるという効果を奏する。 As described above, according to the semiconductor device of the present invention, the surface of the UV glass as the bull's eye glass is configured to be lower than the top surface of the package body, so the UV glass may interfere with other components and cause scratches or cracks. Since the pellets are prevented from being charged and soft errors are also prevented, the appearance is good and the reliability is improved.
第１図は本発明の半導体装置の上面図、第２図
は第１図の−線断面図である。
１……パツケージ本体、２……セラミツクベー
ス、３……ペレツト、４……リード、７……セラ
ミツクキヤツプ、１０……UVガラス（ブルズア
イガラス）。
FIG. 1 is a top view of a semiconductor device of the present invention, and FIG. 2 is a sectional view taken along the line -- in FIG. 1... Package body, 2... Ceramic base, 3... Pellet, 4... Lead, 7... Ceramic cap, 10... UV glass (bull's eye glass).
Claims (1)
クベースと、前記半導体ペレツトに照射すべき紫
外線を透過するためのUVガラスが嵌め込れた孔
を有して前記セラミツクベースに固着されたセラ
ミツクキヤツプとから成るパツケージ本体を具備
する紫外線透過形パツケージの半導体装置におい
て、前記UVガラスは、その表面がパツケージ本
体の上面を構成している前記セラミツクキヤツプ
の上面よりも低い位置となるように、前記セラミ
ツクキヤツプの孔に嵌め込まれてなることを特徴
とする半導体装置。 ２ 前記UVガラス表面は、凹面であることを特
徴とする特許請求の範囲第１項記載の半導体装
置。[Scope of Claims] 1. A ceramic base having a semiconductor pellet fixed to its upper surface, and a hole fitted with UV glass for transmitting ultraviolet rays to be irradiated to the semiconductor pellet, and fixed to the ceramic base. In the semiconductor device of the ultraviolet transmitting type package, the UV glass is located at a position lower than the top surface of the ceramic cap that constitutes the top surface of the package body. , a semiconductor device which is fitted into a hole of the ceramic cap. 2. The semiconductor device according to claim 1, wherein the UV glass surface is a concave surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113708A JPS5816550A (en) | 1981-07-22 | 1981-07-22 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113708A JPS5816550A (en) | 1981-07-22 | 1981-07-22 | semiconductor equipment |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63042000A Division JPS63232355A (en) | 1988-02-26 | 1988-02-26 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5816550A JPS5816550A (en) | 1983-01-31 |
| JPH0322059B2 true JPH0322059B2 (en) | 1991-03-26 |
Family
ID=14619144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56113708A Granted JPS5816550A (en) | 1981-07-22 | 1981-07-22 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5816550A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60219407A (en) * | 1984-04-13 | 1985-11-02 | Honda Motor Co Ltd | Hydraulic tappet system for internal combustion engines |
| JPS6195220A (en) * | 1984-10-17 | 1986-05-14 | Hitachi Ltd | spectrophotometer |
| JPS6327048U (en) * | 1986-08-05 | 1988-02-22 | ||
| US5115299A (en) * | 1989-07-13 | 1992-05-19 | Gte Products Corporation | Hermetically sealed chip carrier with ultra violet transparent cover |
-
1981
- 1981-07-22 JP JP56113708A patent/JPS5816550A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5816550A (en) | 1983-01-31 |
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