JPH0322035A - Trouble evading system for microprocessor - Google Patents

Abstract

PURPOSE:To evade the fixed trouble of a microprogram by substituting the microprogram step, where fixed trouble of the microprogram occurs, with a microprogram step set to a trouble micro register. CONSTITUTION:When fixed trouble occurs in the microprogram, a microprocessor is operated after a pertinent check bit of a check register 1 is made effective and a trouble evading microprogram is set to a trouble micro register 12. When the microprogram in the entry address to which the trouble position belongs is executed, the check bit is referred to select the micro register 12 by a trouble micro selector 5, and contents of the trouble micro register 12 are executed instead of the microprogram where trouble occurs. Thus, trouble of the microprogram is evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for avoiding fixed faults in a microprocessor (LSI), and particularly to a method for avoiding fixed faults in a microprogram built into a microprocessor.

[Prior Art] Conventionally, a microprocessor with a built-in microprogram has no means to avoid a fixed failure even if it occurs in the microprogram.

[Problem to be solved by the invention] For this reason, once a fixed failure occurs, if the system is in operation, the system structure must be changed to one that does not use the microprogram routine where the failure occurred, or the system operation itself must be changed. It has to be stopped. Furthermore, if a fixed failure occurs during evaluation, it becomes difficult to proceed with the evaluation because it becomes impossible to move the microprogram beyond the failure location.

In this way, when a fixed fault occurs in the microprogram of a conventional microprocessor, there is no workaround, so the only way to remove the fixed fault is to rework the microprogram, which takes a long time. As a result, system operation and evaluation are greatly hindered.

[Means for Solving the Problems] A failure avoidance method for a microprocessor according to the present invention is a microprocessor that has a built-in microprogram in its main body, which can be rewritten by the microprogram, and has a system that corresponds to each entry step of the microprogram. A check register having a check bit, a check selector that selects one check bit in the check register from a micro address, a check latch that holds the check bit selected by the check selector for a certain period of time, and a faulty microregister that is rewritable and has the same bit width as one step of the microprogram;
The output of the fault microregister and the output of the microprogram latch are manually selected, and when the contents of the check latch are valid, the output of the fault microregister is selected, and when the contents of the check latch are invalid, the output of the microprogram latch is selected. a fault microselector, when a fixed fault occurs in the microprogram, the corresponding check bit of the check register is enabled, and after setting a fault avoidance microprogram in the fault microregister, the microprocessor is activated. When the microprogram at the entry address to which the fault belongs is executed, the fault micro register is selected by the fault micro selector by referring to the check bit, and the micro program is executed in place of the faulty microprogram. , is characterized in that it is configured such that failures can be avoided by executing the contents of the failure microregister.

[Example code] Next, the present invention will be explained using the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Check register 1 is a microprogram ROM
This register has a number of bits equal to the number of entry steps of 7, and if the data length of MBUS42 used as a data path for reading and writing check register 1 is, for example, 32 bits, then there are Xn registers with a length of 32 bits. Consists of. Here, the entry step refers to the first step of every 32 steps, and refers to the execution start step of the microprogram. The check register controller 2 connects the MD-bus 39 to a destination register specified by the microprogram.
Or point to the source register
4 Check register specified by 0 C H K
It controls reading and writing from the MBUS 42 for R0 to CHKR (n-1). Each bit of the check register is manually input to the check selector 3, and one bit selected by the upper 11 bits of the micro address (MA) 34 is held in the check latch circuit 4 and sent to the faulty micro selector 5 as a FAIL signal 24. is input.

The fault micro selector 5 also contains a signal 36 that latches one step of the micro program corresponding to the micro address (MA) 34, and a fault micro register 1.
2 is input. Failure micro selector 5 is FAIL
When the signal 24 is '0', the MLCH signal 36 is output to the data line 27, and when the FAIL signal 24 is '1', the MLCH signal 36 is output to the data line 27.
The contents of MREG are output to data line 27.

A buffer (BUFFER) 11 holds the microprogram output to the data line 27 for one clock,
It is distributed to various parts of this microprocessor through the MD bus 26.

PREDECODE 10 decodes the contents of data line 27 and generates control signals 25, 37, 38 for controlling the microprocessor.

A microaddress controller (MARCNT) 6 generates a microaddress for the next microprogram to be executed each time a microprogram is executed, and uses an address line 34 to write a microprogram ROM (MROM).
)7 and ROM selector (MSEL)8 input, and M
Select one step in ROM7.

Now, when there are no fixed faults and normal operation is performed, all check registers 1 are "0°", and this causes M
The FAIL signal 24 output from the check latch circuit 4 by the STB 2g is always "O".The failure micro selector 5 eventually sends the output from the micro latch 9 to the precoder 10 and buffer 11, thereby reducing the MR
The microprograms in OM7 are executed sequentially to perform normal operation.

Next, we will show the operation when a fixed failure occurs.

Suppose now that a fixed failure occurs at the acos address of the microprogram. At this time, from the microprogram initialization routine or software initialization routine, the MBU
Bit 0 of CHKR3 of check register 1 is set to "l" via S42. Furthermore, a fault avoidance microprogram to be executed at address OC00, which is the entry address of address OCO8, is set in the fault microregister 12 by the same means.

After starting up the system, the microprogram ocoo
When attempting to execute the address, first, MA-OCOO is selected and the microprogram at address OC00 is selected from the MROM7. At the same time, the check selector 3 selects bit O of CHKR3 as shown in FIG.
operates, and the microprogram and check bit at address OCOO are latched into MLCH9 and CHKLCH4. The check bit latched in CHKLCH4 is “1”
”, the fault micro selector 5 is FMR.
Select the contents of EG12 and pre-decoder 1 the fault avoidance microprogram set in FMREG12.
It outputs 0 to the buffer 11. The predecoder 10 and buffer 11 judge and operate this fault avoidance microprogram as if it were a normal microprogram.

Here, the program sequence can be changed by specifying a branch instruction to a failure handling routine as a failure avoidance microprogram.

In this way, fixed fault avoidance processing can be performed by replacing the microprogram step in which the fixed fault has occurred with the microprogram step in the faulty microregister.

[Effects of the Invention] As explained above, the present invention eliminates the fixed fault in the microprogram by replacing this microprogram step with the microprogram step set in the faulty micro register when a fixed fault occurs in the microprogram. This has the effect that the operation of a system using the present microprocessor and the evaluation of the present microprocessor can be continued without any hindrance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a truth table showing the operation of a check selector. DESCRIPTION OF SYMBOLS 1...Check register, 2...Check register controller, 3...Check selector, 4...Check latch, 5...Failure micro selector, 6...
・Micro address controller, 7...Micro R
OM, 8... Micro ROM selector, 9... Micro ROM latch, 10... Buri decoder, 11...
- Microbuffer, 12...fault microregister. X 0060 03EO 0400 u-7ヱQ-110800 ocoo OEOO CHKR3(0) CHKR4(0) 1000

Claims (1)

[Scope of Claims] 1. A microprocessor with a built-in microprogram, which is rewritten by the microprogram and has a check register corresponding to each entry step of the microprogram, and a check register that has check bits corresponding to each entry step of the microprogram; A check selector that selects one check bit in a check register, a check latch that holds the check bit selected by the check selector for a certain period of time, and a check latch that can be rewritten by the microprogram and one step of the microprogram. Input a fault microregister having the same bit width, the output of the fault microregister, and the output of the microprogram latch, select the output of the fault microregister when the contents of the check latch are valid, and select the output of the fault microregister when the contents are invalid. has a fault micro selector that selects the output of the micro program latch, and enables a corresponding check bit in the check register when a fixed fault occurs in the micro program, and also sends a fault avoidance micro selector to the fault micro register. After setting the program, when operating the microprocessor and executing the microprogram at the entry address to which the faulty location belongs, the faulty microregister is selected by the faulty microselector by referring to the check bit; 1. A failure avoidance method for a microprocessor, characterized in that the failure can be avoided by executing the contents of the failure microregister in place of a microprogram in which a failure has occurred.