JPH03219658A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To largely reduce or eliminate an interconnection region which is required except a layout block and to enhance integration of semiconductor elements, etc., by dividing interconnections for connecting the blocks therebetween into second and third layer interconnections, and arranging all or part of the interconnections by using the blocks. CONSTITUTION:Basic gates necessary for a semiconductor integrated circuit device are prepared as standard cells 1-22, and the cells 1-22 are so grouped to suitable number of stages that second and third layer interconnections 2AL, 3AL to be connected to each other are short and not entangled. Then, the interconnections 2AL, 3AL are formed by using interconnection regions B, C on standard cell rows. If all the interconnections cannot be provided, conventional interconnection regions 23-24 on the regions B, C and the periphery of the standard cell row. Thus, the regions 23-24 provided between the stages have no interconnections 2AL, 3AL or can be largely reduced in number even if the interconnections 2AL, 3AL exist to enhance the integration of the entirety, thereby reducing a board.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device configured as an assembly of multiple types of layout blocks, mainly standard cells, having different logic functions and driving capabilities.

[Conventional technology]

FIG. 6 shows a conventional semiconductor integrated circuit device (Place and Route) configured as an assembly of standard cells.
eReference Manual Versi
on 2.0 SDA Systems, I
ncJune 22.1988 Chapter 15
, page 15).
．． 5.6.16.7.8, etc. all indicate standard cells. The standard cells 15 to 8 each have a logic function and a driving ability,
Therefore, the width dimensions are also different. These standard cells 15
8, the wiring is as short as possible (furthermore, it is divided into multiple groups for simplicity, arranged in an appropriate number of stages, and has an appropriate width between each stage).
The IN eye layout RIAL (both appear as horizontal wiring) and the second layer wiring 2 are set here by setting area 24.
The standard cells 15 to 8 are interconnected using AL (all shown as vertical wiring).

For example, the standard cell 6 is a two-person AND gate, and is specifically constructed as shown in FIG. 7.8. 7th
The figure is an enlarged layout diagram of a standard cell constituting a two-man-powered ND gate circuit, and Figure 8 is a layout diagram of input/output terminals. 35 is a gate polysilicon, and 37 is a first layer wiring (a region shown with hatching) that connects these transistors.

Diffusion layer 34 constituting the transistor. The gate polysilicon 35 is connected to the first layer wiring 37 via a contact 38 (shown in the figure), and is connected to a terminal 36a shown in FIG.
, 36c, 36d and connection points 40 as shown in FIG.
a, 40b (or 40e, 40f), 40c (
or 40g) is constructed. Input terminal 36a of standard cell 6 as described above,
36c and 36d are connection points 40a and 40b (or 40
e, 40f), 40c (or 40g), the pH range 24.
It is connected to the other first-layer wiring IAL arranged on the wiring area 24 and the second-layer wiring 2AL arranged with an insulating film interposed between the first-layer wiring IAL and the first-layer wiring IAL. It is connected to other standard cells 15 to 8 via IN-th and second-layer wirings IAL and 2AL.

By the way, when designing a semiconductor integrated circuit device using such a standard cell, the procedure is usually as shown in FIG. FIG. 9 is an explanatory diagram showing the procedure for determining the layout of a standard cell of a semiconductor integrated circuit. First, a logic diagram is created using the basic gates necessary to configure the logic circuit to be designed, and then the created logic diagram is Based on this, the stray capacitance is estimated according to the number of gates in the next stage that the output terminal of each standard cell should drive (referred to as the fan-out number), and the required driving capacity for each standard cell is determined. As shown in Figure 9 (al), the necessary basic gates, such as AND, OR, NAND.

NOR, NOT, etc. are prepared as standard cells 1 to 22.

Standard cells 1 to 22 have different widths depending on their function and driving force, and the drawing shows three types of standard cells 1 to 22 with different widths.
12.13-21 and 22 are shown.

Next, regarding the standard cells 1 to 22 as shown in FIG. 9(a), the standard cells 1 to 22 are grouped so that the length of the wiring connecting these terminals to each other is as short as possible and is simplified. They are divided and arranged in an appropriate number of stages (three stages in the drawing) as shown in FIG. 9 (b>).

Next, as shown in FIG. 9(C), between the terminals of each standard cell 1 to 22, a wiring area 22° 23, defined around the standard cell row,
24, the first layer wiring IAL as shown in FIG.
Connection is made by the second layer wiring 2AL. Note that the distribution areas 22, 23, and 24 are expanded or contracted as appropriate depending on the number of wires.

[Problem to be solved by the invention]

By the way, in the layout created in this manner, the wirings IAL and 2AL connecting between the standard cells are located in wiring areas 22, 23, and 24 that are separate from the formation areas of semiconductor elements such as transistors that constitute the standard cells 1 to 22. , approximately half of the chip area is allocated to the wiring areas 22, 23 .
24, which has the disadvantage that the degree of integration of transistors and the like is poor.

In addition, the stray capacitance of the wiring connected to the output terminal is estimated according to the number of fan-outs, the driving capacity of the standard cells 1 to 22 is determined, and the standard cells 1 to 22 are divided into groups as shown in Figure 9 (bl). Even if this is done, not all the wiring will be shortened, and in some cases, as shown in FIG. A case may arise when cell 12.1 must be driven.

In such a case, the signal will be delayed and the overall operation will be slow, so standard cells 2 and 11 will be replaced with cells with larger driving force, but in this case, the cell width will naturally change, so other standard cells would have to be moved. However, when the amount of movement increases, there is a problem that the wiring area becomes insufficient and a wider substrate area is sometimes required, making it necessary to redesign the wiring.

The present invention was made in view of the above circumstances, and its purpose is to provide a semiconductor integrated circuit device that increases the degree of integration of transistors, reduces the chip area, and eliminates inconveniences such as signal delays. It is on offer.

[Means to solve the problem]

In the semiconductor integrated circuit device according to the present invention, wiring connecting between layout blocks is divided into second layer wiring and third layer wiring, and all or part of these wirings are arranged using the layout blocks. do.

[Function] According to the present invention, the wiring area required other than the layout block is significantly reduced or becomes unnecessary, and the degree of integration of semiconductor elements and the like is increased.

〔Example〕

The present invention will be specifically described below based on drawings showing embodiments thereof.

FIG. 1 is a layout diagram showing standard cells arranged in groups and wiring in the second and third layers in a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a standard cell shown in FIG. 1. FIG. 3 is an enlarged layout diagram showing the first layer wiring provided in the cell area. FIG. 3 is an explanatory diagram showing connection points between third-layer wiring and standard cells.

In Figure 1, 15 to 8 are all standard cells arranged in the same row by grouping, IAL is the IN-th wiring, 2AL is the second layer wiring (appears as horizontal wiring), and 3AL is the 3rd layer wiring. The eye wiring (shown as vertical wiring) is shown.

The standard cell 6 is an AND gate made by two people, and as is clear from FIG. 2, a diffusion layer 25 constituting a transistor, which is a semiconductor element, and a gate polysilicon 26 are also formed.
Gate polysilicon 26 that constitutes these transistors
, the diffusion layer 25 is connected to the first layer wiring 1^L via a contact 29 (shown in the figure), and the diffusion layer 27a is connected to the output terminal 27b.
, 27c are used as input terminals. The first layer wiring IAL is connected to the second layer wiring 2^L (28a, 28a, 28c, 28
d) and/or the second and third layer wirings 2AL connected to the third layer wiring 3AL disposed on the wiring 2AL with an ml film in between.

Standard cells are interconnected via 3^L.

2nd and 3rd layer wiring 2^L, 341. 1.3
As shown in the figure, the second and third layer wirings 2AL and 3AL are set approximately at the center of the standard cells 15 to 8 in the vertical direction.
Areas excluding connection point area A, that is, wiring areas B and C
(shown with hatching) are disposed above each other with an insulating film interposed therebetween. Note that 28b is a relay point for wiring that crosses the standard cell.

FIG. 4 is an enlarged layout diagram showing another example of the standard cell, in which the formation region of the diffusion N25'25' constituting the transistor is extended in the vertical direction, and along with this, the gate polysilicon 26' The formation region is also configured to extend in the vertical direction of the standard cell, and although the width of the standard cell as a whole remains the same, the length in the vertical direction is increased, and the driving capacity is increased. The rest of the structure is substantially the same as that of the embodiment shown in FIG. 2, and corresponding parts are given the same reference numerals and explanations will be omitted.

A procedure for creating a layout of a semiconductor integrated circuit device as described above will be specifically explained. FIG. 5 is an explanatory diagram showing the layout creation procedure. As in the past, basic gates necessary for a semiconductor integrated circuit device are prepared as standard cells 1 to 22, as shown in FIG. 9(a), and each standard cell 1. 22 are grouped into an appropriate number of stages (three stages in the embodiment) as shown in FIG. 5(a) so that the interconnections 2AL and 3AL in the second and third layers that are connected to each other are short and do not become complicated. At this time, a gap is provided around the standard cell row as a wiring area as in FIG. 9(b), but it is expanded or reduced as appropriate depending on the number of wiring lines.

Next, the second and third layer wirings 2AL and 3AL are formed using the wiring areas B and C on the standard cell column. Of course all arrangements
There may be cases where it is not possible to arrange IIIA2AL and 3AL in areas B and C, but in this case it is impossible to arrange them on the standard cell column! A? Needless to say, this is carried out using the conventional wiring areas 23 to 24 (areas indicated by hatching on Cbl in FIG. 5) around the iJ areas B and C and the standard cell row. As a result, arrangement 1 ml area 2 provided between each stage
3 to 24 have no wires, wires 2AL and 3AL, or wires 4
Even if 12AL and 3AL exist, their number can be significantly reduced, increasing the overall degree of integration and making it possible to reduce the size of the substrate.

We check whether the predetermined performance can be obtained with the completed layout as shown in Figure 5, calculate the stray capacitance from the actual wiring length, and determine the amount of signal delay through simulation.

As a result, for example, because the signal line is long, the stray capacitance becomes larger than the drive capacity of the standard cell, the amount of delay is large, and the desired performance may not be obtained.
1 is replaced with standard cells 2' and 11' as shown in FIG. 5(C), which are separately prepared. The standard cell 2' shown in FIG. 5(C) is, for example, type B as shown in FIG.
Although the width is the same as that of the cell 2 shown in FIG. 2(b), the vertical length is larger than that of the standard cell 2, and the capacity is also larger.

Further, the standard cell 11' has the same width as the standard cell 11 shown in FIG.
is larger than that of . As a result, the standard cells 2' and 11' have the same width as the standard cell 2.11 before replacement, so they can be replaced without moving other standard cells, and the semiconductor integrated circuit device has less delay. can be easily obtained.

〔Effect of the invention〕

As described above, according to the device of the present invention, the upper part of the standard cell can be used as a wiring area, the degree of integration can be increased, and the chip area can be reduced.The present invention has excellent effects.

[Brief explanation of drawings]

Fig. 1 is a partial layout diagram of the device of the present invention, and Fig. 2 is a partial layout diagram of the device of the present invention.
Fig. 3 is an explanatory diagram showing the distribution ASI area in the device of the present invention, and Fig. 4 is an enlarged plan view of the first layer wiring and semiconductor element of the standard cell shown in the figure. 5 is an explanatory diagram showing the design process of the device of the present invention, FIG. 6 is a partial layout diagram of the conventional device, and FIG. 7 is the first layer wiring of the standard cell shown in FIG. 6. and an enlarged plan view of a semiconductor element, FIG. 8 is an explanatory diagram showing the arrangement of input terminals and output terminals in a conventional device, and FIG. 9 is an explanatory diagram showing the design process of the conventional device. L~22...Standard cell 2', 11'...Standard cell 23, 24...'A'? iI area 1^L...
1st layer wiring 2AL... 2nd layer wiring 3AL...
・Third layer wiring A... Connection point area B, C...
Wiring area: In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device that has one or more semiconductor elements and a first layer of wiring that interconnects these elements, and is configured as a collection of multiple types of layout blocks with different logical functions and driving capabilities, A wiring layer in which a second layer of wiring is provided for connection between the layout blocks, and a third wiring layer in which a third layer of wiring is provided, and the first layer wiring and the second layer wiring are provided. A semiconductor integrated circuit device characterized in that each wiring layer is stacked and provided in this order on the region of the layout block in a mutually insulated state.