JPH03218073A - Thin film semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To reduce the time lag of a threshold voltage without increasing the number of processes by constituting the gate electrode of an FET of a P-type semiconductor containing crystal grains having specified diameters. CONSTITUTION:A thin intrinsic amorphous film having a thickness of about 1,000-1,500Angstrom is deposited on a quartz substrate 100 and the thin film is patterned to meet the semiconductor area 101 of a thin-film transistor TFT. Then the grain size of the crystals is enlarged to 1mum by a solid-phase growing method, annealing method, etc., and the crystal grains are coated with an SiO2 film 102 having a thickness of 300-500Angstrom which is a gate insulating film. The film 102 is then coated with a P-type alpha-Si film 103 having a thickness of 3,000-7,000Angstrom and the hydrogen contained in the film 103 is removed and, at the same time, the B particles added when the thin film is formed are activated so as to form a polycrystalline thin film by annealing. A gate electrode 104 is formed by patterning the thin film 103 of large crystal grains and positioning the film 103 on the film 102. Thereafter, areas 105, 106, and 107 which respectively become a source area, drain area, and channel area are formed by implanting ions through the film 102 by using the film 103 as a mask.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a thin film semiconductor device and a method for manufacturing the same.

[Conventional technology] In recent years, insulating amorphous substrates such as glass and quartz have been developed to realize large, high-resolution active matrix liquid crystal display panels, high-speed, high-resolution contact image sensors, 3D ICs, etc. , polysilicon (SiOx・X is 1~
Attempts have been made to form high-performance semiconductor elements on insulating amorphous layers such as 3). In particular, in large-sized liquid crystal display panels, in order to meet the demand for low cost, it is becoming essential to form thin film transistors (TPT) on inexpensive low-melting point glass substrates. Conventionally, the active layer of TPT formed on a low melting point glass substrate was
s Vol. 65(10) p. 3951 (1989), etc., using non-quality silicon (a-Si), Solid State E-electron
ics Vol. 32(5) p. 391 (1989)
, IEEE Elec-tron Device Le
tters Vol. 10(3) p. 123 (198
9), EEE Transactions on E
Lectron Devices Vol. 36(3)
p. 529 (1989), etc., which use polycrystalline silicon (poly-Si). In addition, the gate electrode is made of MO, Cr, A, etc. as seen in the above-mentioned known example.
There are those using metal electrodes such as L, Ti, and PT, and those using poly-Si doped with impurities. [Problem to be solved by the invention] In TPT, a poly-Si thin film has been heated in PCI Os gas, which does not require particularly difficult techniques, in order to obtain a low-resistance gate electrode. Ta. Further po
By introducing hydrogen into the channel region of the poly-Si thin film using H2 plasma, etc., an n-type poly-Si gate electrode with lower resistivity was obtained by reducing the trap levels of the poly-Si thin film. However, it is known that when this gate electrode is used, a shift in threshold voltage occurs in an n-channel TPT, and an increase in off-state current leads to wasted power consumption. In the conventional manufacturing process of thin film semiconductor devices, channel doping, such as introducing B (boron) ions into the channel portion, has been carried out in order to reduce the above-mentioned shift in threshold voltage. However, it is difficult to control the amount of channel doping introduced, and the number of steps required is one. In addition, the po
Although there have been attempts to form the semiconductor region or gate electrode part of TPT (hereinafter these two parts will be referred to as silicon material) using an a-Si thin film, the material structure of the a-Si thin film is insufficient. There was no effective method to prevent cavitation of the thin film during the desorption process of the contained hydrogen. Therefore,
The resistivity of the silicon material formed by the thin film is po
It was not possible to compete with the low resistivity of silicon, which is formed by thin films of ly-Si deposited by low-pressure chemical vapor deposition (LPCVD). Therefore, the present invention aims to convert a p-type a-Si thin film into a p-type poly-Si thin film with lower resistivity using a simpler method, and its purpose is to provide higher performance thin-film semiconductor devices and their use. The purpose is to provide manufacturing methods. [Means for Solving the Problems 1] The thin film semiconductor device of the present invention is characterized in that the gate electrode of the field effect transistor is made of a p-type semiconductor containing crystal grains having a crystal grain size of 1 μm or more.

Further, the method for manufacturing a thin film semiconductor device of the present invention includes a step of forming an amorphous semiconductor thin film containing impurities, a step of annealing the thin film to form a polycrystalline semiconductor thin film, and annealing the thin film to form the thin film. The feature is that it includes at least a step of activating impurities contained therein. The method for manufacturing a thin film semiconductor device of the present invention includes a method for manufacturing a thin film semiconductor device using the above manufacturing method.
The feature is that the gate electrode of a field effect transistor made of a type semiconductor is formed. Furthermore, the method for manufacturing a thin film semiconductor device of the present invention is characterized in that an upper limit is set for the temperature increase rate when increasing the temperature from the pre-annealing temperature to the set annealing temperature in the impurity ion activation annealing step. ．． [
Embodiment] FIGS. 1(a) to 1(d) are examples of manufacturing process diagrams of a thin film semiconductor device in an embodiment of the present invention. In FIG. 1, a case where a TPT is formed as a thin film semiconductor element is illustrated.

First, a plasma CVD method (PCVD) was applied on a quartz substrate.
About 1,000 to 1,500 intrinsic a-Si thin films are laminated by the LPCVD method or the LPCVD method.

After patterning this a-Si thin film into the semiconductor region 101 of the TFT, the grain size is increased by means such as solid phase growth or aeral (FIG. 1(a)). In this case, patterning may be performed after increasing the grain size.

Further, in the annealing, the annealing method used for thinning p-type poly-Si from p-type a-Si thinning during gate electrode formation, which will be described later, may be used. Next, thermal oxidation is performed to form a gate insulating film of about 30% Si02102 on the Si thin film.
Form 00 to 500 people. Here, a sputtering method may be used instead of thermal oxidation. Further, the material of the gate insulating film is not limited to Si02, but may be silicon nitride or other insulating silicon compounds. Then, using the PCVD method, about 30% of p-type a-Sil03 is deposited on the substrate and the gate insulating film.
000 to 7000A (Fig. 1(b)) In this p-type a-Sil03 lamination process, a μ-wave plasma CVD method, a sputtering method, etc. may be used in addition to the PCVD method, and an intrinsic Si ion implantation may be performed into the a-Si (or p-type a-Si, or n-type a-Si) thin film. In this example, the PCV
The case of method D will be explained. In the PCVD method, p-type a-Si
S i H a and H2 gas are used as the thin film forming gas, and B 2 H is used as the doping gas for introducing holes.
s gas was used. The conditions for forming the p-type a-Si thin film were a substrate temperature of 180 to 250°C and a vacuum chamber internal pressure of 0.8 Torr.
An RF power source with a frequency of 13.56 MHz was used. Also, B
The flow rate ratio of 2H6 and SiH4 is [B2Hsl/[3 i
H4] "3 X 1 0-'~3 X 1 0-2
I set it so that However, the film forming conditions are not limited to these. Here, annealing is performed to form a p-type a-
Hydrogen contained in the Si thin film is desorbed, B atoms added at the time of forming the thin film are activated, and the thin film is made into a polycrystalline thin film (poly-Si thin film). Anil is
It consists of a first annealing and a second annealing, and in this example, both annealings were N2 annealing. First, during annealing, preheating of the annealing furnace is kept to a minimum and low-temperature insertion is performed. In mass production, since it is a continuous process, residual heat from the previous patch may remain, but even in this case, it is preferable to cool the furnace once and insert it into the warmer state. The primary purpose of the first annealing is to prevent the p-type a-Si thin film from adsorbing oxygen, etc. when taken out into the atmosphere, thereby reducing the film quality of the thin film. It is desirable that the annealing process after forming the p-type a-Si thin film be a continuous process, that is, a process in which nitrogen gas is introduced without breaking the vacuum chamber and heat treatment is performed as it is; in that case, the first annealing may be omitted. can. The first annealing is preferably performed at a heat treatment temperature of 300°C or higher, and a particularly large effect was obtained at 400-500°C. Incidentally, if the purpose is only to densify the thin film, it is effective even if the heat treatment temperature is less than 300°C. The second annealing increases the grain size of the p-type a-Si thin film,
This is done with the purpose of reducing the resistivity of the thin film so that the thin film can sufficiently fulfill its role as a gate electrode later on. The second annealing was performed at a heat treatment temperature of 550 to 650° C. for several hours to 72 hours, and particularly desirable effects were obtained after 40 hours or more. The second annealing causes hydrogen desorption and crystal growth, resulting in a growth of 1-3 μm (2 μm over 40 hours).
A p-type poly-Si thin film with large grain size (~3 μm) is formed. For both annealing, the temperature increase rate from the pre-anneal temperature to the set annealing temperature was 20 d/min.
e g. (5 d e per minute)
g. (It is especially desirable to make it slower than The reason for this is that when the temperature is raised to a predetermined annealing temperature faster than the temperature rise rate mentioned above, defects are more likely to occur in the p-type a-Si thin film, which is a noticeable phenomenon especially after the temperature exceeds 300°C. This is because, as a result, peeling of the thin film may occur.

After the annealing, the p-type a-Si thin film, which has become a p-type poly-Si thin film by increasing the grain size, is patterned into the shape of the gate electrode 104 (FIG. 1(C)). At this time, the resistivity of the gate electrode is 1 x 1 0-' to 3 x 1
0-3 Ω-cm, formed using the conventional LPCVD method, and does not contain crystal grains with a grain size of 1 μm or more.
The resistivity of the gate electrode formed by patterning the ly-Si thin film is almost comparable to that of 2.5xlO-''Ωcm.The patterning of the p-type a-Si thin film was performed before the first annealing. or, if possible, between the first annealing and the second annealing.Also, the first annealing can be omitted.Furthermore, annealing is not limited to N2 annealing. Laser beam annealing, rapid thermal annealing, etc. are also used.When using laser beam annealing and rapid thermal annealing, there is an advantage that the annealing time can be shortened compared to N2 annealing.Next, ion implantation is performed. In the case of p-channel TPT, B (boron) ions are used, and in the case of n-channel TPT, P (phosphorus) ions are used.
A source region 105 and a drain region 106 are connected to the semiconductor region 101 through the gate insulating film using the gate electrode as a mask.
, and form a channel region 107 (FIG. 1(d))
．． Here, activation annealing is performed. Activation annealing is performed in an N2 gas atmosphere for the purpose of promoting activation of B ions or P ions in the source and drain regions.
However, it has been found that this activation also activates B ions in the gate electrode due to patterning of the p-type a-Si thin film, which has become a p-type poly-Si thin film. The resistance of the crystal grain boundaries of the gate electrode is also reduced, making it possible to reduce the resistivity of the entire gate electrode. The setting annealing temperature condition for activation annealing is 600℃~1100℃
However, a temperature of 900°C or higher is particularly desirable. Even at temperatures around 600°C, the resistivity of the gate electrode decreases somewhat. In activation annealing, the heating rate condition from the temperature before annealing to the set annealing temperature is 20 d e g per minute. below(
Preferably 5 d e g. (below).
The reason for this is that if the temperature is raised faster than the temperature increase rate limit in the first stage, the uncrystallized portion of the amorphous material will not crystallize very much, and even if it does crystallize vertically, many crystal nuclei will be generated. This is because residual hydrogen may rapidly desorb from the layer that was a p-type a-Si thin film, causing the layer to become hollow. This will lead to an increase in the rate. Therefore,
In this embodiment, a method of increasing the temperature from the pre-anneal temperature to the set annealing temperature in activation annealing will be described. FIGS. 2(a) to 2(d) are schematic diagrams of a temperature raising method in the activation annealing process of a thin film semiconductor device in an embodiment of the present invention. FIG. 2(a) is a schematic diagram when the temperature is increased from the pre-annealing temperature [T+] to the set annealing temperature [T2]. The set annealing temperature [T2] is 600°C to 1100°C (preferably 900°C to 110°C).
00℃).

Also, the temperature increase rate from [T+] to [T2] is 20 degrees per minute. (Preferably 5 degrees per minute.) The slower speed is adopted as described above, and [T1] is a lower temperature than [T2]. Note that the heating rate does not always have to be constant, and may vary within the above range. Figure 2(b) shows that when increasing the temperature from the pre-annealing temperature [T+] to the set annealing temperature [T2], [T+ko<
This is a schematic diagram when the heating rate is changed at a temperature [T3] where [T3] < [T2]. The set annealing temperature [T2] is 600°C to 1100°C (preferably 900°C to 1100°C). A certain temperature [T3] is within a range lower than the set annealing temperature [T2], 800
℃ to about 1000℃, and after exceeding this temperature [T3], the speed is 5 d e g. It is preferable to increase the temperature at the following rate. Also, from the temperature before annealing to the lower of the set annealing temperature [T2] and 700°C, the rate is 10 d e g. Although a more flexible heating rate is acceptable, even in this case it is 20 d e g. The following heating rate is preferable. The temperature [T3] can be measured not only at one point during annealing, but also at multiple points, and the temperature increase rate from the temperature [T1] before annealing to the set annealing temperature [T2] can be continuously changed. I don't mind if you let me. [T1] is a lower temperature than [T3]. Note that the temperature increase rate does not always need to be constant, and may vary within the above range. Figure 2 (C) shows that when increasing the temperature from the temperature [T+] before annealing to the set annealing temperature [T2], the temperature [T3 FIG. 3 is a schematic diagram of a case where the temperature increase is temporarily stopped and the temperature increase is started again after a certain period of time. The set annealing temperature [T2] is 600°C to 1100°C (
The temperature is preferably 900°C to 1100°C. A certain temperature [
T3] is approximately 600°C to 900°C within a range lower than the set annealing temperature [T2]. This temperature [T3]
The temperature is kept constant for 10 minutes to 1 hour, for example. Alternatively, the temperature [T3] does not always need to be constant, for example, at 5 d e g. You can slowly raise the temperature at 2 to 3 d e g. Degree temperature [T3]
It does not matter if it fluctuates around . This temperature [T3]
Either keep the temperature constant at , or slowly raise the temperature from temperature [T3], or increase the temperature at 2 with temperature [T3] as the center.
~3 d e g. By varying the amount, activation can be performed without impairing the crystallinity of the silicon material. The temperature increase rate from the temperature [T+] before annealing to the temperature [T3] is 20 d e g. (preferably 5 d e g. per minute or less), and the temperature increase rate from temperature [T3] to set annealing temperature [T2] is:
30 d e g. It doesn't matter if it's faster, with an upper limit of .

Further, there may be a plurality of temperatures [T3], which has a higher activation effect, and [T+] is a temperature lower than [T3]. Note that the temperature increase rate does not always need to be constant, and may vary within the above range.

Figure 2 (d) shows that when the temperature is raised from the pre-annealing temperature [T1] to the set annealing temperature [T2], the humidity is raised to the set annealing temperature [T2] and then the annealing is started continuously or after the temperature is raised to the set annealing temperature [T2]. After that (the figure shows a continuous case), [T4] is completed in a shorter time than the time required for annealing.
This is a schematic diagram of a case where the temperature is raised to a temperature [T4] such that the temperature is [T2], and then annealing is performed by lowering the temperature to a set annealing temperature [T2] in a shorter time than the time required for annealing again. The set annealing temperature [T2] is 600℃
~1100°C (in this case, effective results can be obtained at temperatures between 600°C and 950°C, which is particularly desirable). The temperature increase rate from the temperature ['r+] before annealing to the set annealing temperature is 20 d e g. Below, in particular, 5 d e g. The following is desirable.
Also, when increasing the temperature from the set annealing temperature [T2] to the temperature [T4] and from the temperature [T4] to the set annealing temperature [
The rate at which the temperature is lowered to T2 is 10deg/min. ~
40 d e g per minute. It is desirable that the value be within the range of . For rapid temperature increases, rapid thermal annealing such as lamp annealing and laser beam aeration is most suitable. In this case, 40 degrees per minute. It is also possible to increase the temperature even further. By raising the temperature to the temperature [T4], residual hydrogen in the silicon can be completely removed, and activation annealing at the set annealing temperature [T2] can be made more complete. This is because the set annealing temperature [T2] is 6.
This is a particularly effective method of raising the temperature within the range of 00°C to 950°C. At this time, the temperature [T4] is preferably 900° C. to 1100° C. within the range of the set annealing temperature [T2]. ['r+] is a lower temperature than [T2].

Note that the heating rate does not always have to be constant, and may vary within the above range. Moreover, the temperature raising method shown above is not limited to the explanation of FIGS. 2(a) to 2(d). It is also possible to use a combination of each of Figures 2 (a) to (d). Conventional hydrogenated poly-Si contains a very small amount of electrons as carriers, so if n-type poly-Si is used as the gate electrode, there is no problem in the case of p-channel TPT, but in n-channel TPT, the threshold voltage is - There is a phenomenon where it deviates to about IV.
This is undesirable because it leads to an increase in off-state current, leading to heat generation and increased power consumption. For this reason, conventionally, a channel treatment process was required to cancel the charges near the interface between the gate insulating film and the channel region. However, in channel doping, which is the main channel processing step, it is difficult to control the amount of dope, and excessive doping often causes deterioration of film quality and a decrease in current during TPT operation. If a gate electrode formed by patterning a p-type a-Si thin film, which has become the p-type poly-Si thin film of the present invention, can be used not only for n-channel TPT but also for p-channel TP.
Since the threshold voltage does not shift even at T, the channel processing step can be omitted and a TPT with good characteristics can be obtained. [Effects of the Invention] According to the thin film semiconductor device and the manufacturing method thereof of the present invention, it is possible to reduce the shift in threshold voltage that occurs in conventional TPTs without increasing the number of steps. Further, according to the thin film semiconductor device and the manufacturing method thereof of the present invention, it is possible to form a Si thin film that has a large crystal grain size and is difficult to trap impurities at the grain boundary interface. According to the thin film semiconductor device and the method for manufacturing the same of the present invention, a semiconductor thin film with good characteristics can be manufactured more easily than in conventional processes, so that it is possible to improve the yield and shorten the manufacturing time.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are examples of manufacturing process diagrams of a thin film semiconductor device in an embodiment of the present invention. FIGS. 2(a) to 2(d) are schematic diagrams of a temperature raising method (partially a temperature lowering method) in an embodiment of the present invention. 00...
Quartz substrate 01...Semiconductor region 02...Gate insulating film 03...P-type a-Si thin film 04...P-type poly-Si thin film gate electrode 0
5...Source region 06...Drain region 07...Channel region and above

Claims (4)

[Claims] (1) The gate electrode of a field effect transistor has a crystal grain size of 1
A thin film semiconductor device comprising a p-type semiconductor containing crystal grains of μm or more. (2) A step of forming an amorphous semiconductor thin film containing impurities, a step of annealing the thin film to form a polycrystalline semiconductor thin film, and a step of annealing the thin film to activate the impurities contained in the thin film. A method for manufacturing a thin film semiconductor device, comprising at least the following. (3) Manufacturing a thin film semiconductor device characterized in that a gate electrode of a field effect transistor made of a p-type semiconductor containing crystal grains with a crystal grain size of 1 μm or more is formed by the method for manufacturing a thin film semiconductor device according to claim 2. Method. (4) In the impurity ion activation annealing step, an upper limit value is set for the temperature increase rate when increasing the temperature from the pre-annealing temperature to the set annealing temperature. A method for manufacturing a thin film semiconductor device.