JPH03218005A - Resist pattern forming method - Google Patents

Abstract

PURPOSE:To improve throughput of very fine resist pattern formation by forming, on a substrate, a resist layer reactive with light and electron beam, exposing said layer to light or electron beam in accordance with the pattern size, and developing the resist layer. CONSTITUTION:A resist layer 2 reactive with both light L and electron beam E is formed on a wafer 1. A light exposure pattern region S-1, for which sufficient resolution is obtained by using light, is exposed to the light L, and a light pattern latent image 3 is obtained. A very fine pattern region S-2, for which sufficient resolution is not obtained by using light L, is exposed to the electron beam E, and an electron beam pattern latent image 4 is obtained. A resist pattern 5 is formed by developing the resist layer 2. Thereby the exposure time of a resist pattern containing the very fine pattern can be shortened, and throughput is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a resist pattern forming method used for manufacturing semiconductor devices, optical disks, precision mechanical devices, etc.

<Conventional technology> In the lithography technology in LSI device manufacturing,
The mainstream is photolithography technology using a reduction projection exposure apparatus using g-line (wavelength: 416 ns) or i-line (wavelength: 365 nm) as a light source.

Furthermore, with the reduction of the design rule of de Heiss, photolithography using an excimer laser, X-ray lithography, electron beam lithography, etc. have been proposed.

In particular, electron beam lithography is capable of forming ultra-fine resist patterns, and is highly expected to form the core of future lithography technology.

<Problem to be solved by the invention> However, electron beam lithography has an extremely low throughput because it takes an extremely long time to expose one device compared to photolithography.

Therefore, it has been difficult to apply electron beam lithography to the mass production process of dehyss.

<Means for Solving the Problems> The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to provide a resist pattern forming method for forming an ultra-fine resist pattern with excellent throughput. .

That is, a method in which a resist layer that reacts with light and electron beams is formed on a substrate, and the resist layer is developed by exposing it to light and electron beams according to the dimensions of the pattern to be formed on the resist layer. There is.

Further, a pattern forming area that can be resolved by light exposure is exposed to light to form a light beam pattern latent image, and the remaining pattern forming areas excluding the pattern forming area that can be resolved by light exposure are exposed to electron beam. There is a method of forming a resist pattern by forming an electron beam pattern latent image.

Furthermore, when forming a hole-like pattern by forming a resist layer using a negative resist, the resist layer at the periphery of the hole-like pattern to be formed is exposed to an electron beam, and the remaining area except for the area exposed to the electron beam is There is a method of exposing the exposed area to light.

<Function> According to the resist pattern forming method of the above method, by using both light exposure and electron beam exposure in accordance with the pattern dimensions of the pattern forming area, the electron beam exposure area is narrowed and the electron beam Reduce exposure time.

<Example> A first embodiment of the present invention will be described with reference to FIG.

The resist pattern forming method shown in FIG.
, h, a resist layer 2 that reacts with both the light beam L and the electron beam E is formed.

Next, the light ray (i-line: wavelength: t65 nm or g-line dual wavelength 43 nm)
The light beam exposure pattern region S-1, which can be sufficiently resolved when exposed to light (e.g., 6 nm), is exposed to the light beam to obtain a light beam pattern latent image 3.

Next, the ultra-fine pattern area S- that cannot be resolved by the light beam is
2 is exposed to an electron beam E to obtain an electron beam pattern latent image 4.

Then, the resist layer 2 is developed to form a resist pattern 5.

Below, two methods using the above-mentioned resist pattern forming method will be described.
The details of the step of forming the layered resist pattern will be explained with reference to FIG. Furthermore, the various numerical conditions shown in this explanation are illustrative, and it is clear that the present invention is not limited to only these conditions.

In the process ■ "Formation of the lower resist layer," the electron beam E is applied to prevent the hack scatter that occurs when the electron beam E is irradiated onto the wafer L, and also to prevent damage to the wafer L due to the irradiation of the electron beam E. Absorbing novolac type resist (
For example, TSM88800 [resist manufactured by Tokyo Ohka Kogyo Co., Ltd.] and PFR: 1650 [resist manufactured by Japan Synthetic Rubber Co., Ltd.]
) etc. are spin-coated onto the wafer l to form the lower resist layer 6.

In step (2) "hard bake", the lower resist layer 6 is hardened. The baking conditions at this time are, in the case of a hot plate, a baking temperature of 200°C and a baking time of 3 minutes. A lower resist layer 6 having a film thickness of 2.0 g is thus obtained.

Process ■ "Resist layer formation" involves the use of light ray L (iM: wavelength:
165 nm) and an electron beam E;
For example, the resist layer 2 is formed by spin-coating a polyallylsilsesquioxane bisacide resist onto the lower resist layer 6.

In step (2) "prebake", the resist layer 2 is hardened. The baking conditions at this time are, in the case of a hot plate, a baking temperature of 100° C. and a baking time of 1 minute. A resist layer 2 having a film thickness of about 0.5 gm+ is obtained.

The exposure pattern area S-1 is exposed to light by using a reduction projection exposure device (not shown) using an i-line light source, and the exposure pattern area S-1 is Then, a light beam pattern latent image 3 is obtained.The pattern of the light beam exposure pattern area S-1 is
．． It is about 6 JLm, and the hole pattern is about 0.7 in diameter.
It is about pm.

4) "Exposure 2" is to expose ultra-fine pattern area S-2, which cannot be resolved by the above-mentioned light beam exposure, with electron beam E using a vector scanning type electron beam exposure device (not shown). do.

Then, an electron beam pattern latent image 4 is obtained. The electron beam exposure conditions include an accelerating voltage of 20 kV and an irradiation radiation density of 5 lC/cr.
There is n'.

In "Developing and rinsing", the resist layer 2 is developed with a 10/1.5 (volume ratio) mixed solution of isopropanol/hexanone. Then, a resist pattern 5 is obtained. The developing conditions at this time were paddle stationary development and development time of 45 seconds.

Furthermore, after the development process, rinsing is performed using isoprobanol.

In step (2) "bost bake", the dissolved solution impregnated into the resist 2 by development and rinsing is evaporated, and the resist layer 2 is hardened. The baking conditions at this time were a baking temperature of 100° C. for 15 minutes.

In step (2) "Etching", the lower resist layer 6 is anisotropically etched using a reactive ion etching device (not shown) using oxygen gas using the resist pattern 5 as an etching mask.

Then, a resist pattern 7 is formed.

As explained above, in order to form a resist pattern such as an etching mask or an impurity implantation mask, steps 1 to 2 may be performed in order. Further, either step (1) "Exposure 1" or step (2) "Exposure 2" may be performed first.

By the method described above, 161 bits are printed on a 6-inch wafer.
The total exposure time t required to form a gate resist pattern equivalent to DRAM is approximately 25 minutes? It was.

The total exposure time t is the total exposure time L1■ by the light beam L and the total exposure time L1. : The time required for alignment, the time required for moving the wafer, etc. are not included.

On the other hand, as in the conventional example, 16
The total exposure time t required when a resist pattern of a gate corresponding to 1 bit DRAM was entirely formed by electron beam exposure was approximately 1 hour and 30 minutes.

Therefore, in the case of the first embodiment, approximately I
/3 exposure time.

Next, a second embodiment will be explained with reference to FIG.

The resist pattern forming method shown in FIG. 3 is a method of forming a hole-like pattern.

A negative resist layer 2n (2) that reacts with both the light beam (i-ray) L and the electron beam E is formed on the wafer l.

Next, the resist layer 2n at the peripheral edge S-3 of the hole pattern 8 formed in the resist layer 2n is exposed to an electron beam E to obtain an electron beam pattern latent image 4.

Further, the remaining exposure area S-4 excluding the peripheral edge S-3 is exposed to the light beam L to obtain a light beam pattern latent image 3.

Then, the resist layer 2n is developed to obtain a hole pattern 8.

The resist pattern forming method explained above is based on the above-mentioned two methods.
It can also be used in layered resist pattern forming methods. The details will be omitted here, as the other steps are the same except for step 2 "Exposure 1" and step 2 "Exposure 2" in FIG. 2, and will be omitted here. "Exposure 2" will be explained with reference to FIG.

In step (2) "Exposure I", the peripheral edge S-3 of the hole pattern 8 to be formed in the resist layer 2 is exposed to the electron beam E using a vector scanning electron beam exposure device (not shown). Then, an electron beam pattern latent image 4 is obtained. The electron beam exposure conditions are an acceleration voltage of 20 kV and an irradiation dose of 5 JLc/cm'.

Generally, the hole pattern obtained by electron beam exposure has a diameter of 0.7
J. It is smaller than L■.

In the step (Φ "exposure 2"), the peripheral edge S- of the resist layer 2 is
The remaining exposure area S-4 except for exposure area S-3 is exposed to light.

Then, a light beam pattern latent image 3 is obtained. Generally, the hole pattern obtained by light exposure has a diameter of 0.7p or more. In addition, the above step ■ "Exposure 1" or the above step ■ "Exposure 2"
” may be performed first.

By the method described above, 16 bits were printed on a 6-inch wafer.
The total exposure time t required to form a resist pattern of contact holes corresponding to DRAM was approximately 30 minutes.

On the other hand, as in the conventional example, 161b i is placed on a 6-inch wafer.
tTotal exposure time t required when all resist patterns of contact holes equivalent to DRAM are formed by electron beam exposure
It took about 2 hours and 15 minutes.

Therefore, in the case of the second embodiment, approximately 1
/5 exposure time.

<Effects of the Invention> As described above, according to the present invention, light exposure and electron beam exposure are used together when exposing the same resist layer, and ultrafine patterns are exposed using electron beams. The exposure time for resist patterns including fine patterns can be significantly reduced.

Therefore, with the existing exposure equipment, 161bitD R
It enables patterning of high-speed devices such as AM, 64 Mbit DRAM, and even DRAM with a larger memory capacity.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the first embodiment, Fig. 2 is an explanatory diagram of the two-layer resist pattern forming method, Fig. 3 is an explanatory diagram of the second embodiment, and Fig. 4 is an explanatory diagram of the hole pattern forming method. There is a diagram explaining the exposure. DESCRIPTION OF SYMBOLS 1... Wafer, 2, 2n... Resist layer, 3... One-ray pattern latent image, 4... Electron beam pattern latent image, 5... Resist pattern, 8... Hole pattern, L
...Light ray, E...Electron beam, S-1...Light beam exposure pattern area, S-2...Ultra-fine pattern area, S-3...Periphery, S-4...One periphery The remaining exposure area except for part S-3.

Claims (3)

[Claims] (1) Resist pattern formation characterized by forming a resist layer that reacts with light beams and electron beams on a substrate, exposing the resist layer to light beams and exposing the resist layer to electron beams, and developing the resist layer. Method. (2) The above-mentioned resist pattern forming method, in which a pattern forming area resolvable by light exposure is exposed to light to form a light pattern latent image, and the remainder excluding the pattern forming area resolvable by light exposure. 2. The resist pattern forming method according to claim 1, wherein the pattern forming area is exposed to an electron beam to form an electron beam pattern latent image. (3) In the resist pattern forming method, when forming the resist layer with a negative resist to form a hole pattern, the resist layer at the periphery of the pattern to be formed is exposed to an electron beam, and at the same time, the resist layer is exposed to an electron beam. 3. The method of forming a resist pattern according to claim 1, wherein the remaining exposed area excluding the exposed area is exposed to light.