JPH03214658A - Multiple-structure buffer cell - Google Patents

Abstract

PURPOSE:To improve the utilization ratio of a chip of super LSI by providing a plurality of buffers disposed in series in the direction of the long side of a buffer cell and pads disposed in series along the direction of the short side. CONSTITUTION:A plurality of buffers 103 and 104 are disposed in the direction of the long side of a buffer cell 105, while pads 101 and 102 in the same number with the buffers are disposed in the direction of the short side of the buffer cell 105 along the short side thereof. In one buffer cell, in other words, a plurality of pads are disposed along the short side of the buffer cell so that an interval between them is as narrow as possible and, in addition, a plurality of buffers are disposed vertically to the direction of disposition of the pads. When the buffer cell thus constructed is disposed in a very large scale integration, a space between an internal circuit of the very large scale integration and the buffer cell can be made smaller than usual. According to this constitution, the buffer cell can be disposed in a narrower area in the very large scale integration and the utilization ratio of the chip in the very large scale integration can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to the structure of a peripheral buffer cell used in the layout of a very large scale integrated circuit.

[Prior Art] A conventional peripheral buffer cell used in the layout of a VLSI will be described below with reference to the drawings.

FIG. 4 shows a conventional hearing device in which two peripheral buffer cells are arranged side by side. The two buffer cells 205 and 206 have the same shape and structure. A buffer 203 and a pad 201 are arranged in the buffer cell 205 . Buffer cell 205 and buffer 203 are rectangular, and pad 201 is square. The buffer 203 has its short side within the buffer cell 205.
is placed close to one of the short sides of the

Further, the pad 201 is located within the buffer cell 205 and faces the other short side of the buffer cell 205.
03 and the short side of the buffer cell 205. Similarly, the buffer cell 206 includes a buffer 20
4 and a pad 202 are arranged. Note that pads are typically much smaller than buffers.

Buffer cells 205 and 206 configured in this way
If you arrange them in the same direction with their long sides touching, it will look like Figure 4. At this time, the distance between the centers of the adjacent pads 201 and 202 is
05 or the length of the short side of the face cell 206. Furthermore, when arranging a large number of buffer cells in the layout of a VLSI, the buffer cells are arranged so that the pads and buffers are adjacent to each other, with the buffer cells being brought together, as shown in FIG.

[Problem 8 to be Solved by the Invention] FIG. 5 shows a state in which a large number of buffer cells are arranged in a VLSI in this manner.

In the center of the VLSI 211, a square internal circuit 212 is arranged. A large number of buffer cells 205 are arranged in the VLSI so as to surround this internal circuit 212. In this arrangement, the buffer cells 205 are arranged in one column for each side according to the direction of each side of the internal circuit 212.

In this column, the buffer cells 205 are arranged so that the long sides of the buffer cells 205 are joined together, as shown in FIG.

On the other hand, if a plurality of columns of buffer cells 205 are arranged instead of one column as described above, there is a risk of show I between the wires bonded to the pads of the buffer cells. Therefore, if you want to arrange more buffer cells 205 in a VLSI, as shown in FIG. I will do it.

Furthermore, if a predetermined number of buffer cells are arranged in a ring in one row as shown in Figure 5, and there is an internal circuit inside the buffer cells, if the internal circuit is small, there will be a large gap between the buffer cells and the internal circuit. can.

In any case, conventionally there was a problem in that the internal circuit and the buffer cell were separated, creating a large gap, resulting in poor utilization of the VLSI chip. Therefore, this invention was made to solve the two problems.
The purpose is to improve the utilization rate of I's chips.

[Means for Solving the Problems] The present invention provides a rectangular buffer cell having a plurality of buffers and the same number of pads as the plurality of buffers, the plurality of buffers being arranged in series in the direction of the long side of the buffer cell. and pads arranged in series along the short sides of the buffer cell in the direction of the short sides.

Note that the object of the present invention can be more effectively achieved by arranging the plurality of pads arranged along the short sides of the buffer cell so that the spacing between the pads is as narrow as possible.

In the multi-structure buffer cell of the present invention, a plurality of buffers are arranged in the direction of the long side of the buffer cell, and the same number of pads as the buffer cells are arranged in the direction of the short side of the buffer cell. That is, a plurality of pads are arranged in one buffer cell along the short side of the buffer cell so that the spacing between them is as narrow as possible, and moreover, a plurality of buffers are arranged perpendicular to the direction in which the pads are arranged. Therefore, in contrast to the conventional method in which one pad and one buffer are arranged in each width of one side of the buffer cell, in this invention, a plurality of pads and buffers are arranged in one width of one side of the buffer cell. .

As mentioned above, when the multi-structure buffer cell of the present invention is arranged in a VLSI so as to surround the internal circuit, a plurality of pad huffers can be arranged in the width of one side of the buffer cell, so that the internal circuit can be separated from the conventional one. If the same number of buffer cells are placed at the same distance from each other, the number of buffers and pads will be several times larger than in the past. Therefore, the buffer cells can be arranged closer to each other than in the past, and the same number of buffers and pads can be arranged as in the past. As a result, the gap between the internal circuit and the buffer cell becomes smaller than before.

At this time, if the area of the narrowed gap is larger than the area increased by newly arranging buffers in the direction perpendicular to the direction of pad arrangement, then the buffer cells can be placed in a narrower area than before in the ultra-LSI. It would have been placed in

In this way, it is possible to improve the chip utilization rate of the VLSI.

[Embodiment] A multi-structure buffer cell according to the present invention having two pads and two pads will be described below with reference to the drawings.

FIG. 1 is a plan view showing an embodiment of a buffer cell according to the present invention. Buffer cell 105 is rectangular and contains rectangular buffers 103 and 104 and square pads]. o1 and 1o2 are arranged. The rectangular buffer 1.04 has its short side as the buffer cell 105.
The buffer cell 105 is arranged in the buffer cell 105 so as to be close to one of the short sides of the buffer cell 105 . Furthermore, another buffer 103
along the long side of the buffer cell 105.
It is located close to 4. On the other hand, between the other short side of buffer cell 105 and buffer cell 103, pads 101 and 102 are arranged along the short side of buffer cell 105 at appropriate intervals.

A case where the same buffer cells 105 configured as described above are arranged side by side in a VLSI will be described below.

FIG. 2 is a plan view showing a state in which the buffer cell shown in FIG. 1 is arranged in a VLSI. A square internal circuit ]-12 is arranged in the center of the VLSI 111, and 32 buffer cells 105 are arranged so as to surround the internal circuit 112. These buffer cells are internal circuit 1
12, eight buffer cells are arranged for each side, with the long sides of the buffer cells touching each other.

On the other hand, according to the conventional technology, a buffer cell having one buffer and one pad each having the same shape and size as this embodiment is fabricated into a VLSI so as to have the same function as the VLSI shown in FIG. Once placed, it will look like Figure 3. Since there are only ]- pads and buffers in the buffer cell 305, 16 buffer cells are placed on each side of the internal circuit 312, for a total of 64 buffer cells, so as to surround the internal circuit 3]-2. must be placed. Second
As is clear from a comparison between the figure and FIG.
I 3 1. Compared to 1, the gap between the internal circuit and the buffer cell is significantly reduced. And super LSIII
The area of I is smaller than that of the VLSI 311. Therefore, in this embodiment, the chip utilization rate is improved compared to the prior art.

In the embodiment according to the present invention, a buffer cell having two rectangular buffers and two square pads has been described. A buffer cell can be formed as appropriate.

At this time, the object of the present invention can be more effectively achieved by reducing the spacing between the pads arranged in the buffer cell as much as possible.

[Effects of the Invention] When the multi-structure buffer cell of the present invention is placed in a VLSI, the gap between the internal circuit of the VLSI and the buffer cell can be made smaller than in the past. As a result, the buffer cells can be arranged in a narrower area in the VLSI, and the chip utilization rate of the VLSI can be improved. Also, if the chip utilization rate improves,
Since a VLSI can be manufactured using a smaller chip, the cost of the VLSI can be reduced.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a buffer cell of an embodiment according to the present invention. FIG. 2 shows a buffer cell according to an embodiment of the present invention with ultra-L
FIG. 3 is a plan view showing a state where it is placed in SI. FIG. 3 is a plan view showing a state in which a VLSI having the same function as the VLSI shown in FIG. 2 is formed using a conventional buffer cell. FIG. 4 is a plan view showing a conventional buffer cell. FIG. 5 is a plan view showing a state in which a large number of conventional buffer cells are arranged around a VLSI. In the figure, ]01, ]02, 201 and 202 are pads, 103, 104, 203 and 204 are buffers, ]05, 205, 206 and 305 are buffer cells, 111, 2]1 and 310 ]] are very LSIs, 1 12, 212 and 312 indicate internal circuits.

Claims (1)

[Scope of Claims] A rectangular buffer cell comprising a plurality of buffers and the same number of pads as the plurality of buffers, the plurality of buffers arranged in series in the direction of a long side of the buffer cell, the buffer along a short side of the cell, the pads being arranged in series in the direction of the short side.