JPH0321099B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to suppress fluctuations in substrate potential when power is turned on in semiconductor devices, and to prevent latch-up without increasing the circuit scale, and which has one conductivity type. a semiconductor substrate; a first region formed on the surface of the semiconductor substrate, having an opposite conductivity type and electrically grounded;
a second region formed on a region different from the region and having an opposite conductivity type; and a second region formed within the second region,
a third region having one conductivity type and to which a power supply voltage is applied; and the first and second regions on the semiconductor substrate.
a fourth region formed on a region different from the region, having an opposite conductivity type and electrically connected to the first region; pn between and the first area
The structure is such that the junction capacitance between the semiconductor substrate and the fourth region is set to be smaller than the magnitude of the forward voltage at the junction.

[Industrial application field]

The present invention relates to semiconductor devices, and in particular to complementary metal oxide semiconductors (hereinafter referred to as "complementary metal oxide semiconductors") using substrate bias.
(referred to as CMOS) device. The device according to the present invention can be used, for example, as an SRAM (static random access memory) as a storage element in information equipment such as computers, electronic equipment, and the like.

[Conventional technology]

An n-type well is formed on a p-type substrate.
An example of a CMOS device is schematically shown in FIG.
Due to its structure, CMOS is equivalently represented by a thyristor consisting of two transistors, as shown by the broken line. That is, one side is the substrate 1 (p region), the well 3 (n region), and the diffusion layer 2 (n region).
The other is a PNP transistor T _r2 consisting of a substrate 1 (p region), _a well 3 (n region), and a diffusion layer 4 (p region). Therefore, if for some reason the potential level of the substrate 1 rises above a predetermined level for a predetermined period of time, the transistor
T _r1 turns on and its collector potential drops, which causes the base potential of transistor T _r2 to drop and transistor T _r2 turns on,
A through current flows from the power supply V _cc to the ground via the diffusion layer 4, the transistors T _r2 and T _r1 , and the diffusion layer 2 (latch-up). Once latch-up occurs, the through current cannot be stopped even if the thyristor trigger disappears; to stop this, the power supply voltage V _cc must be reduced to zero.

Conventionally, various measures have been taken to prevent such abnormal phenomena (latch-up). As one means, from the viewpoint of preventing transistors T _r1 and T _r2 from turning on,
Although there is a method of increasing the distances d ₁ and d ₂ corresponding to the base widths of T _r1 and T _r2 , this is not preferable because it goes against the trend of miniaturization of the circuit scale. Therefore,
A commonly used method is to use a substrate bias. This is designed to supply a negative voltage (approximately -3V) to the substrate 1 by a substrate bias generation circuit (not shown) appropriately arranged in other peripheral circuits.

Figures 5a and 5b show the potential V _BB of the substrate 1 and the power supply voltage V _CC from when the power supply V _cc is applied to the CMOS and substrate bias generation circuit until it settles into a steady state.
The relationship between is shown. Since the substrate bias generation circuit operates at the time t ₀ when the predetermined voltage V ₀ is reached, the potential V _BB of the substrate 1 is equal to the junction capacitance C 1 between the well 3 and the substrate 1 until it reaches this time t ₀ . , increases in accordance with the inverse ratio of the junction capacitance C2 between the substrate 1 and the diffusion layer 2. That is, as is clear from the equivalent circuit shown in FIG. 7, the potential V _BB is expressed by the following equation.

V _BB = C1/(C1+C2)・V _CC …… (1) [Problems to be solved by the invention] The conventional substrate bias described above is used.
In a CMOS device, due to the CMOS structure, the junction capacitance C1 is much larger than the junction capacitance C2, so as is clear from the relationship in equation (1), the power supply V _CC
The potential V _BB of the substrate when the voltage is turned on becomes a sufficiently large value that it can trigger the thyristor, and this causes a problem in that latch-up is likely to occur.

Furthermore, due to the relatively large forward equivalent resistance in the pn junction between the substrate 1 and the diffusion layer 2, discharge does not occur quickly, so that even when a minute noise signal is applied to the substrate, Substrate potential
V _BB will maintain a relatively large value, and it is highly anticipated that there will be a shift to latch-up.

The present invention was created in view of the problems with the conventional type described above, and is a semiconductor device capable of suppressing fluctuations in the potential of the substrate when power is turned on, and preventing the occurrence of latch-up without increasing the circuit scale. The purpose is to provide equipment.

[Means for solving problems]

As shown in the principle block diagram of FIG. 1, the semiconductor device of the present invention includes a semiconductor substrate 1 having one conductivity type, and a semiconductor device formed on the surface of the semiconductor substrate 1 having an opposite conductivity type and electrically First area 2 to be grounded
a second region 3 formed on a region different from the first region 2 on the semiconductor substrate 1 and having an opposite conductivity type; and a second region 3 formed within the second region 3 and having one conductivity type. and a third region 4 to which a power supply voltage V _cc is applied, and the first and second regions on the semiconductor substrate 1.
A fourth region 6 is formed on a region different from the regions 2 and 3, has an opposite conductivity type, and is electrically connected to the first region 2, and when the power is turned on, the semiconductor substrate 1 The potential V _BB between the semiconductor substrate 1 and the first
A junction capacitance C3 between the semiconductor substrate 1 and the fourth region 6 is set to be smaller than the magnitude of the forward voltage at the pn junction between the semiconductor substrate 1 and the fourth region 2.

[Effect]

According to the configuration described above, when the power is turned on, the substrate potential
The junction capacitance C3 between the semiconductor substrate 1 and the fourth region 6 is set so that V _BB is smaller than the magnitude of the forward voltage at the pn junction between the semiconductor substrate 1 and the first region 2. This occurs due to the coupling of junction capacitance between each region when the power is turned on. Fluctuations in the potential of the substrate can be suppressed, thereby making it possible to prevent the transition to latch-up.

〔Example〕

2 and 3 show a semiconductor device as an embodiment of the present invention, FIG. 2 is a schematic sectional view taken from the - line in FIG. 3, and FIG. FIG.

In this embodiment, a p-type substrate/n-well type CMOS device is used and is formed as an inverter. That is, a p-channel MOS field effect transistor (PMOSFET) as a load transistor is formed in the n-type well 3,
N-channel as an amplification transistor
A MOSFET (nMOSFET) is formed within a p-type substrate 1.

The CMOS device is formed using a known method, and as an example, the entire surface of the substrate 1 is oxidized → P ion implantation and drive-in diffusion to form the n-type well 3 → field oxidation →
Formation of FET region → ion implantation into pMOS field → ion implantation into nMOS field → field and gate oxidation → pMOS and
Ion implantation for nMOS punch-through prevention and V _th (threshold voltage) control → Polycrystalline Si deposition (formation of insulating layer 10) → Etching of polycrystalline Si for gate → To form diffusion layer (n ⁺ ) 2 P ion implantation → B ion implantation to form the diffusion layer (p ⁺ ) 4 → diffusion → contact hole formation → Al
Deposition (electrodes 11 _S , 11 _G , 11 _D , 12 _S ,
It is formed through the steps of forming _12G and _12D → etching Al.

On the outside of the substrate 1, the electrode _11S is
It is electrically connected to a GND (ground) line 13, and the electrode _12S is connected to a power supply V _CC . Moreover, the electrodes 11 _G and 12 _G are interconnected, and the input terminal
The electrodes 11 _D and 12 _D are interconnected and connected to the output terminal OUT.

As shown in FIG. 3, the GND line 13 is
It is derived from the GND pad 15 on the chip 14 and extends to the peripheral circuit 16 on the chip.
The CMOS device in this example is the peripheral circuit 1.
6, and the broken line portion shown in FIG. 2 indicates the boundary between the peripheral circuit 16 side and the GND line 13 side.

Also on the GND line 13 side, reference numeral 6 is a diffusion layer (n ⁺ ), which is formed at the same time as the diffusion layer (n ⁺ ) 2 in the CMOS device manufacturing process described above. The junction capacitance (assumed to be C3) between the substrate 1 and the diffusion layer (n ⁺ ) 6 is the substrate 1
and the junction capacitance between the diffusion layer (n ⁺ )2 (assumed to be C2)
It needs to be larger than . This diffusion layer (n ⁺ ) 6 is connected to a GND line 13 made of Al.

Although not shown, a substrate bias generation circuit for supplying a negative bias voltage (and -3V) to the p-type substrate 1 is internally connected, and this circuit is a p-type substrate/n-well type CMOS transistor. It is a well-known circuit that is commonly used with the device.

As mentioned above, due to the structure of CMOS, the area of the junction region between the n-type well 3 and the p-type substrate 1 (assuming the junction capacitance is C1) is the area between the diffusion layer (n ⁺ ) 2 and the p-type substrate 1.
This is extremely large compared to the area of the junction region between them (junction capacitance C2). However, in the device of this embodiment, the aforementioned junction capacitance C3 having an extremely large value is connected in parallel with the junction capacitance C2.
The substrate potential V _BB when the power supply V _CC is turned on is expressed by the following equation with reference to the relationship of equation (1) described above.

V _BB =C1/(C1+C2+C3)・V _CC (2) FIG. 4 shows an equivalent circuit when the power of the device shown in FIG. 2 is turned on. Furthermore, FIG. 5b shows the substrate potential when the power supply V _CC is applied to the device of this embodiment.
The change in V _BB is shown by the broken line, and as is clear from the comparison with the change in the substrate potential V _BB in the conventional type shown by the solid line, the variation in the substrate potential V _BB at power-on is reduced by ΔV. has been done.

Therefore, the substrate _potential V _BB (=
C1/(C1+C2+C3). Latch-up can be prevented by making the magnitude of V ₀ ) smaller than at least the magnitude of the forward voltage at the pn junction between the substrate 1 and the diffusion layers (n ⁺ ) 2 and 6. Furthermore, in the device of this example,
The ground capacitance of the substrate 1 can be sufficiently increased without increasing the circuit scale of the CMOS device.

Although the above-mentioned embodiment describes a device with a CMOS structure, the present invention is not limited to CMOS, and can be similarly applied as long as a pnpn junction is formed in a semiconductor substrate and there is a similar potential relationship. This will be clear to those skilled in the art.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to suppress the variation in the potential of the substrate when the power is turned on, and to prevent the occurrence of latch-up without increasing the circuit scale.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a semiconductor device according to the present invention, FIG. 2 is a schematic sectional view showing an embodiment of the present invention, and FIG. 3 is a schematic plan view showing the device shown in FIG. 2. , FIG. 4 is an equivalent circuit diagram of the device shown in FIG. 2 when the power is turned on, FIGS. 5 a and b are diagrams showing the relationship between the power supply voltage V _CC and the substrate potential V _BB , and FIG.
A schematic diagram showing an example of a CMOS device.
FIG. 3 is an equivalent circuit diagram when the device shown in the figure is powered on; FIG. 1...Substrate, 2...First region (diffusion layer), 3
... second region (well), 4 ... third region (diffusion layer), 6 ... fourth region (diffusion layer), V _CC ...
...Power supply (voltage), V _BB ...Substrate potential, C1, C2,
C3... Junction capacitance.

Claims (1)

[Claims] 1. A semiconductor substrate 1 having one conductivity type; a first region 2 formed on the surface of the semiconductor substrate 1, having an opposite conductivity type and electrically grounded; and the semiconductor substrate a second region 3 formed on a region different from the first region 2 on the first region 1 and having an opposite conductivity type; and a second region 3 formed in the second region 3 having one conductivity type and having a power supply voltage V a third region 4 to which _cc is applied, which is formed on a region different from the first and second regions 2 and 3 on the semiconductor substrate 1, has an opposite conductivity type, and has a conductivity type different from the first region 2; and a fourth region 6 that is electrically connected to the semiconductor substrate 1, and when the power is turned on, the potential _VBB of the semiconductor substrate 1 is equal to the forward voltage at the p-n junction between the semiconductor substrate 1 and the first region 2. A semiconductor device characterized in that a junction capacitance C3 between the semiconductor substrate 1 and the fourth region 6 is set to be smaller than the size of the semiconductor substrate 1.