JPH03209522A - Instruction code decoder - Google Patents

Abstract

PURPOSE:To improve the response in a high speed by optionally selecting an optimum map (instruction set) out of plural instruction maps (instruction sets) and limiting the number of instructions available to each instruction map (instruction set). CONSTITUTION:An instruction code register 1 selects one of plural instruction maps 5 (1 - n) based on the value of the register 1. The value of the register 1 is inputted to an instruction decoding part 4 together with the data 3 which is received from software as a part of an instruction code. This data 3 has the shortest word length and therefore the queuing frequency is reduced through the width of data supplied from the software is limited. Consequently, the throughput of a system is improved and the response in the high speed is also attained.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention has a plurality of instruction maps (instruction sets) and can select any instruction map (instruction set), thereby reducing the actual instruction code word length. Shorten it and wait for the instruction code (
The present invention relates to an instruction code decoding device that can improve throughput (operating rate) by reducing (hereinafter referred to as queue waiting).

[Prior Art] Conventionally, in a processor that has many types of instructions,
When assigning instruction codes to all instructions, it is not possible to assign instruction codes to all instructions with a single instruction word length unique to the processor. Therefore, in addition to the first map, a second map is formed to assign short and long instructions. Commands were assigned to long commands. That is,
Instructions that were used relatively frequently were given short word lengths, and orders that were used less frequently were given long word lengths.

[Problems to be Solved by the Invention] However, although the frequency of instructions assigned to long word length instructions is low, when the word length becomes long, the probability of waiting in a queue increases, and not only that instruction but also other instructions This affected execution and reduced system throughput.

The present invention solves the above-mentioned conventional problems, and aims to provide an instruction decoding device that can eliminate queue waiting and improve system throughput by forming an instruction set using only short word length instructions. .

[Means for Solving the Problems] In order to achieve the above object, the present invention has the following configuration. That is, the instruction code decoding device of the present invention includes an instruction code register that can arbitrarily select an instruction map from a plurality of instruction maps, and inputs data of the selected instruction map to an instruction decoding section together with short word length data input from software. It is characterized by having a means to do so.

In the configuration of the present invention, it is preferable that the instruction code is formed by data in the instruction code register and software, and that an instruction map is arbitrarily selected from a plurality of instruction maps using the instruction code.

Further, in the configuration of the present invention, in the multi-register file system, each register file has a data register that forms a part of the instruction code, and the instruction code is used to arbitrarily select an instruction map from a plurality of instruction maps. It is preferable to switch the instruction map depending on each register file by being able to select the instruction map.

[Operation] According to the configuration of the present invention described above, an optimal instruction map (instruction set) is arbitrarily selected from a plurality of instruction maps (instruction sets).
Since the number of instructions that can be used in each instruction map (instruction set) can be limited, each instruction can be formed with a short word length, reducing the frequency of queue waiting. You can realize your sexuality.

Further, according to a preferred aspect of the present invention, the instruction code is formed by data in the instruction register and software,
Since the instruction code allows an arbitrary instruction map to be selected from a plurality of instruction maps, instructions can be configured with a short word length, and the number of memory access wait states can be reduced.

Further, according to a preferred aspect of the invention, in a multi-register file system, each register file has a data register forming part of an instruction code;
By using the instruction code, it is possible to arbitrarily select an instruction map from a plurality of instruction maps, and since the instruction map is switched according to each register file, there is no need to rewrite the instruction code register when executing multitasking. .

[Example 1] An example of the present invention will be described in more detail below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an instruction code decoding device according to an embodiment of the present invention. Instruction code register 1 is a register for selecting instruction map 5, and one of instruction maps 1 to n can be selected depending on the value of this register. The value of the instruction code register 1 is input to the instruction decoder 4 together with data 3 input from software as part of the instruction code. The data 3 inputted from the software is short word length data, and although the data width inputted from the software is limited, since it is short word length, the frequency of waiting in the queue is reduced.

Since the bit width of the input data 3 from the software is short word length, in order to assign codes to many types of instructions, the data in the instruction code register 1 is used as part of the instruction code, and the data is input to the instruction decoder 4. When doing so, use long word length commands. However, since there is a limit to allocating short length instructions to one instruction map, each instruction map is provided with chained instructions so as to be compatible with various applications.

FIG. 2 is a diagram showing a group of instructions constituting each instruction map (instruction set). Instruction map 1 (instruction set 1) is chained for the operating system. The data transfer instructions are a full set including stack frame formation instructions that can support up to high-level languages. A full set of logical operations, arithmetic operations, and shift low write instructions is provided, but a full set of bit manipulation instructions in data and branch instructions, mainly conditional branches, are not considered necessary for operating system operation. , a subset. Instead, privileged instructions such as system control instructions can be used. Instruction map 2 (instruction set 2) and instruction map 3 (instruction set 3) are chained instruction sets for user applications, and while they only have simple transfer instructions, they have powerful bit operations. In arithmetic operations, the operations that can be handled are limited or omitted, there are no privileged instructions, and the constituent instructions of each instruction map (instruction set) are kept short. If the desired instruction is not available, the instruction map can be changed by rewriting the instruction code register 1, and the necessary instruction can be executed. There is a limit to the number of bits that can be read from memory at one time, and the longer the opcode or operand is, the more memory data will be used, and there may be cases where only memory reading can keep up.

Therefore, by configuring instructions with short word lengths, the number of memory access wait states can be reduced.

Figure 3 shows that in the multi-register fatel system,
This is an example in which each register file can select an instruction map. Each register file 6 is provided with an instruction code register 1, and an instruction map 5 is selected by the instruction code register 1.

Since the instruction code register 1 corresponds to the register file 6, the instruction map 5 is selected by the application software or operating system that uses the register file 6. The value of the instruction code register 1 is decoded together with data from the software during instruction decoding, and the instruction code register 1 is selected. By applying the present invention to a multi-register configuration, there is no need to rewrite the instruction code register 1 during multi-task execution.

[Effects of the Invention] As explained above, according to the present invention, a plurality of instruction maps (
Since the optimal instruction map (instruction set) can be arbitrarily selected from the instruction set (instruction set) and the number of instructions that can be used in each instruction map (instruction set) can be limited, each instruction can be formed with a short word length, reducing the frequency of queue waiting. can. Therefore, it is possible to achieve the effects of improving system throughput and realizing high-speed response.

Further, according to a preferred aspect of the present invention, the instruction code is formed by data in the instruction register and software,
Since an instruction map is arbitrarily selected from a plurality of instruction maps using the instruction code, the instruction can be configured with a short word length, and the memory access waiting state can be reduced.

Further, according to a preferred aspect of the invention, in a multi-register file system, each register file has a data register forming part of an instruction code;
By using the instruction code, it is possible to arbitrarily select an instruction map from a plurality of instruction maps, and since the instruction map is switched according to each register file, there is no need to rewrite the instruction code register when executing multitasking. It has this effect.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an instruction code decoding device according to an embodiment of the present invention, FIG. 2 is a diagram showing a group of instructions constituting each instruction map (instruction set), and FIG. FIG. 3 is a diagram showing an example in which each register file can select an instruction map in a register file system. 1... Instruction code register, 2... Data constituted by the instruction code register in the instruction code, 3...
Data configured by software in instruction code,
4...Instruction decoding unit, 5...Instruction map, 6...Register file. 2?

Claims (3)

[Claims] (1) An instruction code register capable of arbitrarily selecting an instruction map from a plurality of instruction maps, and means for inputting the data of the selected instruction map to an instruction decoding section together with short word length data input from software. An instruction code decoding device featuring: (2) The instruction code decoding device according to claim 1, wherein the instruction code is formed by data in an instruction code register and software, and further comprising means for arbitrarily selecting an instruction map from a plurality of instruction maps based on the instruction code. (3) Using a multi-register file system, each register file has a data register that forms part of the instruction code, and by arbitrarily selecting an instruction map from multiple instruction maps according to the instruction code, each register 2. The instruction code decoding device according to claim 1, further comprising means for switching instruction maps depending on the file.