JPH03206651A - semiconductor packaging equipment - Google Patents
semiconductor packaging equipmentInfo
- Publication number
- JPH03206651A JPH03206651A JP169690A JP169690A JPH03206651A JP H03206651 A JPH03206651 A JP H03206651A JP 169690 A JP169690 A JP 169690A JP 169690 A JP169690 A JP 169690A JP H03206651 A JPH03206651 A JP H03206651A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead frame
- semiconductor package
- sealing material
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000004806 packaging method and process Methods 0.000 title description 3
- 239000003566 sealing material Substances 0.000 claims abstract description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 abstract description 3
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 17
- 238000005476 soldering Methods 0.000 description 17
- 238000007667 floating Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 241000272168 Laridae Species 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、工Ｃチップの封止を行なうための半導体パッ
ケージ装置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor package device for sealing a manufactured C chip.
［従来の技術コ
半導体パッケージ装置のうち、表面実装型と呼ばれる、
ＱＦＰ（Ｑｕａｄｒａｐｌｅ ＦｌａｔＰａｃｋａｇ
ｅ）とｓｏｐ（ｓｍａ１ｘ Ｏｕｔｌｉｎｅｄ Ｐ
ａｃｋａｇｅ）の半導体パッケージ装置はそれぞれ第２
図及び第５図に示すような構造を有している。第２図（
α）はＱＦＰの外観を示す図であり、第２図（ｂ）は第
２゛図（α）のＡＡ’部の断面を示した図であってＱＩ
Ｉ′Ｐの内部構造を示している。同様に、第３図（α）
はＳＯＰの外観を示す図であり、第３図Ｃｈ）は第３図
（α）のＡＡ’部の断面を示した図であってＳＯＰの内
部構造を示している。[Among the conventional technology semiconductor package devices, the so-called surface mount type
QFP (Quadraple Flat Pack
e) and sop(sma1x Outlined P
ackage) semiconductor package devices are the second
It has a structure as shown in FIG. Figure 2 (
α) is a diagram showing the external appearance of the QFP, and FIG.
The internal structure of I'P is shown. Similarly, Fig. 3 (α)
3 is a diagram showing the external appearance of the SOP, and FIG. 3 Ch) is a cross-sectional diagram of the section AA' in FIG. 3 (α), showing the internal structure of the SOP.
ＱＦＰは、そのり・−ド７レームアウターリード部６が
四方向に配置されており、ＳＯＰは、そのリードフレー
ムアウターリード部６が相対する二方向に配置されてい
る。In the QFP, the lead frame outer lead portions 6 are arranged in four directions, and in the SOP, the lead frame outer lead portions 6 are arranged in two opposing directions.
従来のＱＦＰ及びｓｏｐの半導体パッケージ装置は、Ｉ
Ｃチップ１とリードフレームダイパッド部４とを固着し
、工Ｃチップ１上の外部接続用パッド２とリードフレー
ムインナーリード部５とを極細金線３等で接続し、樹脂
封止材等の封止材７で封止した後に、リードフレームア
ウターリード部６に屈曲を付けていたためにその屈曲部
８は封止材７の外部に存在していた。第７図（α）〜（
ｆ）はこれを説明する図である。第７図（α）に示すリ
ードフレームダイパッド部４に、工Ｃチップ１ｆ！：：
固着し（第７図（ｂ））、極細金線３等で接続し（第７
図（Ｃ））、封止材７で封止した（第７図（ｄ））のち
、リード７レームアウターリード部６に屈曲部８馨付け
（第７図（ｅ））、リードフレームアウターリード部６
を適当な長さに切断して（第７図（ｆ））完戊となる。Conventional QFP and SOP semiconductor packaging devices are
The C-chip 1 and the lead frame die pad part 4 are fixed together, the external connection pads 2 on the C-chip 1 and the lead frame inner lead part 5 are connected with ultra-fine gold wires 3, etc., and sealed with a resin sealant or the like. Since the lead frame outer lead portion 6 was bent after being sealed with the sealing material 7, the bent portion 8 was present outside the sealing material 7. Figure 7 (α) - (
f) is a diagram explaining this. A C chip 1f! is attached to the lead frame die pad portion 4 shown in FIG. 7(α)! ::
(Fig. 7 (b)) and connect with ultra-fine gold wire 3 (Fig. 7 (b)).
After sealing with the sealing material 7 (Fig. 7 (d)), the bent part 8 is attached to the lead 7 frame outer lead part 6 (Fig. 7 (e)), and the lead frame outer lead is sealed. Part 6
Cut it to an appropriate length (Fig. 7(f)) to complete the process.
前述のり一ドフレームアウターリード部６の形状がカモ
メが飛んでいる時の羽根の形状に似ていることから、Ｑ
ＦＰとｓａｐの半導体パッケージ装置は、ガルウィング
（Ｇｕ：ｃ１ ｗｔｎｇ）型の半導体パッケージ装置と
も呼ばれている。Q
The FP and SAP semiconductor package devices are also called gull wing (Gu:c1 wtng) type semiconductor package devices.
［発明が解決しようとする課題コ
しかし、前述の従来技術では以下に述べるような問題点
を有する。[Problems to be Solved by the Invention] However, the above-mentioned prior art has the following problems.
すなわち，ＱＦＰとＳＯＰの半導体パッケージ装置にお
いては、リードフレームアウターリード部６に屈曲部８
を付けた後の半導体パッケージ装置の取り扱いあるいは
搬送の際に、リードフレームアウターリード部６のＸ方
向またはＹ方向または２方向の変形が発生しやすいとい
う欠点があった。Ｘ方向またはＹ方向の変形を「リード
曲り」２方向の変形を「リード浮き」などと呼ぶ。リー
ドフレームアウターリード部乙の変形のうちで、特に「
リード浮き」の発生した半導体パッケージ装置をプリン
ト基板９等にハンダ付けする時にリードフレームアウタ
ーリード部６とプリンタ基板９上のハンダ付け用ランド
１０との間に隙間が生じて、適性なハンダ付けを行なう
ことが困難になり、程度がひどくなるとハンダ付けがま
ったくできなくなってしまうという問題点を生ずる。That is, in QFP and SOP semiconductor package devices, the lead frame outer lead portion 6 has a bent portion 8.
There is a drawback in that the lead frame outer lead portion 6 is likely to be deformed in the X direction, the Y direction, or two directions when handling or transporting the semiconductor package device after attaching the lead frame. Deformation in the X or Y direction is called "lead bending," and deformation in two directions is called "lead floating." Of the deformations of the lead frame outer lead part B, especially
When soldering a semiconductor package device with "lead floating" to a printed circuit board 9, etc., a gap is created between the lead frame outer lead part 6 and the soldering land 10 on the printer board 9, making it difficult to solder properly. Soldering becomes difficult, and if the situation becomes severe, it becomes impossible to solder at all.
これらを第４図，第５図および第６図を用いて説明する
。第４図は、ＱＦＰとＳＯＰの半導体バ，ケージ装置を
プリント基板９ヘハンダ付けした適性な状態を示す図で
ある。リードフレームアウターリード部６に「リード浮
き」が無いために、リードフレームアウターリード部６
とハンダ付け用ランド１０との間は密着しており、適正
なハンダ付けが得られている。第５図は、「リード浮き
」のあるＱＦＰとＳＯＰの半導体パッケージ装置をプリ
ント基板９ヘハンダ付けした状態を示す図である。リー
ドフレームアウターリード部６とハンダ付け用ランド１
０との間に隙間が生じて、第４図に示す状態に比べて適
正なハンダ付けが得られていない。第６図は、さらに「
リード浮き」のあるＱＦＰとＳＯＰの半導体パッケージ
装置をプリント基板９等にハンダ付けした状態を示す図
である。リードフレームアウターリード部６とハンダ１
１が接しておらず、まったくハンダ付けされていない状
態である。ハンダ付け条件にもよるが、０．１ ｗ〜０
．１ ５ｍｍ程度の「リード浮き」が発生すると適正な
ハンダ付けができなくなると言われている。These will be explained using FIGS. 4, 5, and 6. FIG. 4 is a diagram showing a suitable state in which QFP and SOP semiconductor bags and cage devices are soldered to the printed circuit board 9. Since there is no “lead floating” in the lead frame outer lead portion 6, the lead frame outer lead portion 6
There is close contact between the soldering land 10 and the soldering land 10, and proper soldering is obtained. FIG. 5 is a diagram showing a state in which QFP and SOP semiconductor package devices with "lead floating" are soldered to a printed circuit board 9. Lead frame outer lead part 6 and soldering land 1
0, and proper soldering is not obtained compared to the state shown in FIG. 4. Figure 6 further shows “
2 is a diagram showing a state in which QFP and SOP semiconductor package devices with floating leads are soldered to a printed circuit board 9, etc.; FIG. Lead frame outer lead part 6 and solder 1
1 are not in contact and are not soldered at all. Depending on the soldering conditions, 0.1w~0
．． It is said that if a "lead float" of about 15 mm occurs, proper soldering will not be possible.
なお、「リード浮き」の状態は１個のりードフレームア
ウターリード部６で発生することは珍しく、隣どうしの
連続したリードフレームアウターリード部６で発生する
のが普通であるために、一旦「リード浮き」の発生した
リード７レームアウターリード部６を元の状態へ戻すこ
とは極めて困難であり、実際には不良としている。It should be noted that the "lead floating" condition rarely occurs in one lead frame outer lead section 6, but usually occurs in adjacent lead frame outer lead sections 6 that are continuous. It is extremely difficult to return the lead 7-frame outer lead portion 6 in which "lead floating" has occurred to its original state, and it is actually considered defective.
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは適性なハンダ付け状態の得られる
ＱＦＰとＳＯＰの半導体パッケージ装置を提供するとこ
ろにある。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a QFP and SOP semiconductor package device in which a suitable soldering condition can be obtained.
［課題を解決するための手段］
本発明のＱ，ＦＰとＳＯＰの半導体パッケージ装置は、
リードフレームのアウターリード部の屈曲部が封止材の
内部にあることを特徴とする。[Means for Solving the Problems] The Q, FP and SOP semiconductor package device of the present invention has the following features:
It is characterized in that the bent portion of the outer lead portion of the lead frame is inside the sealing material.
［実施例コ
第１図（α）は本発明の実施例のＱＩＦＰの外観を示す
図であり、第１図（ｂ）は第１図（α）のＡＡ’部の断
面を示した図である。[Example 1] Figure 1 (α) is a diagram showing the external appearance of a QIFP according to an example of the present invention, and Figure 1 (b) is a diagram showing a cross section of section AA' in Figure 1 (α). be.
また、第８図（α）〜（ ／．）は本発明の実施例の製
造順の一例を示す図である。Further, FIGS. 8(α) to (/.) are diagrams showing an example of the manufacturing order of the embodiment of the present invention.
第８図（α）〜（／）の実施例の製造順の一例によれば
、まず第８図（α）に示すリードフレームアウターリー
ド部６に屈曲部８を付け（第８図（ｈ））て、第８図（
ｃ）に示すようにリードフレームダイパッド部４に工Ｃ
チクブ１を固着するその後工Ｃチップ１とリードフレー
ムインナーリード部５とを極細金線３等で接続し（第８
図（ｄ））．第８図（ｃ）に示すように封止材７を用い
て、リードフレームアウターリード部６の屈曲部８を覆
うように封止を行なう。そして第８図（ｆ）に示すよう
に、リードフレームアウターリード部６を適当な長さに
切断する。According to an example of the manufacturing order of the embodiments shown in FIGS. 8(α) to (/), first, the bent portion 8 is attached to the lead frame outer lead portion 6 shown in FIG. 8(α) (FIG. 8(h)). ), Figure 8 (
C) on the lead frame die pad part 4 as shown in c).
After the process of fixing the chip 1, the C chip 1 and the lead frame inner lead part 5 are connected with an ultra-fine gold wire 3 or the like (No. 8
Figure (d)). As shown in FIG. 8(c), sealing is performed using a sealing material 7 so as to cover the bent portion 8 of the lead frame outer lead portion 6. Then, as shown in FIG. 8(f), the lead frame outer lead portion 6 is cut to an appropriate length.
このようにして、アウターリード部６の屈曲部８が封止
材７の内部にある゛ＱＦＰの半導体パッケージ装置が完
或し、第１図（α）がその外観図である。In this way, a QFP semiconductor package device in which the bent portion 8 of the outer lead portion 6 is inside the sealing material 7 is completed, and FIG. 1(α) is an external view thereof.
以上からわかるように、本発明の半導体パ，ケージ装置
では、封止材７等で封止を行なう前にリ一ド７レームア
ウターリード部６に屈曲部８を与える必要がある。第８
図では工Ｃチップ１をリードフレームダイパッド部４に
固着する前（第８図（ｂ））にこれを行なっているが、
例えば工ｃチツブ１をリードフレームダイパッド部４と
を固着した直後（第８図（ｃ）の時）に、あるいは工０
チップ１とり十ドフレームインナーリード部５とを接続
した直後（第８図Ｃｄ）の時）に、リード７レームアウ
ターリード部６に屈曲部８を付けても同様の半導体パッ
ケージ装置が得られることは明らかである。As can be seen from the above, in the semiconductor package and cage device of the present invention, it is necessary to provide the bent portion 8 to the lead 7 frame outer lead portion 6 before sealing with the sealing material 7 or the like. 8th
In the figure, this is done before fixing the C-chip 1 to the lead frame die pad part 4 (FIG. 8(b)).
For example, immediately after fixing the die pad part 4 of the lead frame to the die pad part 4 (as shown in FIG. 8(c)), or
A similar semiconductor package device can be obtained even if the bent portion 8 is attached to the lead 7 frame outer lead portion 6 immediately after the chip 1 is connected to the lead frame inner lead portion 5 (at the time shown in Fig. 8Cd). is clear.
本発明の半導体パッケージ装置の実施例をＱＦＰを用い
て説明したが、ＳＯＰでも同様に実施できることは明ら
かであ゛る。Although the embodiment of the semiconductor package device of the present invention has been described using a QFP, it is clear that it can be implemented in the same way with an SOP.
［発明の効果］
以上述べたように本発明のＱＦＰとＳＯＰの半導体パッ
ケージ装置によれば、リードフレームのアウターリード
部の屈曲部が封止材の内部に存在することにより、「リ
ード浮き」の発生がごく軽微に押えられるために、これ
をプリント基板等へハンダ付けし際に適正なハンダ付け
状態を得ることができるという効果を有する。[Effects of the Invention] As described above, according to the QFP and SOP semiconductor package devices of the present invention, "lead floating" is prevented because the bent portion of the outer lead portion of the lead frame exists inside the sealing material. Since the occurrence of the soldering is suppressed to a very small extent, it is possible to obtain a proper soldering condition when soldering this to a printed circuit board or the like.
また、封止材の外部に出ているリードフレームのアウタ
ーリード部の部分を短くすることができるので、半導体
パッケージ装置の全体の大きさを小さくでき、高密度実
装が可能となるという効果を有する。In addition, since the outer lead portion of the lead frame that is exposed outside the encapsulant can be shortened, the overall size of the semiconductor package device can be reduced and high-density packaging is possible. .
さらに、リードフレームのアウターリード部が封止材の
内部で屈曲しているために、アウターリードの引き抜か
れる強さである引き抜き強度が増す。このことはアウタ
ーリードの界面を伝わって半導体パッケージ装置外部か
らの水分等が侵入しにくくなるということを意味し、こ
れら水分等の腐蝕などによる工０チップの不良が著しく
低下するために、半導体パッケージ装置の１６頼性が向
上するという効果を有する。Furthermore, since the outer lead portion of the lead frame is bent inside the sealing material, the pull-out strength, which is the strength with which the outer lead can be pulled out, is increased. This means that moisture, etc. from outside the semiconductor package device is difficult to penetrate through the interface of the outer lead, and the number of chip failures due to corrosion due to moisture, etc. is significantly reduced. This has the effect of improving the reliability of the device.
第１図（α）は本発明の半導体パッケージ装置の一実施
例の外観を示す図。
第１図（ｂ）は第１図（α）のＡＡ’部の断面を示す図
。
第２図（α）は従来のＱＦＰ半導体パッケージ装置の外
観を示す図。
第２図Ｃｈ）は第２図（α）のＡＡ’部の断面を示す図
。
第３図（α）は従来のＳＯＰ半導体パッケージ装置の外
゜観を示す図。
第５図（ｂ）は第３図（α）のＡＡ’部の断面を示す図
。
第４図は従来の半導体パッケージ装置の適性なハンダ付
け状態を示す図。
第５図および第６図は従来の半導体パッケージ装置の適
性でないハンダ付け状態を示す図。
第７図（α）〜（／）は従来の半導体パッケージ装置の
製造順を示す図。
第８図（α）〜（／）は本発明の実施例の製造順の一例
を示す図。
１・・・・・・・・・工Ｏチップ
２・・−・・・・・・外部接続用パッド３・・・・・・
・・・極細金線
４・・・・・・・・・リードフレームダイパッド部５・
・・・・・・・・リードフレームインナーリード部６・
・・・・・・・・リードフレームアウターリード部７・
・・・・・・・・封止材
８・・・・・・・・・屈曲部
９・・・・・・・・・プリント基板
１０・・・・・・・・・ハンダ付け用ランド１１・・・
・・・・・・ハンダ
以
上FIG. 1(α) is a diagram showing the appearance of an embodiment of the semiconductor package device of the present invention. FIG. 1(b) is a cross-sectional view taken at the AA' portion of FIG. 1(α). FIG. 2 (α) is a diagram showing the appearance of a conventional QFP semiconductor package device. Fig. 2 Ch) is a cross-sectional view taken at the AA' section of Fig. 2 (α). FIG. 3(α) is a diagram showing the appearance of a conventional SOP semiconductor package device. FIG. 5(b) is a cross-sectional view taken at section AA' in FIG. 3(α). FIG. 4 is a diagram showing a proper soldering state of a conventional semiconductor package device. FIGS. 5 and 6 are diagrams showing improper soldering conditions in a conventional semiconductor package device. FIG. 7 (α) to (/) are diagrams showing the manufacturing order of a conventional semiconductor package device. FIG. 8 (α) to (/) are diagrams showing an example of the manufacturing order of the embodiment of the present invention. 1......O-chip 2...-...External connection pad 3...
...Ultra-fine gold wire 4...Lead frame die pad part 5.
・・・・・・Lead frame inner lead part 6・
・・・・・・Lead frame outer lead part 7・
..... Sealing material 8 ..... Bent part 9 ..... Printed circuit board 10 ..... Soldering land 11 ...
・・・・・・More than solder
Claims (1)
たのち、極細金線等を用いて前述ＩＣチップの外部接続
用パッドと前述リードフレームのインナーリード部とを
接続し、樹脂封止材等の封止材を用いて封止を行なった
半導体パッケージ装置のうち、表面実装型と呼ばれるＱ
ＦＰとＳＯＰとの半導体パッケージ装置において、 前述リードフレームのアウターリード部の屈曲部が前述
封止材の内部に存在することを特徴とする半導体パッケ
ージ装置。[Claims] After the IC chip is fixed to the die pad portion of the lead frame, the external connection pads of the IC chip and the inner lead portion of the lead frame are connected using ultra-fine gold wire, and then resin-sealed. Among semiconductor package devices that are sealed using a sealing material such as
A semiconductor package device of FP and SOP, characterized in that a bent portion of an outer lead portion of the lead frame is present inside the sealing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP169690A JPH03206651A (en) | 1990-01-09 | 1990-01-09 | semiconductor packaging equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP169690A JPH03206651A (en) | 1990-01-09 | 1990-01-09 | semiconductor packaging equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03206651A true JPH03206651A (en) | 1991-09-10 |
Family
ID=11508699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP169690A Pending JPH03206651A (en) | 1990-01-09 | 1990-01-09 | semiconductor packaging equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03206651A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05243448A (en) * | 1992-02-28 | 1993-09-21 | Nec Kyushu Ltd | Package for integrated circuit |
| JP2018057590A (en) * | 2016-10-05 | 2018-04-12 | 株式会社パジコ | Accessory, manufacturing method thereof, and eye bolt for accessory |
-
1990
- 1990-01-09 JP JP169690A patent/JPH03206651A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05243448A (en) * | 1992-02-28 | 1993-09-21 | Nec Kyushu Ltd | Package for integrated circuit |
| JP2018057590A (en) * | 2016-10-05 | 2018-04-12 | 株式会社パジコ | Accessory, manufacturing method thereof, and eye bolt for accessory |
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