JPH03206510A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device including an oscillation circuit, and particularly to an oscillation circuit that responds to changes in its driving voltage.

[Prior art and problems to be solved by the invention] In conventional semiconductor devices, for example, reference voltage generation circuits that generate different voltages as reference voltages are provided, and one of them is selected based on a command from a CPU. There are some devices that use this as a driving voltage for the CPU. In other words, the low drive voltage and the high drive voltage are switched as necessary depending on the processing speed of the CPU.

However, since the same drive voltage as the CPU is applied to the oscillation circuit, the drive capability of the oscillation inverter forming the oscillation circuit varies as follows depending on the magnitude of the drive voltage.

a> Oscillation When the inverter was designed to have a low driving capacity and the power supply voltage of the oscillation circuit was switched to a lower one, oscillation was likely to stop, and conversely, when oscillation was stopped, it was difficult to start oscillation.

b> If the oscillation inverter is designed to have a high driving capacity and the power supply voltage of the oscillation circuit is switched to a higher side, harmonic oscillation will occur and the device will malfunction.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can stably oscillate even when the power supply voltage of an oscillation circuit is switched.

[Means for Solving the Problems] A semiconductor device according to the present invention includes a plurality of reference voltage generation circuits each generating a different reference voltage, and a selection signal for selecting the reference voltage generation circuit based on a command from a CPU. An analog switch is provided corresponding to the selection control storage circuit for storing data and the reference voltage generation circuit, and is opened based on the selection signal and sends out the reference voltage from the reference voltage generation circuit. The oscillation inverter is provided corresponding to each circuit and is supplied with a reference voltage as a driving voltage.The oscillation signal of the oscillation inverter selected based on the selection signal is supplied as a system clock to the microcomputer. and a low frequency oscillation circuit.

Here, the low frequency oscillation circuit has a plurality of oscillation inverters each having a different drive capacity, and the higher the drive capacity is supplied with a lower drive voltage and oscillates at a lower frequency, and the lower the drive capacity is, the higher the drive capacity is. When a voltage is supplied, it similarly oscillates at a low frequency.

For example, when the low frequency oscillation circuit includes two oscillation inverters, one of the oscillation inverters has a high driving capability and is supplied with a low driving voltage from the analog switch. The other oscillation inverter has a low driving capability, is supplied with a high driving voltage from the analog switch, and has the same oscillation frequency as the former.

Alternatively, an operational amplifier may be provided between the analog switch and the low frequency oscillation circuit, and the reference voltage sent from the analog switch may be stabilized before being sent to the low frequency oscillation circuit.

Here, the microcomputer includes a CPU that executes arithmetic functions and controls computer operations;
a data bus coupled to the CPU for sending and receiving data; an address bus coupled to the CPU; a ROM coupled to the data bus and the address bus and storing a program that determines the operation of the computer; A RAM is connected to the data bus and the address bus and stores data for arithmetic processing.

Further, the semiconductor device according to the present invention includes a high frequency oscillation circuit to which a reference voltage from an operational amplifier is supplied as a driving voltage;
A high frequency oscillation control circuit that controls the drive of the high frequency oscillation circuit based on a command from the CPU, and a switching control signal that selects either the output of the low frequency oscillation circuit or the output of the high frequency oscillation circuit based on the command from the CPU. The clock switching control circuit that outputs the clock, and the switching control signal from the clock switching control circuit are manually selected to select either the output of the low frequency oscillation circuit or the output of the high frequency oscillation circuit, and are synchronized and sent to the computer. It has a clock synchronization circuit that sends out a system clock.

Also, connect the reset signal line to the CPU of the microcomputer.
, a selection control storage circuit, a high frequency oscillation control circuit, and a clock switching control circuit, and is initialized when the power is turned on or when the device is initialized.

[Function] In the present invention, the selection control storage circuit stores a selection signal for selecting a reference voltage generation circuit based on a command from the CPU, and the analog switch performs an opening operation based on input of the selection signal. Selects and outputs the reference voltage from the reference voltage generation circuit.

Further, the oscillation inverter of the oscillation circuit reference voltage is also selected based on the input of the selection signal, and the selected reference voltage is supplied via the analog switch. For example, when the reference voltage is low, an oscillation inverter with high drive capacity is selected, and when the reference voltage is high, an oscillation inverter with low drive capacity is selected, and the oscillation inverter stably oscillates and the oscillation signal is sent to the microcomputer. Supplied as system clock.

An operational amplifier was installed between the analog switch and the low-frequency oscillation circuit. In this case, the reference voltage sent out from the analog switch is stabilized and then output to the low frequency oscillation circuit.

[Embodiment] FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present invention. The microcomputer 100 is a CPU that executes arithmetic functions, controls computer operations, etc.
It is composed of a ROM 104 in which system programs etc. for driving the CPU 102 are stored, a RAM 10B in which various data are stored, an address bus 108, and a data bus 110 for exchanging data. . CPU102, ROM104 and R
A M 10B are interconnected via this address bus 108 and data bus 110.

The selection control storage circuit 112 is composed of, for example, a decoder and a latch circuit such as a D-type flip-flop circuit or a register, and is set to "1" or "0" based on the arithmetic processing of the CPU 102. This configuration is the same for the high frequency oscillation control circuit ta4 and clock switching circuit 18B, which will be described later.

The reference voltage generation circuits 114 and 118 generate different reference voltages, for example, the reference voltage generation circuit II6 generates a higher voltage than the reference voltage generation circuit 114. Analog switches 118 and 122 are coupled to reference voltage generation circuits 114 and 116, respectively, and select one of the reference voltages in response to a selection control signal 113 from selection control storage circuit 112. Note that the analog switch 118
is connected to the analog switch 12 via the inverter 120.
Since the direct selection control signal 113 is input to 0, the two analog switches 118 and 122 do not become conductive at the same time, and the analog switches 118 and 122 always operate in opposite directions.

The operational amplifier 124 is connected to analog switches 118 and 12
2 is stabilized and output as a drive voltage to the microcomputer 100, low frequency oscillation circuit 12B, and high frequency oscillation circuit 132.

The low frequency oscillation circuit 12B is an oscillation inverter with high driving capacity.
28, and an oscillation inverter I30 having a lower driving force than the oscillation inverter 128, and these are selected by the selection control signal 113. Oscillation inverter 128 of this low frequency oscillation circuit 12B. The driving ability of the inverter 180 is varied by making a difference in the ratio W/L between the channel width W and the channel length L of the FETs constituting the inverter. The larger the W/L, the greater the driving capacity.

The high frequency oscillation circuit 132 is composed of, for example, a CR oscillation circuit, and its operation is controlled by the high frequency oscillation control circuit 134. The clock switching control circuit 13B is the CPU 102
Outputs switching signals based on control commands from The clock synchronization circuit 138 inputs the oscillation signals from the low frequency oscillation circuit 126 and the high frequency oscillation circuit 132, and changes the oscillation signal from the low frequency oscillation circuit 126 or the high frequency oscillation circuit 132 based on the switching signal from the clock switching control circuit 136. After being selected and synchronized, it is output to the CPU 102 as the system clock 139. The frequency dividing circuit 140 inputs the oscillation signal from the low frequency oscillation circuit 12B, and
An interrupt signal 141 is output to U 102. The reset control line 144 is connected to the CPU 102 and the selection control storage circuit 1.
12, connected to the high frequency oscillation control circuit 184 and the clock switching control circuit 136, and outputs a reset signal.

FIG. 2 shows the reference voltage generation circuits 114 and 116 in FIG.
, analog switches 118 and 122, an inverter 120, and a low frequency oscillation circuit 126. FIG.

Next, the operation of the semiconductor device of this embodiment configured as described above will be explained.

First, when a reset signal is input from the outside to the reset signal line 144, the CPU 102 and the selection control storage circuit 112
, the high frequency oscillation control circuit 134, and the clock switching control circuit 136 are each initialized. In other words, CPU10
The program counter 2 is set to the initial address.

'0' is set in the selection control storage circuit 112, and its output becomes LOW level (hereinafter referred to as L level).
The high frequency oscillation control circuit 134 is set to “0” as its initial state.
is set, and the output signal stops the high frequency oscillation circuit 132.

The clock switching control circuit 13B is set to “0” as its initial state.
" is set, and the selection control signal causes the clock synchronization circuit 13g to select the oscillation signal of the low frequency oscillation circuit 12B.

Next, the analog switch 118 is turned ON and the analog switch 122 is turned OFF by the initialization output (L level) of the selection control storage circuit 112, and the voltage generated by the reference voltage generation circuit 114, for example, I
V is supplied. The operational amplifier 124 stabilizes the input voltage, outputs it, and supplies it to the microcomputer 100, the low frequency oscillation circuit 12B, and the high frequency oscillation circuit 132 as a driving voltage.

Further, the initialization output of the selection control storage circuit 112 selects the oscillation inverter 128 with the higher driving ability from the two oscillation inverters of the oscillation circuit 12B. Oscillation inverter 12
8 starts driving, and the signal with an oscillation frequency of 32 KHz is sent to the CPU 10 via the clock synchronization circuit 138.
2 as the system clock 139.

1. When the signal on the reset signal line 144 enters the reset release state, the CPU 102 starts operating and connects the address bus 1.
08 and the data bus 110 to read the program from the ROM 104. Then, the CPU 102
Read and write data to M10B in ROM104
By executing the program read from
Operation as a computer is realized.

Furthermore, when the CPU 102 analyzes an instruction to drive the CPU 102 with a high power supply voltage in the process of executing the program in the ROM 104, the CPU 102
outputs the address data assigned to the selection control storage circuit 112 to the address bus 108, and
Data "1" is written to the selection control storage circuit 112 via the control circuit 10. As a result, the output of the selection control storage circuit 112 becomes HIGH level. Therefore, contrary to the above case, the analog switch 118 is turned OFF and the analog switch 122 is turned ON. As a result, the reference voltage generation circuit li
The reference voltage generated from ft, for example 2v, is applied to the operational amplifier 12.
Enter 4.

The operational amplifier 124 stabilizes and strengthens the input voltage and outputs it to the microcomputer t00 and low frequency oscillation circuit 1.
2B and the high frequency oscillation circuit 132 as a driving voltage. Further, the output of the selection control storage circuit 114 is the output of the oscillation circuit 1
Of the two oscillation inverters 26, the oscillation inverter 130 with the lowest driving capacity is selected. Oscillation inverter l30
starts driving, and a signal with an oscillation frequency of, for example, 32KHZ is sent to the CPU 1 via the clock synchronization circuit 138.
02 as the system clock 139.

Figure 3 shows the oscillation inverter 128 of the low frequency oscillation circuit 12B.
, 1.30 and the stability region. For example, the oscillation inverter 12g with high driving capacity has a low driving voltage range Va (approximately 0.7 to 1.7 V).
The oscillation operation becomes stable, and when the drive voltage drops beyond that range, the oscillation stops, and when the drive voltage rises beyond that range, harmonic oscillation occurs. The oscillation inverter 130 with low driving capacity has a high driving voltage range Vb (approximately {,5~
The oscillation operation becomes stable at a voltage of 2.5 V), and when the driving voltage falls beyond that range, the oscillation is stopped, and when the driving voltage rises beyond that range, harmonic oscillation occurs.

Therefore, in the embodiment of FIG.
4 is set as I■, and the reference voltage generation circuit 116
If the generated voltage is set to 2V, the reference voltage generation circuit 11
Even if the oscillation inverters 128 and 180 are switched from 4 to the reference voltage generation circuit ll6, each of the oscillation inverters 128 and 180 operates stably, and even if the drive voltage becomes high, the low frequency oscillation circuit 12
B's oscillation frequency does not change, and the system clock's 139
It can be seen that the frequency of does not change either.

Further, when the CPU 102 reads out the program in the ROM 104 and performs arithmetic processing, when there is a command to drive the high frequency oscillation circuit 132, the selection control storage circuit 112, the high frequency oscillation control circuit 134, and the clock switching control circuit 136 is set to "1".

The high frequency oscillation circuit 132 starts driving and, for example, 3 M
The clock synchronization circuit 13 generates an oscillation frequency of Hz.
System clock 13 to CPU 102 via 8
Output as 9.

1 6 FIG. 4 shows the oscillation inverter 128 of the low frequency oscillation circuit 126.
．． FIG. 2 is a characteristic diagram showing the relationship between the oscillation frequency and drive voltage of the high-frequency oscillation circuit 130 and the high-frequency oscillation circuit 132. For example, a low drive voltage is applied to the oscillation inverter 128 with a high drive capacity, and a high drive voltage is applied to the oscillation inverter 130 with a low drive capacity, and their oscillation frequencies are the same and low. Further, the high frequency oscillation circuit 132 is supplied with a high driving voltage and has a high oscillation frequency, and a high frequency system clock 139 is supplied to the CPU 102 via the clock synchronization circuit 138.

Although the above embodiment shows an example in which two reference voltage generation circuits are provided, three or more reference voltage generation circuits may be provided, and in that case, the number of analog switches and oscillation inverters of the low frequency oscillation circuit is adjusted accordingly. Provide a corresponding number of pieces.

[Effects of the Invention] As described above, according to the present invention, the oscillation circuit is configured with a plurality of oscillation inverters having characteristics corresponding to the reference voltage,
Since the selection is made according to the drive voltage of the CPU, fluctuations in the drive capacity of the oscillation inverter that occur when the drive voltage is switched by program are eliminated, and as a result, oscillation starts easily when the power is turned on, and the power supply It is possible to realize a semiconductor device that exhibits good characteristics such that oscillation stops when the voltage drops and that harmonic oscillations are difficult to occur.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a specific example of a part of the configuration shown in FIG. FIG. 3 is a characteristic diagram showing the relationship between a low capacity oscillation inverter, a high capacity oscillation inverter, and drive voltage. FIG. 4 is a characteristic diagram showing the relationship between the low frequency range, high frequency range, and drive voltage. 100...Microcomputer, l02...CP
U, 104...ROMS10B...RAMS108
...Data bus, 110...Address bus, 1l2
...Selection control storage circuit, 114. 116... Reference voltage generation circuit, 118, 122... Analog switch, 124... Operational amplifier, 12B... Low frequency oscillation circuit, 128, 130... Oscillation inverter. 8) ■u skewer times 01゛N

Claims (7)

[Claims] (1) A plurality of reference voltage generation circuits that generate different reference voltages, a selection control storage circuit that stores a selection signal for selecting the reference voltage generation circuit based on a command from a CPU, and the reference voltage generation circuit. an analog switch provided correspondingly to the reference voltage generating circuit and configured to open based on input of the selection signal to send out the reference voltage from the reference voltage generating circuit; and an analog switch provided correspondingly to the reference voltage generating circuit; A low-frequency oscillation device comprising an oscillation inverter to which the reference voltage from the analog switch is supplied as a driving voltage, and supplies an oscillation signal of the oscillation inverter selected based on the input of the selection signal as a system clock to the microcomputer. A semiconductor device having a circuit. (2) The low frequency oscillation circuit has a plurality of oscillation inverters each having a different drive capacity, the higher the drive capacity is, the lower the drive voltage is supplied, and the lower the drive capacity is, the higher the drive voltage is supplied, and Claim 1: The oscillation frequencies are the same.
The semiconductor device described. (3) The low frequency oscillation circuit has two oscillation inverters,
One oscillating inverter has a high drive capability and a low drive voltage is supplied by one analog switch, the other oscillating inverter has a low drive capability and a high drive voltage is supplied by the other analog switch, and both 2. The semiconductor device according to claim 1, wherein the oscillation frequencies are the same. (4) The semiconductor device according to claim 3, further comprising an operational amplifier that stabilizes the reference voltage sent out from the analog switch and then sends it out to the low frequency oscillation circuit. (5) a CPU that executes arithmetic functions and controls computer operations; a data bus that is coupled to the CPU and that exchanges data; an address bus that is coupled to the CPU; and the data bus and the address 4. A microcomputer comprising: a ROM coupled to a bus and storing a program that determines the operation of the computer; and a RAM coupled to the data bus and the address bus and storing data for arithmetic processing. The semiconductor device described. (6) a high-frequency oscillation circuit to which a reference voltage from an operational amplifier is supplied as a driving voltage; a high-frequency oscillation control circuit that controls driving of the high-frequency oscillation circuit based on a command from a CPU; a clock switching control circuit that outputs a switching control signal for selecting either the output of the low frequency oscillation circuit or the output of the high frequency oscillation circuit; 6. The semiconductor device according to claim 5, further comprising a clock synchronization circuit that selects one of the output and the output of the high frequency oscillation circuit, synchronizes the output, and sends the synchronized signal to the computer as a system clock. (7) The semiconductor device according to claim 6, further comprising a reset signal line that is coupled to the CPU of the microcomputer, the selection control storage circuit, the high frequency oscillation control circuit, and the clock switching control circuit, and is initialized when the power is turned on or the device is initialized. .