JPH0319974B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an interrupt control device for a data processing device, and more particularly to a control method for determining interrupts for a data processing device that processes interrupts in order starting from the highest priority interrupt request.

Prior Art Conventionally, interrupt control for a data processing device that has a plurality of execution process levels and sequentially executes processes corresponding to the highest priority interrupt level has been performed using the following procedure.

First, a plurality of interrupt level signals input from a plurality of ports are respectively decoded, the decoded level signals are collected for each level, and the highest priority level is determined through a priority circuit. Next, select the port with the interrupt level corresponding to the highest priority level. When there are a plurality of such ports, the selected port is further passed through a priority circuit to determine the highest priority port. Next, interrupt address information corresponding to the highest priority port is selected. Then, comparing the highest priority level and the current execution level,
Interrupts the higher-level processing unit when the interrupt level is higher.

Conventional interrupt control devices that perform the above-described procedure have the drawbacks of complex control and large hardware requirements.

OBJECT OF THE INVENTION The object of the invention is to solve the above-mentioned conventional drawbacks and
An object of the present invention is to provide an interrupt control device that has a simple processing procedure and a small amount of hardware.

Composition of the Invention The interrupt control device of the present invention is an interrupt control device that inputs an interrupt level signal and an interrupt address signal for a plurality of interrupt requests, and controls interrupt requests to a data processing device that processes interrupts in order starting from the highest priority. , a current processing level register holding the currently executing process level;
a plurality of level comparators that respectively compare interrupt level signals input from a plurality of ports with the output of the current processing level register and output an interrupt enable signal for an interrupt level signal having a higher priority than the current processing level; a port designation circuit that selects any one of the level comparators inputting the outputs of the plurality of level comparators and outputs the interrupt enable signal and outputs the corresponding port number; and the port designation circuit. a level signal selection circuit that selects and outputs the interrupt level signal input to the corresponding port by the output of the port designation circuit; and interrupt address information that selectively outputs the interrupt address information input to the corresponding port by the output of the port designation circuit. a selection circuit, and the interrupt enable signal is at least one
means for generating an interrupt signal when detecting that an interrupt exists, and selects any one of the ports in which an interrupt of a higher level than the currently executing process level has occurred, and inputs the interrupt level signal to the port. The data processing apparatus is characterized in that the data processing apparatus is interrupted by interrupt address information.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of a data processing device to which the present invention is applied. That is, the processing device 2 is a processing device having execution process levels of levels 0 to 7. Input/output channel device 3~
8 connects various peripheral devices (not shown);
Controls data transfer with the main storage device 9. The main storage device 9 is a memory for storing programs and data to be processed. System control device 1
controls access to the main storage device 9 from the processing device 2 and output channel devices 3 to 8, and
Interrupt signals from input/output channel devices 3 to 8 (including interrupt level signals and interrupt address information)
It includes an interrupt control device of the present invention for receiving and interrupting the processing device 2. The above-mentioned interrupt signal includes, for example, an interrupt level signal coded in 3 bits and 8-bit interrupt address information. The interrupt level is a level that is fixedly determined in advance in response to an interrupt event, and is determined by the transfer speed of the peripheral device and the type of processing request. The interrupt address is set to each input/output channel device 3 to 8 by a program from the processing device 2 at the time of system initialization.
Different values are set for interrupt events. The interrupt address information is added to the base address of the interrupt vector during process transition control in the processing device 2 and used to obtain an interrupt vector corresponding to an interrupt event. Interrupt vector is instruction counter
It consists of an IC, process control register PSR, page base register PTBR, etc., and defines the start address and mode of the interrupt processing program.

FIG. 2 is a circuit diagram showing an embodiment of the present invention, and the present interrupt control device is used as a built-in part of the system control device 1. As shown in FIG. Interrupt level signal LA input from ports A to G of system control device 1
~LG and interrupt address information AA~AG are input to the level signal selection circuit 111 and interrupt address information selection circuit 112, respectively, and in the level comparison circuits 102 to 108, the current execution output from the current processing level register 110, which will be described later, is compared to the internal process level. As for interrupt levels, level 0 has the highest priority, and level 7
is defined as the lowest rank.

The current processing level register 110 is initially set to the lowest priority level 7 by an initialize signal, and a new higher level to be interrupted next is set by an interrupt acceptance signal given from a processing device (not shown). . Further, it is reset to level 7 by a release signal of the processing process from the processing device. The release signal of the processing process is issued by the program at the end of the interrupt processing program, and signifies the completion of the interrupt processing program.

The output of the current processing level register 110 is connected to one input of the level comparators 101 to 108, and the comparison circuits 102 to 108 receive interrupt level signals LA to 1 from each port, respectively, as described above.
The level of LG and the output of the current processing level register 110 are compared, and if the level of the interrupt level signal is higher, an interrupt enable signal is generated and input to the port designation circuit 109. Level comparator 101
is an old level comparator that compares the output of the current processing level register 110 and the output of an old register encode circuit 116, which will be described later, and outputs an interrupt enable signal when the output of the old register encode circuit 116 is at a higher level. be.

Furthermore, as will be described later, the level signal selection circuit 111 outputs a level signal 503 to be processed next based on the output of the port designation circuit 109 and inputs it to the currently processed level register 110, and also outputs a level signal 503 to be processed next, and inputs the level signal 503 to the current processing level register 110. The setting decoder circuit 113 decodes the interrupt acceptance signal from the processing device and sets the corresponding bit of the old level register 115 to "1". Then, when the current processing level is released, the current processing level register 1
The output of 10 is decoded by the reset decoder circuit 114 and output to the old level register 11.
The corresponding bit of 5 is reset to "0".
The old level register 115 has levels 0 to 7.
This is an 8-bit register that corresponds to
is initially set to . This old level register 115 sets bits to "1" corresponding to the level currently being processed and the process level that has been suspended due to a new higher-level interrupt, which will be described later. This is a register used to control restart. The old register encode circuit 116 corresponds to (encoded) the highest level of the interrupt levels pending in the old level register 115.
An interrupt level signal is output and inputted to one input of the comparison circuit 101. That is, the interrupt level signal corresponding to the highest pending process level is compared in the old level comparator 101 with the level currently being processed.

The interrupt valid signals output from the level comparators 101 to 108 are inputted to one specific port O and ports A to G of the port designation circuit 109, respectively. The port designation circuit 109 assigns levels to ports A to G in order, with port O being the highest level. Therefore, the output 501 of the port designation circuit 109
is a signal indicating the highest port number (code "0" for old level, code "7" for port G). By this signal, the level signal selection circuit 1
11 and the interrupt address information selection circuit 112 are controlled, and the level signal selection circuit 111
selectively outputs the interrupt level signal corresponding to the designated port number, and the interrupt address information selection circuit 112 selectively outputs the address information corresponding to the designated port number. Further, the port designation circuit 109 outputs an interrupt signal based on the logical sum of the interrupt valid signals output from the level comparators 101 to 108.
502 and sends it to the processing device 2. The processing device 2
When the interrupt signal 502 is received and the interrupt acceptance signal is given to the current processing level register 110, the output 503 of the level selection circuit 111 is set to the current processing level register 110, and the output of this register and the output of the address information selection circuit 112 are set. address information 504 is sent to the processing device 2. As a result, the processing device 2 temporarily stores the above information in the registers for each level, and then performs interrupt processing.

On the other hand, due to the interrupt acceptance signal, the output of the level selection circuit 111 is transferred to the set decoder circuit 113.
decoded by old level register 115
The corresponding bit of is set to "1". This bit is reset via the reset decoder circuit 114 by a release signal from the processing device 2 when the interrupt processing is completed. However, as will be described later, when the interrupt processing is suspended due to the occurrence of a higher interrupt level, the interrupt level is stored in the old level register 11.
5, and the interrupt will be processed after the high-level interrupt is completed.

Next, the operation of this embodiment will be explained. now,
For example, assume that an interrupt of priority level 4 occurs from the input/output channel device 7 in FIG. 1, and an interrupt of priority level 3 occurs from the input/output channel device 6. The interrupt level signal LB and interrupt address information AB from the input/output channel device 7 are input to port B of the system control circuit 1, and the interrupt level signal LB is sent to the current processing level register by the level comparator 103 in FIG. 110 output. Now, since the output of the current processing level register 110 is level 7, the level comparator 103
generates an interrupt enable signal, which is input to port B of port designation circuit 109. Similarly, level comparator 104 also generates an interrupt enable signal and inputs it to port C of port designation circuit 109. but,
The port designation circuit 109 selects the input of port B with priority and outputs port number 2 as the port designation signal 501. As a result, the level signal selection circuit 111 and the interrupt address information selection circuit 112
selectively output the interrupt level signal LB (level 4) and interrupt address information AB, respectively. At the same time, a logical sum signal of the interrupt enable signals is output as an interrupt signal 502 to the processing device 2.
When the interrupt acceptance signal from the processing device 2 is given to the current processing level register 110, the output 503 of the level signal selection circuit 111 is set to the current processing level register 110, and the output (level 4) of the current processing level register 110 and the interrupt are set. The output of the address information selection circuit 112 (interrupt address information AB) is sent to the processing device 2.
attempts to set the interrupt address information AB in the level 4 register and start interrupt processing.

On the other hand, in response to the interrupt acceptance signal, the set decoder circuit 113 selects the level signal selection circuit 111.
The bit corresponding to level 4 of the old level register 115 is set to "1" by decoding the output 503 (level 4) of the old level register 115. The old register encode circuit 116 encodes the old level register 115.
The interrupt level signal corresponding to the highest level (currently level 4) is output. This signal is compared in the old level comparator 101 with the output of the current processing level register 110 (level 4).
Since both inputs of the old level comparator 101 are at the same level, the output of the level comparator 101 is “0”.
It is. Further, the output (level 4) of the current processing level register 110 is input to the level comparator 103, and the output of the level comparator 103 also becomes "0". The level comparator 104 compares the output of the current processing level register 110 (level 4) with the interrupt level signal LC (level 3), thereby
“1” is output. Therefore, the port designation circuit 109 now preferentially selects the output of the level comparator 104. Then, port number 3 corresponding to port C is output as a port designation signal 501, and an interrupt signal 502 is generated again based on the OR signal of the interrupt enable signal. Processing device 2
Level 3 is set in the current processing level register 110 by the interrupt acceptance signal from the processing device 2.
The processing device 2 receives the interrupt address information output from the interrupt address information selection circuit 112.
Interrupt processing is started by AC. Therefore, the interrupt processing of interrupt level 4 that occurred earlier is temporarily suspended and postponed.

When the interrupt processing at interrupt level 3 is completed, the current processing level register 110 is reset to level 7 by a release signal from the processing device 2. On the other hand, the bit corresponding to level 3 of the old level register 115 is also reset to "0" via the reset decoder circuit 114. Therefore, in the old level register 115, only the bit corresponding to level 4 is now "1". The output of the old register encode circuit 116 is an interrupt level signal indicating level 4. For this reason, the old level comparator 10
1 generates an interrupt enable signal by comparing level 7 and level 4 and inputs it to port O of port designation circuit 109. The level comparator 103 also inputs the interrupt enable signal to port B, but the port designation circuit 109 selects port O and outputs port number 0 as the port designation signal 501, and at the same time outputs the OR signal of the interrupt enable signal. Interrupt signal 5 by
02 to the processing device 2. The level signal selection circuit 111 also receives an interrupt level signal output from the old register encoder circuit 116, and the interrupt level signal is used as the port designation signal 50.
1 and the current processing level register 1
10 to the processing device 2. Further, a specific code AO indicating that the interrupt is for a pending interrupt request is also input to the interrupt address information selection circuit 112, and the code AO is selected and output by the signal port designation signal 501. . The processing device 2 learns from the interrupt level signal and the specific code AO that this interrupt request is for previously stored address information, and resumes the pending interrupt processing. Of course, if a high-level interrupt occurs during the interrupt processing, the processing is suspended again as described above, and the high-level interrupt processing is processed with priority.

Depending on the configuration of the processing device 2, the old level register 115, old register encode circuit 116, old level comparison circuit 101, etc. are unequal. Therefore, these are not essential components of the present invention. However, by providing these, the operation of the processing device can be simplified as described above.

Effects of the Invention As described above, in the present invention, after comparing the process level currently being processed and the interrupt level signal, select the ports from which an interrupt request of a higher level than the current processing level is generated. Since any one port is selected and the data processing device is configured to be interrupted by the interrupt level signal and interrupt address information corresponding to the selected port, the amount of hardware of the interrupt control device can be reduced and interrupt control can be performed at low cost. The effect is that it can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a data processing device to which the present invention is applied, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. In the figure, 1: system control device, 2: processing device, 3-8: input/output channel device, 9: main storage device, 101: old level comparator, 102-
108: Level comparator, 109: Port designation circuit, 110: Current processing level register, 111:
Level signal selection circuit, 112: Interrupt address information selection circuit, 113: Set decoder circuit, 1
14: Reset decoder circuit, 115: Old register, 116: Old register encode circuit.

Claims (1)

[Claims] 1. In an interrupt control device that controls interrupt requests to a data processing control device that inputs interrupt level signals and interrupt address signals for a plurality of interrupt requests and processes interrupts in order from the highest priority, a current processing level register that holds the current processing level; and an interrupt level signal input from a plurality of ports is compared with the output of the current processing level register to determine whether the interrupt level signal has a higher priority than the current processing level. A plurality of level comparators that output interrupt enable signals, and a level comparator that inputs the outputs of the plurality of level comparators and outputs the interrupt enable signal, select any one and connect the corresponding port. a port designation circuit that outputs a number; a level signal selection circuit that selects and outputs an interrupt level signal input to a corresponding port according to the output of the port designation circuit; an interrupt address information selection circuit for selectively outputting the input interrupt address information; means for generating an interrupt signal when detecting that there is at least one interrupt enable signal; An interrupt control device comprising control means for selecting any one of the generated ports and providing the data processing device with an interrupt level signal and interrupt address information input to the selected port. 2. The interrupt control device according to claim 1, which includes an old level register that holds process level signals currently being processed and pending interrupt level signals, and outputs the highest level signal held by the old level register. an old register encoding circuit; and an old level comparator that compares the output of the old register encoding circuit with the output of the current processing level register and inputs an interrupt enable signal to a specific port of the port designation circuit. The port selection circuit outputs the specific port number when the old level comparator outputs a level valid signal, and the level signal selection circuit outputs the output of the old register encoding circuit. The interrupt address information selection circuit includes means for selecting and outputting a specific code indicating that the interrupt request is an interrupt request for a pending interrupt request.