JPH03198432A - Encoding/decoding device - Google Patents

Abstract

PURPOSE:To prevent the pattern of a synchronizing signal from appearing on the boundary between a data area and a parity area to prevent detection of the presence of error in data by inserting at least one dummy bit to the last of the data area. CONSTITUTION:A switch 3 is set to the synchronizing signal side to apply the synchronizing signal to a modulating circuit 5, and switches 3 and 2 are set to the input data side to give input data to a modulating circuit 5. The switch 2 is set to the dummy bit side to apply dummy bits, for example, '101' to the modulating circuit 5. Finally, the switch 3 is set to the parity side to apply the parity to the modulating circuit 5. Since at least one dummy bit is inserted to the last of the data area in this manner, the pattern of the synchronizing signal is prevented from appearing between the data area and the parity area, and an error detecting circuit is normally operated though the synchronizing signal pattern appears in the parity area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an encoder/decoder for using a signal having a format composed of synchronization signal data and parity.

[Conventional technology] Conventionally, data transfer devices such as communication equipment and magnetic recorders have
A code/decoder is used. The signal format used in this encoder/decoder generally consists of a synchronizing signal 5YNC, data D1 and a parity P, as shown in Figure 4, and this parity P has a CRCC (cyclic code) added. It may be. FIG. 5 is a block diagram of a typical decoder that demodulates signals in such a format.

Referring to the same figure, a demodulation circuit 10 reproduces data input from an encoder, a synchronization detection circuit 11 detects a synchronization pattern from the reproduced data, and an error detection circuit 11 detects a synchronization pattern.
2 and timing generation circuit 13. The error detection circuit 12 synchronizes with the reproduced data at the timing of the detected synchronization signal, and determines the parity of whether the reproduced data is correct.

In the case of such a format signal, the synchronization signal pattern uses a pattern that does not appear in the data. However, depending on the code/decoding method, a synchronization signal pattern may appear in the code/decoded data string. This will be explained using the format of the 5-DAT subcode shown in FIG. 6 as an example. At this time, the n-th modulation system is a digital FM modulation system, and the synchronization signal pattern is "0011111111111101" (NR2
(representation), and the parity is the cyclic code of the CRCC.

Dummy bits are placed in the data format so that this synchronization signal pattern does not appear in the data. The dummy bits limit the data to be used to BCD codes and separate the length of the data in order to prevent the same pattern as the 16-bit synchronization signal pattern from appearing in the data. In this way, by limiting the data to be used, it is possible to prevent synchronization signal patterns from appearing in the data area of the format.

[Issue to be Solved by the Invention]However, even if the synchronization signal pattern is prevented from appearing in the data area as described above, the synchronization signal pattern will not appear in the data area and the parity area as shown in FIG. 7A. or a pattern of synchronization signals may appear in the parity area as shown in FIG. 7B. In this case, the synchronization signal detection circuit 11 detects the erroneously appearing synchronization pattern as a synchronization signal, and the error detection circuit 12 is unable to synchronize with the original data and determines that the data string is "erroneous."

The present invention has been made in view of the above problems, and is designed to prevent a synchronization signal pattern from appearing at the boundary between a data area and a parity area, and to operate an error detection circuit normally even if a synchronization signal pattern appears in a parity area. The purpose is to provide an operating code/decoder.

[Means for Solving the Problem] To achieve the above object, the encoder/decoder of the present invention has the following features:
dummy bit insertion including an encoder part and an encoder part, the encoder part including a boundary between a data area and a parity area, and inserting at least one dummy bit at the end of the data area so that a synchronization pattern does not appear; the decoder portion comprises demodulating means for regenerating the data input;
A synchronization signal detection means for detecting a synchronization signal from data reproduced by the demodulation means, a data delay means for delaying the reproduced data by a parity bit length, and a detection signal delay means for delaying a synchronization signal detection signal by a parity bit length. means, gate means for controlling the signal obtained by the detection signal delay means with an undelayed synchronization detection signal, and error detection for detecting errors in data delayed by the parity bit length using the output from the gate means. means.

[Operation of the Invention] According to the encoder/decoder of the present invention having the above configuration, data is It is possible to prevent a synchronization signal pattern from appearing between the area and the parity area. The synchronization signal pattern appearing in the parity area is then processed in the encoder section. That is, the synchronization signal detection means detects a synchronization signal pattern from the data reproduced by the demodulation means, and the detection signal delay means delays this by the number of parity bits. Next, the gate means interrupts the gate with the original synchronization signal (without delay) placed next to the parity area, and the synchronization detection signal (
(delayed by the parity bit length). Further, the synchronization pattern appearing in the synchronization signal area is delayed by the parity bit length by the detection signal delay means and then provided to the error detection means. Therefore, even if a synchronization signal pattern appears in the parity area, the error detection means can operate correctly.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The encoder consists of dummy bit generation circuit 1, switch 2, and switch 3.
, a parity generation circuit 4, a modulation circuit 5, and a recording head H1.

FIG. 2 is a diagram illustrating dummy bits inserted into the data format. In the figure, A assumes that the dummy bit is 1 bit, B assumes that the dummy bit is 2 bits,
C is an example assuming that the dummy bits are 3 bits. The synchronization signal pattern used here is “0011111
111111101''. In this case, the manner in which the synchronization signal pattern appears including the boundary between the data area and the parity area is as follows. Namely, as shown in Figure A, (1) 1 dummy bit “0”
When "Q:Q: 11111111111101"
(,0: is a dummy bit) pattern appears, and (2) when the dummy bit is “1”, “00:1:11
111111111101'' (=1: dummy bit) pattern appears.As described above, a synchronization signal pattern appears including the boundary between the data area and the boundary area.

Similarly, in the case of dummy bits or 2 bits as shown in Figure B, the synchronization signal pattern appears including the boundary between the data area and the parity area in all dummy bit patterns. Further, in the case of dummy bits or 3 bits as shown in Fig. C, when the dummy bit pattern is a pattern other than "101", the synchronization signal pattern appears including the boundary between the data area and the parity area. Therefore, assuming that the synchronization signal pattern is "0011111111111101",
In order to prevent the synchronization signal pattern from appearing including the boundary between the data area and the parity area, the dummy bits may be set to at least 3 bits and the pattern may be set to "101".

The dummy bits are set to 101" when the synchronization signal pattern is the above-mentioned pattern, and it goes without saying that the number of dummy bits and the dummy bit pattern will change depending on the No. 71 form of the synchronization pattern. In other words, in order to identify the boundary between the data area and the parity area, if the code string of the synchronization pattern is all “0”, it is sufficient to set the dummy bit to one “1” bit; In that case, you can set it to "0".

To insert the above dummy bit, do the following:

That is, (1) the switch 3 is set to the synchronization signal side and the synchronization signal is applied to the modulation circuit 5;

(2) Next, switch 3 and switch 2 are set to the input data side, and input data is provided to the modulation circuit 5. (3) Next, set the switch 2 to the dummy bit side and add the above-mentioned dummy bit “101#” to the modulation circuit 5.

(4) Finally, set the switch 3 to the parity side and apply it to the tg circuit 5. The data modulated by the modulation circuit 5 is sequentially sent to the RadEdge H1 for recording and then transferred to the tape T.
recorded in

By doing the above, a synchronization signal pattern including the boundary between the data area and the parity area does not appear. However, if this continues, there is a possibility that a synchronization signal pattern will appear in the parity area. In other words, if the parity area is set to the same 16 bits as the sync signal area as explained in the invention or problem to be solved (see Figure 7B), the 16 bits of the parity area will become the same sync signal pattern as the sync signal pattern. This is the case.

Next, the decoder will be explained. In the block diagram of FIG. 1, the demodulation circuit 10, synchronization signal detection circuit 11, error detection circuit 12, and timing generation circuit 13 are the same as those described in the conventional example. data delay circuit 14, synchronization signal detection signal delay circuit 15 (hereinafter abbreviated as detection signal delay circuit),
The gate circuit 16 is a predetermined delay circuit inserted between the synchronization signal detection circuit 11 and the error detection circuit 12. In this gate circuit 16, a human power gate 161 is connected to the synchronization signal detection circuit 11, and the other human power gate 162 is connected to the detection signal delay circuit 15. In other words, if the synchronization signal is “H”
゛When the level is reached, open the gate.

The following will explain the timing chart of the decoder shown in FIG. In the figure, a is the synchronization detection signal detected by the synchronization detection circuit]1, b is the synchronization detection signal delayed by the detection signal delay circuit 15, and C is the output signal of the gate circuit 16. Also, Xl is the point when the synchronization pattern appears in the parity area, Xl is the point 16 bits later (parity bit length) (at this point, the original synchronization signal appears in the synchronization signal area), and X3 is the point when the synchronization pattern appears in the parity area. Indicates a time point further delayed by a parity bit length. Further, Y is a timing chart when no synchronization pattern appears in the parity area.

At the time point Xl, a synchronization signal pattern appears in the parity area. The synchronization pattern appearing in this parity area is detected by the synchronization detection circuit 11, and a detection signal is given to the manual gate 161 of the gate circuit 16 and the detection signal delay circuit 15. Upon receiving this detection signal, the gate circuit 16 enters a cut-off state. Therefore, the output of the gate circuit 16 becomes "L". As a result, no synchronization signal is detected. Then, from Xl to Xl, the gate of the gate circuit [6] is in an open state, or the synchronizing signal pattern does not appear during this period, so the output of the detection signal delay circuit [5] is "L". In other words, the synchronization signal is not detected.

Next, at the time point Xl, the original synchronization signal appears in the synchronization signal area, this is detected by the synchronization detection circuit 11, and the synchronization detection signal is transmitted to the detection signal delay circuit 15 and the gate circuit 16.
is applied to the input gate 161 of. When this synchronization detection signal is input, the gate of the gate circuit 16 is cut off.

Therefore, the output of the gate circuit 16 becomes "L" and the synchronization signal is not detected. Since no synchronizing signal is detected by the synchronizing signal detection circuit 11 between X1 and X3, the output of the gate circuit 16 becomes "L", similar to the processing between X1 and X1.

Next, since no synchronization signal is detected by the synchronization detection circuit 11 at time X3, the gate remains open.

Then, at the time point X2, the original synchronization signal detected by the synchronization detection circuit 11 and further delayed by the parity bit length by the detection signal delay circuit 5 is input to the input gate 162 of the gate circuit 16. Therefore, the output of the gate circuit 16 becomes "H" and a synchronization signal is detected.

As described above, even if the synchronization detection circuit 11 detects a bang of the synchronization signal in the parity area, the detection signal delay circuit 15 and the gate circuit 16 delay the synchronization pattern signal appearing in the synchronization signal area by the parity bit length. It is possible to detect the original synchronization signal.

This synchronization detection signal delayed by the parity bit length is given to the error detection circuit 12, and the error detection circuit 12 detects the data delayed by the parity bit length by the data delay circuit 14 at the timing of the original synchronization signal delayed by the parity bit length. Check.

This makes it possible to prevent errors in data recognition due to the appearance of a synchronization signal pattern in the parity area.

Next, a case where no synchronization signal pattern appears in the parity area will be described. Since no synchronization signal pattern appears in the parity area at the time point Yl, the synchronization signal detection circuit 11 does not detect the synchronization signal. At the next time point Y2, the synchronization signal pattern in the synchronization signal area is detected by the synchronization signal detection circuit 11. However, due to the action of the detection signal delay circuit 15, no synchronizing signal is detected in the output of the gate circuit 16. Subsequently, at time Y3, the synchronizing signal detection signal is detected by the action of the gate circuit 16 and the detection signal delay circuit 15.

Although the above embodiment has been explained using a digital magnetic recording device as an example, it is also possible to apply it to a data transfer device that combines an encoder and a decoder using an optical transmission line or a signal line, etc. Various design changes can be made without changing the gist of the invention.

[Effects of the Invention] According to the present invention, by inserting at least one dummy bit at the end of the data area by the dummy bit insertion means, it is possible to prevent a synchronization signal pattern from appearing at the boundary between the data area and the parity area. It can be prevented. Therefore, it is possible to prevent the error detection means from detecting that there is an "error" in the data. Furthermore, even if an incorrect synchronization pattern appears in the parity area, a signal obtained by delaying the original synchronization signal by the parity bit length by the detection signal delay means can be detected as the synchronization signal.
It is possible to prevent the error detection means from detecting that there is an "error" in the data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a dummy bit insertion method in the embodiment of the present invention, FIG. 3 is a timing chart of the block diagram of FIG. 1, and FIG. 4 is a conventional and Code modulation format in the present invention, fifth
The figure is a block diagram showing the conventional example, Figure 6 is the code inter-interval format used in the conventional example and the embodiment of the present invention, and Figure 7 (
This is the synchronization signal pattern generated at the wrong position as shown in the conventional example. In the figure, 11 is a synchronization signal detection circuit, 12 is an error detection circuit, 13 is a timing generation circuit, 14 is a data delay circuit, and 15 is a synchronization signal detection signal delay port 16 is a gate circuit.

Claims (1)

[Claims] A code for a signal having a format consisting of a synchronization signal, data, and parity with the same bit length as the synchronization signal, and in which the synchronization signal pattern is represented by a data string encoded and decoded. - In the decoder, the encoder portion includes a dummy bit insertion means for inserting at least one dummy bit at the end of the data area so that a synchronization pattern does not appear including the boundary between the data area and the parity area; includes demodulation means for reproducing data input, synchronization signal detection means for detecting a synchronization signal from data reproduced by the demodulation means, data delay means for delaying the reproduced data by a parity bit length, and synchronization signal detection means. A detection signal delay means for delaying a signal by the parity bit length, a gate means for controlling the signal obtained by the detection signal delay means with an undelayed synchronization detection signal, and a parity bit by the output from the gate means. An encoder/decoder comprising: error detection means for detecting errors in data delayed by a long time.