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JPH03198414A - Waveform shaping circuit for interface circuit - Google Patents

Waveform shaping circuit for interface circuit

Info

Publication number
JPH03198414A
JPH03198414A JP1337664A JP33766489A JPH03198414A JP H03198414 A JPH03198414 A JP H03198414A JP 1337664 A JP1337664 A JP 1337664A JP 33766489 A JP33766489 A JP 33766489A JP H03198414 A JPH03198414 A JP H03198414A
Authority
JP
Japan
Prior art keywords
pair
terminals
circuit
waveform
diodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1337664A
Other languages
Japanese (ja)
Other versions
JP2735661B2 (en
Inventor
Toshio Matsui
松井 利夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1337664A priority Critical patent/JP2735661B2/en
Publication of JPH03198414A publication Critical patent/JPH03198414A/en
Application granted granted Critical
Publication of JP2735661B2 publication Critical patent/JP2735661B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To reduce the undershoot of a transmission pulse waveform to hold the transmission pulse waveform within a prescribed pulse mask by using a pair of specific diodes to shape the waveform of the pulse outputted to a transmission line. CONSTITUTION:Not only resistances R1 and R2 but also respective cathodes of diodes D1 and D2 constituting a waveform shaping circuit 20 are connected to terminals X1 and X2 of a driver 10, and anodes connected in common of diodes D1 and D2 are connected to the connection point of resistances R3 and R4. The pair of diodes D1 and D2 are connected to one pair of terminals X1 and X2 respectively, and they are pulled up to potentials near the high level of this pair of terminals. Thus, the undershoot of the transmission pulse waveform is reduced to hold the transmission pulse waveform within the preliminarily prescribed pulse mask.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はインタフェース回路の波形整形回路に関し、l
5DN (サービス総合ディジタル網)基本インタフェ
ースの出力パルス波形を整形するインタフェースの回路
の波形整形回路に圓する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a waveform shaping circuit for an interface circuit.
5DN (Integrated Service Digital Network) The waveform shaping circuit of the interface circuit shapes the output pulse waveform of the basic interface.

l5DNは近年急速に普及しており対応装置も次第に増
加している。しかしl5DNでは同一インタフェース上
に各種装置を接続するために出力パルス波形等について
厳しいインタフェース規約が規定されている。
15DN has rapidly become popular in recent years, and the number of compatible devices is gradually increasing. However, in 15DN, strict interface regulations are prescribed regarding output pulse waveforms, etc. in order to connect various devices on the same interface.

〔従来の技術〕[Conventional technology]

第3図は従来のインタフェース回路の一例の回路構成図
を示す。同図中、ドライバ10の端子X1.X2夫々は
電流制限用の抵抗R+ 、R2(各150)夫々を介し
てトランスTの1次側巻線の両端に接続されている。ト
ランスTの2次側巻線の両端は10mのケーブル11が
接続され、このケーブル11の終端は50Ωの抵抗R[
で短絡されている。
FIG. 3 shows a circuit configuration diagram of an example of a conventional interface circuit. In the figure, terminals X1. of the driver 10. Each of X2 is connected to both ends of the primary winding of the transformer T via current limiting resistors R+ and R2 (150 each). A 10m cable 11 is connected to both ends of the secondary winding of the transformer T, and the end of this cable 11 is connected to a 50Ω resistor R[
is shorted.

この回路構成で出力パルス波形が第4図の斜線で示すパ
ルスマスク内にあるようインタフェース規約が定められ
ている。
In this circuit configuration, the interface rules are determined so that the output pulse waveform is within the pulse mask shown by diagonal lines in FIG.

〔課題を解決するための手段〕[Means to solve the problem]

従来はケーブル11として低インピーダンスの特殊なケ
ーブルを用いれば出力パルス波形をパルスマスク内に収
めることが可能であるが、特殊なケーブルは高価である
。インピーダンスが100Ωを越える通常のケーブルを
用いると、抵抗R4両端における伝送パルス波形は第4
図に実線で示す如く、端子×1がHレベルからハイイン
ピーダンスに切換わり、端子×2がLレベルからハイイ
ンピーダンスに切換ねる際の端子X2の切換えタイミン
グの遅れにより発生するアンダーシュー1〜が大きくな
りパルスマスクの外に出てしまうという問題があった。
Conventionally, it has been possible to fit the output pulse waveform within the pulse mask by using a special cable with low impedance as the cable 11, but the special cable is expensive. If a normal cable with an impedance exceeding 100Ω is used, the transmission pulse waveform at both ends of resistor R4 will be
As shown by the solid line in the figure, the undershoe 1~ that occurs due to the delay in the switching timing of terminal X2 when terminal x1 switches from H level to high impedance and terminal x2 switches from L level to high impedance is large. However, there was a problem in that the pulses would go outside the pulse mask.

本発明は上記の点に鑑みなされたもので、伝送パルス波
形のアンダーシュートを低減し伝送パルス波形を規定の
パルスマスク内に収めるインタフェース回路の波形整形
回路を提供することを目的とする。
The present invention has been made in view of the above points, and it is an object of the present invention to provide a waveform shaping circuit for an interface circuit that reduces undershoot of a transmitted pulse waveform and fits the transmitted pulse waveform within a prescribed pulse mask.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のインタフェース回路の波形整形回路は、トライ
ステート出力を行なう一対の端子よりトランスを介して
伝送路にパルスを出力する差動ドライバ形のインタフェ
ース回路に設けられ、アノードに一対の端子の出力する
ハイレベル近傍の電位とされ、カソードを一対の端子夫
々に接続された一対のダイオードを有し、 伝送路に出力するパルスの波形整形を行なう。
The waveform shaping circuit of the interface circuit of the present invention is provided in a differential driver type interface circuit that outputs pulses from a pair of terminals that perform tri-state output to a transmission line via a transformer, and a waveform shaping circuit that outputs pulses from a pair of terminals to an anode. It has a pair of diodes whose potential is close to high level and whose cathodes are connected to a pair of terminals, respectively, and shapes the waveform of the pulses output to the transmission line.

〔作用〕[Effect]

本発明においては、一対の端子夫々に一対のダイオード
を接続されてこの一対の端子のハイレベル近傍の電位に
プルアップされるため、一対の端子がハイレベル、ロー
レベル夫々から共にハイインピーダンスに切換わるタイ
ミングのずれにより生じる伝送パルス波形のアンダーシ
ュートが低減される。
In the present invention, a pair of diodes are connected to each of the pair of terminals and pulled up to a potential near the high level of the pair of terminals, so that the pair of terminals are both disconnected from the high level and low level to high impedance. The undershoot of the transmission pulse waveform caused by the timing shift is reduced.

〔実施例〕〔Example〕

第1図は本発明回路の一実施例の回路構成図を示す。同
図中、第3図と同一部分には同一符号を付し、その説明
を省略する。
FIG. 1 shows a circuit diagram of an embodiment of the circuit of the present invention. In the figure, the same parts as in FIG. 3 are given the same reference numerals, and their explanations will be omitted.

第1図中、ドライバ10はトライステー1へ出力端子X
1をHレベル(3v)出力、トライスデート出力端子X
2をLレベル(OV)出力として正極性パルス出力状態
とし、端子X1.X2共にハイインピーダンス状態とし
、更に端子×1を1−レベル出力、端子×2をHレベル
出力として負極性パルス出力状態とする差動出力を行な
う。ドライバ10の端FX1.X2に:は抵抗R+ 、
R2が接続されると共に、波形整形回路20を構成する
ダイオードD+ 、D2夫々のカソードが接続されてい
る。ダイオードD+ 、D2の共通接続されたアノード
は抵抗R3、R4の接続点に接続されている。
In Figure 1, the driver 10 is connected to the output terminal X to the tri-stay 1.
1 to H level (3v) output, trice date output terminal
2 is set to a positive polarity pulse output state by outputting L level (OV), and terminals X1. Differential output is performed in which both terminals X2 are in a high impedance state, and terminal x1 is output at a 1-level, and terminal x2 is output at an H level, resulting in a negative pulse output state. End FX1 of driver 10. To X2: is the resistance R+,
R2 is connected, and the cathodes of diodes D+ and D2 forming the waveform shaping circuit 20 are also connected. The commonly connected anodes of diodes D+ and D2 are connected to the connection point of resistors R3 and R4.

例えば1にΩの抵抗R3と例えば1.5にΩの抵抗R4
とは直列に電mVcc(5V)、GND (OV)の間
に接続され、抵抗R3、R4の接続点の電位は例えば3
■と、ドライバ10が端?X1又は×2より出力するH
レベルの電位と略等しくされている。
For example, a resistor R3 of 1Ω and a resistor R4 of 1.5Ω
is connected in series between the voltage mVcc (5V) and GND (OV), and the potential at the connection point of resistors R3 and R4 is, for example, 3
■And driver 10 is the end? H output from X1 or ×2
The potential is approximately equal to the level potential.

ここで、端子X1がHレベル(30)、端子X2がLレ
ベル(OV)のときダイオードD+。
Here, when the terminal X1 is at H level (30) and the terminal X2 is at L level (OV), the diode D+.

D2のアノードは3vであるため、ダイオードD1が′
a断、ダイオードD2は導通する。しかし抵抗R3の抵
抗値は1にΩと抵抗R+ 、R2に対して大であるため
ダイオードD2を流れる電流は掻く小さい。
Since the anode of D2 is 3v, the diode D1 is
A is disconnected, and diode D2 is conductive. However, since the resistance value of the resistor R3 is 1Ω, which is larger than the resistors R+ and R2, the current flowing through the diode D2 is quite small.

この後、端子X1.X2が共にハイインピーダンスと切
換わると端子X1.X2は波形整形回路20によって共
に3■にクランプされる。この場合、ケーブル11にイ
ンピーダンスが100Ωを越える通常のケーブルを用い
、端FX2の切換えタイミングが遅れても端子x2がハ
イインピーダンスとなるまでの間ダイオードD2が導通
しているため、抵抗RL両端における伝送パルス波形は
第2図に実線で示す如くパルスのアンダーシュートが従
来より低減され、伝送パルスは第2図に斜線で示すパル
スマスク内におさまる。これによってケーブル11とし
て^価な低インピーダンスの特殊なケーブルを使用しな
くて済む。
After this, terminal X1. When both terminals X2 switch to high impedance, terminals X1. Both X2 are clamped to 3.times. by the waveform shaping circuit 20. In this case, a normal cable with an impedance exceeding 100Ω is used as the cable 11, and even if the switching timing of the terminal FX2 is delayed, the diode D2 is conductive until the terminal x2 becomes high impedance, so the transmission at both ends of the resistor RL is As for the pulse waveform, as shown by the solid line in FIG. 2, the undershoot of the pulse is reduced compared to the conventional method, and the transmitted pulse falls within the pulse mask shown by the diagonal line in FIG. This eliminates the need to use an expensive special cable with low impedance as the cable 11.

〔発明の効果〕 本発明のインタフェース回路の波形整形回路によれば、
伝送パルス波形のアンダーシュートを低減し、伝送パル
ス波形を予め規定されたパルスマスク内に収めることが
でき、実用上きわめて有用である
[Effects of the Invention] According to the waveform shaping circuit of the interface circuit of the present invention,
This is extremely useful in practice as it reduces the undershoot of the transmitted pulse waveform and allows the transmitted pulse waveform to fall within a predefined pulse mask.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明回路の一実施例の回路構成図、第2図は
本発明回路の伝送パルス波形図、第3図は従来回路の一
例の回路構成図、第4図は従来回路の伝送パルス波形図
である。 図において、 10はドライバ、 11はケーブル、 20は波形整形回路、 D+ 、D2はダイオード、 R1−R4は抵抗 を示す。
Fig. 1 is a circuit diagram of an embodiment of the circuit of the present invention, Fig. 2 is a transmission pulse waveform diagram of the circuit of the present invention, Fig. 3 is a circuit diagram of an example of a conventional circuit, and Fig. 4 is a transmission diagram of the conventional circuit. It is a pulse waveform diagram. In the figure, 10 is a driver, 11 is a cable, 20 is a waveform shaping circuit, D+ and D2 are diodes, and R1-R4 are resistors.

Claims (1)

【特許請求の範囲】 トライステート出力を行なう一対の端子(X1、X2)
よりトランスを介して伝送路にパルスを出力する差動ド
ライバ形のインタフェース回路に設けられ、 アノードに該一対の端子(X1、X2)の出力するハイ
レベル近傍の電位とされ、カソードを該一対の端子(X
1、X2)夫々に接続された一対のダイオード(D_1
、D_2)を有し、 該伝送路に出力するパルスの波形整形を行なうことを特
徴とするインタフェース回路の波形成形回路。
[Claims] A pair of terminals (X1, X2) that perform tri-state output
It is provided in a differential driver type interface circuit that outputs pulses to the transmission path via a transformer, and the anode is set to a potential close to the high level output from the pair of terminals (X1, X2), and the cathode is set to Terminal (X
1, X2) A pair of diodes (D_1
, D_2), and performs waveform shaping of pulses output to the transmission line.
JP1337664A 1989-12-26 1989-12-26 Waveform shaping circuit of interface circuit Expired - Lifetime JP2735661B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1337664A JP2735661B2 (en) 1989-12-26 1989-12-26 Waveform shaping circuit of interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1337664A JP2735661B2 (en) 1989-12-26 1989-12-26 Waveform shaping circuit of interface circuit

Publications (2)

Publication Number Publication Date
JPH03198414A true JPH03198414A (en) 1991-08-29
JP2735661B2 JP2735661B2 (en) 1998-04-02

Family

ID=18310790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1337664A Expired - Lifetime JP2735661B2 (en) 1989-12-26 1989-12-26 Waveform shaping circuit of interface circuit

Country Status (1)

Country Link
JP (1) JP2735661B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013175915A (en) * 2012-02-24 2013-09-05 Denso Corp Driver circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013175915A (en) * 2012-02-24 2013-09-05 Denso Corp Driver circuit

Also Published As

Publication number Publication date
JP2735661B2 (en) 1998-04-02

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