JPH03198381A - Manufacture of non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent a polycrystal film being brought into electrically floating state by a method wherein insulating films are formed only on the sidewall parts of element isolating grooves which are filled with polycrystal silicon film doped with an impurity of the same conductivity type as that of a substrate. CONSTITUTION:When etching grooves 9 are formed by laminating the first gate insulating film 3 of SiO2, a polycrystal silicon film 3 doped with an N type impurity, the second insulating film 4 of SiO2, etc., comprising high-temperature oxidized film 3, the second polycrystal silicon film 5 doped with the N type impurity, a silicon nitride film 5 using CVD process and a patterning mask 7 on a P type Si substrate 1 and then an interlayer insulating film 8 in excellent form retention is deposited in the grooves 9 to perform the anisotropical etching process, the film 8 is formed only on the sidewall parts of the grooves 9 to expose the substrate 1. Accordingly, when polycrystal silicon film 10 of the same conductivity type as that of the third substrate doped with P type impurity is filled in the grooves 9, the film 10 can be prevented from being brought into the electrically floating state while the element isolation region can be fixed to the substrate potential thereby enabling the interelement isolation of the title non-volatile semiconductor memory to be assured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and particularly to a method of manufacturing a nonvolatile semiconductor memory device having a two-layer gate electrode transistor.

[Conventional technology]

The most common structure among nonvolatile semiconductor memory devices is a structure in which a two-layer gate electrode transistor having a floating gate electrode is used as a memory transistor, and the representative one is an EPROM.

Digest of Technology Paper, Digest of Technology Paper,
1986 VLSI Symposium (Digest
o-f Technology Paper, 1986
VLSI SYMPO3IUM), page 87. In this method, an insulating film is buried in a groove formed by etching a predetermined region of a semiconductor substrate to form an element isolation region.

A conventional method which is a further improvement of this manufacturing method is shown in FIG. This manufacturing method will be explained below in Figures 3(a)-(
This will be explained with reference to g).

For example, a first gate insulating film 2 made of, for example, silicon oxide (hereinafter referred to as Si○2) is formed on a predetermined region of a semiconductor substrate 1 made of Si.Furthermore, a first polycrystalline silicon film 3, A second gate insulating film 2 made of, for example, 5i02 is formed.Furthermore, a first polycrystalline silicon film 3,
a second gate insulator M4 made of e.g. S i 02;
A second polycrystalline silicon film 5 and a silicon nitride film 6 are sequentially laminated. Thereafter, a patterning mask 7 made of, for example, resist is formed so that only the portion that will become the element isolation region is exposed (FIG. 1(a)).

Using this mask, the silicon nitride film 6, the second polycrystalline silicon film 5, the second gate insulating film 4, the first polycrystalline silicon film 3, and the first gate insulating film 2 are selectively etched in order, The surface of the substrate is exposed, and the substrate is further etched into grooves. As for these etching techniques, it is numerically preferable to use anisotropic etching such as R, 1, E, etc. in order to reduce the dimensional deviation. Thereafter, an interlayer insulating film 8 with good shape, such as a silicon oxide film, is deposited by low-pressure CVD to cover the wall surface of the trench (see FIG. 1(b)).
), then a third polycrystalline silicon film 10 is grown so as to fill the trench (FIG. 1(C)).

Thereafter, this third polycrystalline silicon film 10 is etched back, and the exposed eyebrow insulating film 8 with good shape is etched to expose the surface of the silicon nitride film 6. When the surface of the polycrystalline silicon film 10 is oxidized, the oxidation-resistant silicon nitride film 6 is not oxidized, and a silicon oxide film 11 is formed only in the element isolation region.

Next, only the silicon nitride M6 is etched to expose the surface of the second polycrystalline silicon film 5 (FIG. 3(e)).
Next, a fourth polycrystalline silicon film 12 is deposited to form a patterning mask 13 (FIG. 3(f)).

After this, using well-known techniques, patterning of each gate electrode, formation of source/drain regions 14 by introducing impurities, formation of glabellar insulating film 15, opening of contact holes 17, and formation of metal wiring 16 are performed. A nonvolatile semiconductor memory device as shown in FIG. 3(g) is obtained.

[Problem to be solved by the invention]

According to the conventional manufacturing method of nonvolatile semiconductor devices described above, the polycrystalline silicon film embedded in the groove of the element isolation region is not in direct contact with the substrate and is electrically floating. structure, even if a high voltage is applied between the source and drain during memory cell programming and holes are injected into the polycrystalline silicon film in the element isolation region, the polycrystalline silicon film in the element isolation region will be directly injected. Since it is not in contact with the substrate, the potential of the element isolation region increases and the threshold voltage of the parasitic MoS transistor decreases. This has the disadvantage that adjacent diffusion layers become electrically conductive.

[Means to solve the problem]

The present invention provides a first gate insulating film, a first polycrystalline silicon film, a second gate insulating film,
a step of sequentially stacking a second polycrystalline silicon film and a silicon nitride film, and forming the silicon nitride film, second polycrystalline silicon film, second gate insulation film, and first polycrystalline silicon film in a predetermined region; a step of selectively removing the first gate insulating film and etching the substrate in the predetermined region to form a trench for element isolation; and a third step of doping with impurities of one conductivity type so as to fill the trench. After growing a polycrystalline silicon film, the third polycrystalline silicon film is etched until the surface of the silicon nitride film is exposed, and the surface of the remaining third polycrystalline silicon film is oxidized to form a device. a step of forming an isolation structure; a step of etching away the silicon nitride film until the surface of the second polycrystalline silicon film is exposed; and a fourth step of making an ohmic connection with the second polycrystalline silicon film. a step of forming a polycrystalline silicon film;
the fourth polycrystalline silicon film in a predetermined region;
a step of sequentially selectively removing the polycrystalline silicon film, the second gate insulating film, the first polycrystalline silicon film, and the first gate insulating film to form a stacked gate structure. 1 is a method for manufacturing a semiconductor memory device.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(g) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention. Figures 1 (a) and (b) show conventional examples; Figures 3 (a) and (
Same as b).

Here, 1 is a semiconductor substrate made of, for example, P-type Si, 2 is a first gate insulating film made of 5i02 with a thickness of, for example, 20 nm, and 3 is a semiconductor substrate doped with, for example, N-type impurities.
0 nm first polycrystalline silicon film, 4 is a second gate insulating film such as 5i02 with a thickness of 20 nm formed by oxidizing the first polycrystalline silicon film 3 at a high temperature of, for example, at least 1150° C., and 5 is, for example, N. Type impurity doped thickness 2
00 nm second polycrystalline silicon film 6, for example CVD
A 150 nm thick silicon nitride film grown by
7 is a patterning mask such as a resist, 8 is a glabella insulating film with good shape such as S i 02 grown by low pressure CVD, and 9 is anisotropically etched with R, 1, and E to a depth of 0. .8 μm groove for element isolation. The manufacturing method up to FIG. 1(b) is the same as the conventional method. From FIG. 1(b) onward, the glabella insulating film 8 with good shape is etched back by anisotropic etching such as R, 1, E, etc., so that the groove bottom and the surface of the silicon nitride 1116 are exposed. . Thereafter, a third polycrystalline silicon film 10 doped with, for example, a P-type impurity is grown to a thickness of 1 μm (FIG. 1(C)). Next, the third polycrystalline silicon film 10
is etched back until the surface of the silicon nitride film 6 is exposed, and a third polycrystalline silicon film is buried in the groove (see Fig. 1).
d)). Next, selectively thick 5i0 is applied only on the element isolation region.
2 film 11 is formed to have a thickness of, for example, 600 nm (FIG. 1(e)).
. Thereafter, the silicon nitride film 6 is removed by etching, and the second
A fourth film capable of making ohmic contact with the polycrystalline silicon film 5 of
A polycrystalline silicon film 14 is grown to a thickness of, for example, 200 nm (FIG. 1(f)). In the following, the same well-known technique as in the conventional example is used to obtain what is shown in FIG. 1(g). According to the conventional example, it is not possible to obtain an element isolation structure in which the polycrystalline silicon film embedded in the trench groove for element isolation is not in direct contact with the substrate, whereas in this example, an impurity of the same conductivity type as the substrate is The trench for element isolation can be filled with a doped polycrystalline silicon film that is in direct contact with the substrate.

FIGS. 2A to 2C are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

After a process similar to that described with reference to FIGS. 1(a) to (e) of the first embodiment, the silicon oxide film 11 is etched back until the surface of the second polycrystalline silicon film is exposed. (FIG. 2(a)), and then a silicide layer 18 made of WSi or the like having a thickness of 150 nm, for example, is formed (FIG. 2(b)). The rest is manufactured in the same manner as in the first embodiment using well-known techniques to obtain what is shown in FIG. 2(C).

This embodiment has the advantage that the layer resistance of the control gate electrode can be lowered because a silicide layer having an electrical resistance lower than that of poly-Si is laminated.

〔Effect of the invention〕

As explained above, the present invention improves the conventional method by forming an insulating film only on the sidewalls of the trench for element isolation, and then filling the trench with a polycrystalline silicon film doped with impurities of the same conductivity type as the substrate. As a result, it is possible to avoid an element isolation structure that includes an electrically floating polycrystalline silicon film, so when programming a memory cell, a high voltage is applied between the source and drain layers, causing damage to the polycrystalline silicon film in the element isolation region. Even when holes are injected, the polycrystalline silicon film in the element isolation region is in direct contact with the substrate and has the same conductivity type as the substrate, so the injected holes can escape to the substrate. This has the effect of fixing the element isolation region to the potential of the substrate.

Further, as a result, the threshold voltage of the parasitic MOS transistor in the element isolation region does not change, and adjacent diffusion layers do not become conductive. Therefore, there is an effect that isolation between elements of a nonvolatile semiconductor memory device can be ensured.

... first polycrystalline silicon film, 4 ... second gate insulating film, 5 ... second polycrystalline silicon film, 6 ... silicon nitride film, 7 ... patterning mask, 8...
・Glabella insulating film with good shape, 9...Etching groove, 1
o...Third polycrystalline silicon film, 11...Silicon oxide film, 12...Fourth polycrystalline silicon film, 13...
- Patterning mask, 14... impurity diffusion layer, 1
5... Interlayer insulating film, 16... Metal wiring, 17...
Contact hole, 18...silicide layer.

Claims (1)

[Claims] A first gate insulating film, a first gate insulating film, and a first gate insulating film are formed on a semiconductor substrate of one conductivity type.
a step of sequentially stacking a polycrystalline silicon film, a second gate insulating film, a second polycrystalline silicon film, and a silicon nitride film; selectively removing the second gate insulating film, the first polycrystalline silicon film, and the first gate insulating film, and etching the substrate in the predetermined region to form a trench for element isolation; After growing a third polycrystalline silicon film doped with one conductivity type impurity so as to fill the
etching the third polycrystalline silicon film until the surface of the silicon nitride film is exposed; oxidizing the remaining surface portion of the third polycrystalline silicon film to form an element isolation structure; etching away the silicon nitride film until the surface of the polycrystalline silicon film is exposed;
forming a fourth polycrystalline silicon film having an ohmic connection with the second polycrystalline silicon film; a step of sequentially selectively removing a second gate insulating film, the first polycrystalline silicon film, and the first gate insulating film to form a stacked gate structure. A method for manufacturing a storage device.