JPH03196634A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03196634A JPH03196634A JP33961189A JP33961189A JPH03196634A JP H03196634 A JPH03196634 A JP H03196634A JP 33961189 A JP33961189 A JP 33961189A JP 33961189 A JP33961189 A JP 33961189A JP H03196634 A JPH03196634 A JP H03196634A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- bump
- tape
- tip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 230000006835 compression Effects 0.000 abstract 2
- 238000007906 compression Methods 0.000 abstract 2
- 238000002788 crimping Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にバンプとリ
ードとの接続方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of connecting bumps and leads.
従来、フィルムキャリア方式で用いられるＴＡＢテープ
のリードを接続するためのバンプを有する半導体装置と
しては、第４図（ａ）、（ｂ）に示すように、素子によ
って回路が形成されている半導体基板ｌと、この基板の
表面に形成された高さの等しい第１のバンプ９および第
２のバンプ１０から構成されていた。Conventionally, a semiconductor device having bumps for connecting leads of a TAB tape used in the film carrier method is a semiconductor substrate on which a circuit is formed by elements, as shown in FIGS. 4(a) and (b). 1, and first bumps 9 and second bumps 10 of equal height formed on the surface of this substrate.
リードキャリアであるＴＡＢテープは、テープ１２と長
さの異なるリード１１Ａとリード１１Ｂから成っており
、半導体装置上に第１のバンプ９と第２のバンプ１０に
ＴＡＢテープのリード１１Ａ、ＩＩＢを接続するときは
、リード１１Ａ。The TAB tape, which is a lead carrier, consists of a tape 12 and leads 11A and 11B of different lengths, and the leads 11A and IIB of the TAB tape are connected to the first bump 9 and the second bump 10 on the semiconductor device. When doing so, use lead 11A.
１１Ｂの先端が第１のバンプ９および第２のバンプ１０
の上にくるように位置合わせを行ない、リードＩＩＡ、
ＩＩＢの先端に対し、上方から治具により熱と圧力をか
けて圧着させていた。The tip of 11B is the first bump 9 and the second bump 10
Align it so that it is above the lead IIA,
Heat and pressure were applied to the tip of IIB from above using a jig to make it crimped.
上述した従来の半導体装置の製造方法では、半導体装置
の高密度化に伴なって間隔が狭くなったバンプ９，１０
とリード１１Ａ、１１Ｂとを接続する場合、高い位置合
せ精度が必要である。この位置合わせがずれたときは第
５図に示すように、第２のバンプ１０に接続するリード
１１Ｂと、それに隣接した第１のバンプ９とが接触し、
電気的な短絡を起こすという欠点がある。In the conventional semiconductor device manufacturing method described above, the distance between the bumps 9 and 10 has become narrower as the density of semiconductor devices has increased.
When connecting the leads 11A and 11B, high alignment accuracy is required. When this alignment is misaligned, as shown in FIG. 5, the lead 11B connected to the second bump 10 and the first bump 9 adjacent thereto come into contact with each other, as shown in FIG.
It has the disadvantage of causing an electrical short circuit.
本発明の半導体装置の製造方法は、半導体基板上に形成
された高さの低い第１のバンプに第１のリードを接続す
る工程と、次で高さの高い第２のバンプに第２のリード
を接続する工程とを含んで構成される。The method for manufacturing a semiconductor device of the present invention includes the steps of connecting a first lead to a first bump with a low height formed on a semiconductor substrate, and then connecting a second lead to a second bump with a high height. The method includes a step of connecting the leads.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の第１の実施例を説明す
るための半導体チップの側面図である。FIGS. 1(a) and 1(b) are side views of a semiconductor chip for explaining a first embodiment of the present invention.
素子が形成された半導体基板１上にはバンプが千鳥状に
配置されており、半導体基板１上の外側の第１バンプ２
に比べ内側の第２バンブ３の方が高く形成されている。Bumps are arranged in a staggered manner on a semiconductor substrate 1 on which elements are formed, and first bumps 2 on the outside of the semiconductor substrate 1
The inner second bump 3 is formed higher than the inner second bump 3.
そしてこの高低差は、第１のリード４の厚さよりも大き
くなっている。This height difference is larger than the thickness of the first lead 4.
まず第１図（ａ）に示すように、半導体基板１上の第１
のバンプ２の上に第１のテープ６上に形成された第１の
リード４の先端がくるように位置合せを行ない、次で第
１のリード４の先端に上方から治具により熱と圧力をか
けて圧着させる。第１のリード４は第１のテープ６の表
面の片側に形成されており、圧着の際には第１のテープ
６の第１のリード４が形成されている側の面が上方を向
くようにする。First, as shown in FIG. 1(a), a first
Align the tip of the first lead 4 formed on the first tape 6 so that it is on top of the bump 2, and then apply heat and pressure to the tip of the first lead 4 from above using a jig. and crimp. The first lead 4 is formed on one side of the surface of the first tape 6, so that the surface of the first tape 6 on which the first lead 4 is formed faces upward during crimping. Make it.
次に第１図（ｂ）に示すように、第２のバング３の上に
第２のリード５の先端がくるように位置合せを行ない、
第２のり−ド５の先端に上方がら治具により熱と圧力を
かけて圧着させる。第２のり−ド５は第２のテープ７の
表面の片側に形成されており、圧着の際には第２のテー
プ７の第２のリード５が形成されている側の面が上方を
向くようにする。第２のり−ド５を接続した後に、第１
のテープ６と第２のテープ７を接着させて固定する。Next, as shown in FIG. 1(b), align the tip of the second lead 5 so that it is on top of the second bang 3,
Heat and pressure are applied to the tip of the second glue board 5 from above using a jig to make it crimped. The second lead 5 is formed on one side of the surface of the second tape 7, and during crimping, the surface of the second tape 7 on which the second lead 5 is formed faces upward. Do it like this. After connecting the second board 5,
The tape 6 and the second tape 7 are adhered and fixed.
このように第１の実施例によれば、第１のり−ド４とそ
れと隣接した第２のリード５との間は、第１のバンプ２
と第２のバンプ３の高低差以上の距離が必ず保たれるこ
とになる。According to the first embodiment, the first bump 2 is connected between the first lead 4 and the second lead 5 adjacent thereto.
A distance equal to or greater than the height difference between the second bump 3 and the second bump 3 is always maintained.
本実施例で位置合せのずれが生じた場合の様子を第２図
に示す。FIG. 2 shows what happens when misalignment occurs in this embodiment.
第２のバンプ３に接続された第２のリード５は、大きな
位置合わせのずれを起こしているが、第１のバンプ２の
高さが低いため第２のリード５は、隣接する第１のバン
プ２および第１のリード４より高く位置するため、接触
を起こすことはない。従って第１のり−ド４と第２のリ
ードらとの短絡を防ぐことができる。The second lead 5 connected to the second bump 3 has a large misalignment, but because the height of the first bump 2 is low, the second lead 5 is connected to the adjacent first lead 5. Since it is located higher than the bump 2 and the first lead 4, no contact occurs. Therefore, short circuit between the first lead 4 and the second leads can be prevented.
第３図（ａ）、（ｂ）は本発明の第２の実施例を説明す
るための半導体チップの側面図である。FIGS. 3(a) and 3(b) are side views of a semiconductor chip for explaining a second embodiment of the present invention.
第３図（ａ）、（ｂ）に示すように、第１のリード４お
よび第２のり−ド５をそれぞれ第１のバンプ２および第
２のバンプ３に接続するが、接続の工程手順は第１図に
示した第１の実施例と同じである。第１の実施例との相
違点は、第３図（ｂ）に示すように、第１のり−ド４を
圧着する際に第１のテープ６の第１のリード４が形成さ
れている側の面が下方に向くようにする点である。As shown in FIGS. 3(a) and 3(b), the first lead 4 and the second lead 5 are connected to the first bump 2 and the second bump 3, respectively, and the connection process procedure is as follows. This is the same as the first embodiment shown in FIG. The difference from the first embodiment is that, as shown in FIG. 3(b), when the first lead 4 is crimped, the side of the first tape 6 where the first lead 4 is formed is The point is to make the surface face downward.
このようにすることにより、第２のテープ７のリード形
成面が上になるように第２のリード５を圧着した場合、
第１のテープ６と第２のテープ７のリードが形成されて
いない測量士が面し、両者のリード形成面は外側に表わ
れる。従ってリード形成面上に配線パターンを造ること
ができるため、テープ上から外部へ信号をとり出すため
のパッドをテープ両面に配置することができるという利
点がある。By doing this, when the second lead 5 is crimped with the lead forming surface of the second tape 7 facing upward,
The first tape 6 and the second tape 7 face the surveyor on which no lead is formed, and the lead forming surfaces of both tapes are exposed on the outside. Therefore, since a wiring pattern can be formed on the lead forming surface, there is an advantage that pads for extracting signals from the tape to the outside can be arranged on both sides of the tape.
以上説明したように本発明は、高さの低い第１のバンプ
に第１のリードを接続したのち、高さの高い第２のバン
プに第２のリードを接続することにより、位置合わせが
ずれた場合でも、第２のバンプに接続した第２のリード
とそれに隣接した第１のバンプとの接触による短絡をな
くすことができる。その結果バンプの間隔を小さくする
ことができ、高密度のバンプを有する半導体装置が実現
できる。As explained above, in the present invention, by connecting the first lead to the first bump with a low height and then connecting the second lead to the second bump with a high height, misalignment can be avoided. Even in such a case, it is possible to eliminate short circuits due to contact between the second lead connected to the second bump and the first bump adjacent thereto. As a result, the distance between the bumps can be reduced, and a semiconductor device having a high density of bumps can be realized.
第１図（ａ）、（ｂ）及び第２図は本発明の第１の実施
例を説明するための半導体チップの側面図及び平面図、
第３図（ａ）、（ｂ）は本発明の第２の実施例を説明す
るための半導体チップの側面図、第４図（ａ）、（ｂ）
及び第５図は従来例を説明するための半導体チップの側
面図及び平面図である。
１・・・半導体基板、２，９・・・第１のバンプ、３゜
１０・・・第２のバンプ、４・・・第１のリード、５・
・・第２のリード、６・・・第１のテープ、７・・・第
２のテープ、１１Ａ、ＩＩＢ・・・リード、１２・・・
テープ。FIGS. 1(a), (b) and 2 are a side view and a plan view of a semiconductor chip for explaining the first embodiment of the present invention,
FIGS. 3(a) and (b) are side views of a semiconductor chip for explaining the second embodiment of the present invention, and FIGS. 4(a) and (b)
5 are a side view and a plan view of a semiconductor chip for explaining a conventional example. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2, 9... First bump, 3°10... Second bump, 4... First lead, 5...
...Second lead, 6...First tape, 7...Second tape, 11A, IIB...Lead, 12...
tape.
Claims (1)
１のリードを接続する工程と、次で高さの高い第２のバ
ンプに第２のリードを接続する工程とを含むことを特徴
とする半導体装置の製造方法。A step of connecting a first lead to a first bump with a low height formed on a semiconductor substrate, and a step of connecting a second lead to a second bump with a high height formed on a semiconductor substrate. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33961189A JPH03196634A (en) | 1989-12-26 | 1989-12-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33961189A JPH03196634A (en) | 1989-12-26 | 1989-12-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03196634A true JPH03196634A (en) | 1991-08-28 |
Family
ID=18329129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33961189A Pending JPH03196634A (en) | 1989-12-26 | 1989-12-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03196634A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0664563A1 (en) * | 1993-12-27 | 1995-07-26 | Kabushiki Kaisha Toshiba | TAB Bonding pads geometry for semiconductor devices |
-
1989
- 1989-12-26 JP JP33961189A patent/JPH03196634A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0664563A1 (en) * | 1993-12-27 | 1995-07-26 | Kabushiki Kaisha Toshiba | TAB Bonding pads geometry for semiconductor devices |
| US5569964A (en) * | 1993-12-27 | 1996-10-29 | Kabushiki Kaisha Toshiba | Semiconductor device |
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