JPH03196334A - Arithmetic control system - Google Patents

Abstract

PURPOSE:To minimize the instruction execution stop time by enqueing asynchronous executable arithmetic instruction into an instruction queue, checking a register interference at the time of execution, and fetching and executing an instruction which does not interfere. CONSTITUTION:An arithmetic instruction fetched from a program is enqued in an instruction queue 2-1. Subsequently, a register interference checking circuit 2-2 fetches from an instruction queue 2-1 an instruction in which it is discriminated that a register used by an instruction to be executed does not interfere with a a register used by an instruction whose execution is started already, and it is fetched and its execution is controlled. Accordingly, an asynchronous executable instruction is enqueued in the instruction queue 2-1, and at the time of execution, a register interference is checked and the instruction which does not interfere can be fetched and executed. In such a way, the instruction execution stop time by the register interference at the time of asynchronous processing can be minimized.

Description

[Detailed Description of the Invention] [Summary] Regarding an arithmetic control method that asynchronously controls instruction arithmetic, instructions that can be executed asynchronously are enqueued in an instruction queue, register interference is checked during execution, and instructions that do not interfere are retrieved and executed. By doing this, we aim to minimize instruction execution stoppage time due to register interference during asynchronous processing, and we create an instruction queue that enqueues arithmetic instructions among the instructions taken out of the program, and an instruction queue that enqueues arithmetic instructions taken out from this instruction queue and executes them. and a register interference check circuit that checks for interference between a register used by an instruction that executes the instruction and a register used by an instruction that has previously started execution, and enqueues an arithmetic instruction extracted from the program into the instruction queue, and The register interference check circuit extracts and controls the execution of instructions for which it has determined that the register used by the instruction to be extracted from this instruction queue and executed does not interfere with the register used by the instruction that has already started execution. Configure it as follows.

[Industrial application field]

The present invention relates to an arithmetic control method for asynchronously controlling instruction arithmetic. In recent years, in order to improve computer performance, instruction execution has been desynchronized. In this case, instruction execution is stopped due to register interference when executing instructions that can be executed asynchronously (interlock).
It is desired to minimize the

[Prior Art and Problems to be Solved by the Invention] Conventionally, in the synchronous type configuration shown in FIG. 4(a), if there is register interference during execution of an instruction, execution of the next instruction is stopped.

For example, ■LD RO, (M
Execution of the following instruction (2) was stopped until the LD data read from the memory by the instruction (EM) was loaded into the register RO. For this reason, there is a problem in that even instructions that do not cause subsequent register interference are stopped from being executed, leading to a decrease in performance.

Furthermore, in the configuration shown in FIG. 4 (b) with an asynchronous arithmetic unit, for example, the LD data read from memory cannot be loaded into register RO immediately after starting execution of the instruction (■) in the program in FIG. 4 (c). Therefore, it registers in the register score board that register RO is in use, executes the next instruction (2), and then attempts to execute the instruction (2). but,
As shown in Figure 4 (d), the register RO to be used has already been registered in the register score board, so the execution of the instruction ■ (41 in Figure 4) is delayed. There is a problem in that the user is forced to wait until the process completes, and the next instruction (2) without register interference cannot be executed, and the benefits of desynchronization are halved.

Incidentally, FIG. 4(A) shows a configuration diagram of a synchronous type.

Here, the central W device performs various controls, and the arithmetic unit exchanges data with registers to execute instructions. A storage device is a memory in which data is read/written according to instructions.

FIG. 4(b) shows a configuration diagram of an asynchronous type. Here, the asynchronous arithmetic unit executes arithmetic instructions that can be executed asynchronously, and includes an instruction queue that stores instructions taken out from a program and to be executed asynchronously, and an instruction queue that stores instructions that are taken out from a program and is to be executed asynchronously. It consists of a register score board that registers registers, registers that store data, and arithmetic units that perform calculations.

FIG. 4(c) shows an example program.

FIG. 4(d) shows an explanatory diagram of asynchronous type register interference. Here, register RO is registered as being in use in the register score board at the time of the LD instruction (■) in the program in Figure 4 (c), so the instruction (■) in Figure 4 (c) is executed, and When attempting to execute the instruction (2), since the instruction (2) uses the register RO, register interference occurs, so execution of the instruction is stopped at the location of the instruction (2).

Even if there is an instruction (■) without register interference after this (■), it will stop here and cannot be executed.

The present invention minimizes instruction execution stoppage time due to register interference during asynchronous processing by enqueuing instructions that can be executed asynchronously into an instruction queue, checking for register interference during execution, and extracting and executing instructions that do not interfere. It is intended to.

[Means to solve problems]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, an instruction queue 2-1 is a queue that enqueues arithmetic instructions among instructions taken out from a program.

The register interference check circuit 2-2 is connected to the instruction queue 2-1.
This circuit checks for interference between registers used by an instruction to be taken out and executed from a register used by an instruction that has previously started execution.

[Effect]

As shown in FIG.
-1, and execution control is performed by taking out an instruction for which it is determined that the register used by the instruction to be taken out and executed does not interfere with the register used by the instruction that has already started execution.

Therefore, by enqueuing instructions that can be executed asynchronously into instruction queues 2-11, checking for register interference during execution, and extracting and executing instructions that do not interfere, the time required to stop instruction execution due to register interference during asynchronous processing can be minimized. It becomes possible to

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 to 3.

In FIG. 1(A), a central control unit 1 performs various controls such as fetching instructions from a program.

The asynchronous arithmetic unit 2 executes arithmetic instructions asynchronously, and includes an instruction queue 2-1 and an instruction queue 2 that enqueue arithmetic instructions among instructions taken out from a program.
- A register interference check circuit 2-2 that checks for interference between a register used by an instruction to be taken out and executed from 1 and a register used by an instruction that has previously started execution, and a plurality of registers 2 that store data. -3, a computing unit 2-4 that performs calculations by exchanging data with a register 2-3, and the like.

The storage device 3 is a memory that stores data and the like.

FIG. 1(b) shows an example of an instruction queue. This instruction queue is a specific example of the instruction queue 2-1 in FIG.
), multiple sets of one output (one register as a destination, for example, l), and an instruction code (OP Cn).
It is enqueued in association with .

FIG. 1(c) shows an example program.

Next, in accordance with the order shown in the flowchart of FIG. 2, the operations of the configurations of FIG. 1(a) and (b) will be specifically explained based on the program example of FIG. 1(c).

In FIG. 2(a), ■ extracts one instruction. This takes out, for example, the first instruction (■) in FIG. 1(C).

@ is set on the register score board (excluding
asynchronous instructions). This is for example shown in Figure 1 (
c) Since the instruction ■ is an LD (load) instruction and not an asynchronous instruction, it is used in the register score board in Figure 1 (a) to avoid register interference when executing a synchronous instruction not shown. Set the register number.

0 determines whether the instruction is for a storage device (synchronous execution instruction) or not. If YES (in the case of an instruction for a storage device which is a synchronous execution instruction, for example, in the case of the instruction shown in FIG. On the other hand, in the case of No (in the case of an operation instruction that can be executed asynchronously), it is stored (enqueued) in the instruction queue 2-1 in Figure 1 (a) and (b) in [phase].
Then, do ■.

(2) Notifies the storage device.

Only one [phase] is processed synchronously.

O resets the register score board. These ■, [phase], and O are the instructions retrieved in ■ (instructions for the storage device that are processed synchronously, for example, in Figure 1 (c)).
Regarding the instruction 2), data is read from the address MEM of the storage device 3, loaded into the register RO, and the register score board is reset (O).

As a result of the above, for instructions for storage devices, 1
On the other hand, asynchronously executable operation instructions are sequentially stored in the instruction queue 2-1.

Next, Figure 2 (B) shows the command queue 2 in Figure 2 (B) ■.
10 shows an execution flowchart for asynchronously executing instructions sequentially enqueued to -1.

In FIG. 2(b), [phase] determines whether or not there is an instruction in the instruction queue. If YES, execute [phase] and subsequent steps. In the case of No, repeat the process (■).

[Phase] performs a register interference check between the instruction to be executed and the instruction that has previously started execution. This checks for register interference between the register used by the instruction to be taken out from the instruction queue 2-1 and executed and all the registers used by instructions that have previously started execution.

[Phase] determines whether or not there is interference. In the case of YES, the steps after ① are repeatedly executed for the next instruction. NO
In the case of , there is no interference, so it is executed in [phase], dequeued from the instruction queue 2-1 in ■, and repeatedly executed in ■.

As a result of the above, among the instructions enqueued in the instruction queue 2-1, the instructions that have started execution previously can be executed sequentially in a manner that skips instructions that do not interfere with the registers being used. It is possible to minimize execution stop time and perform processing at high speed.

FIG. 3 shows an example of the operation of the register interference check circuit according to the present invention.

FIG. 3(a) shows an example of the register check circuit for entry 2. Here, it is assumed that the instruction in entry 1 in FIG. 4(b) has already started to be executed.

This applies to registers S+Z, S2□, and D2 used when attempting to execute the instruction (OPC2) in entry 2 of instruction queue 2-1 in Figure 1 (b). It shows how to check whether there is any register interference with the register D used by the instruction (OPCl>).

That is, register S12 and register D+ of entry 2, register Szz and register D5, register D2 and register D
, are compared by a comparison circuit to see if they are not the same (there is no register interference). If one or more of them are the same, it will not be executed because it will cause register interference. If they are not the same, there is no register interference, so the entry 2
The instruction (OPC2) is executed.

FIG. 3(b) shows an example of the register check circuit for entry 3. Here, it is assumed that the instruction in entry 1.2 in FIG. 1(b) has already started execution. This is shown in Figure 1 (
b) Instruction in entry 3 of instruction queue 2-1 (OP C3
) register 311 used when trying to execute
Regarding SZS, D, whether there is any register interference with register D1 used by the instruction (OPCI) of entry 1 that has started execution previously and register D2 used by the instruction (OPC2) of entry 2. This shows how they play the game. Similarly to FIG. 3(a), entry 1 and entry 2, which have previously started execution,
are compared using a comparison circuit. If one or more of them are the same, register interference will occur, so do not execute. If they are not the same, the instruction (OPC3) of the entry 3 is executed because there is no register interference.

Generally expressing the above register interference check, the following calculation is performed, and when CONFLICT is 1 (register interference has occurred), the instruction (OPCn) of the entry is not executed. When it is 0 (register interference does not occur), the instruction (OPCn) of the relevant entry is executed.

C0NFL I CT =S, , &&D, +32. &&D, +D++&&D
+ Sth && D z + S z = && D z
+D + t && D z ten・groan・ +sli&&[)i-+ +Szt%%D , -, +
D,,%%D,-1 Here, && represents a logical product and an exclusive logical sum.

Sli is a register used for source l, sz= is a register used for source 2, and D is a register used for destination (i-1 to n-1, n is the register enqueued to instruction queue 2-1. number of entries).

〔Effect of the invention〕

As explained above, according to the present invention, a configuration is adopted in which asynchronously executable arithmetic instructions are enqueued in the instruction queue 2-1, register interference is checked during execution, and instructions that do not interfere are retrieved and executed. Therefore, the instruction execution stop time due to register interference during asynchronous processing can be minimized.

Thereby, the performance of the data processing device can be improved.

[Brief explanation of drawings]

FIG. 1 is a configuration/explanatory diagram of one embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of the present invention, FIG. 3 is an example of the operation of the register interference check circuit according to the present invention, and FIG. 4 is an explanation of the prior art. Show the diagram. In the figure, ■ is the central control unit, 2 is the asynchronous arithmetic unit, 2-1
is an instruction queue, 2-2 is a register interference check circuit, 2
-3 represents a register, 2-4 represents an arithmetic unit, and 3 represents a storage device.

Claims (1)

[Claims] In an arithmetic control method that asynchronously controls instruction arithmetic, there is an instruction queue (2-1) for enqueuing arithmetic instructions among instructions taken out from a program, and this instruction queue (2-1).
2-1) and a register interference check circuit (2-2) that checks for interference between a register used by an instruction to be retrieved from 2-1) and a register used by an instruction that has previously started execution; The arithmetic instructions retrieved from the above instruction queue (
2-1), and the register interference check circuit (2-2) takes out the instruction from this instruction queue (2-1) and uses the register used by the instruction that has already started execution. An arithmetic control method characterized by being configured to take out and control execution of instructions that are determined not to interfere with registers that are currently in use.