JPH0319575A - Field identification signal detecting circuit - Google Patents

Abstract

PURPOSE:To easily identify even/odd number fields by detecting a field identification signal with a logic circuit from a composite synchronizing signal. CONSTITUTION:A 1st monostable multivibrator circuit 2, a 1st flipflop 5, a 2nd flip-flop 6, a counter 7, and a 2nd monostable multivibrator circuit 8 are provided and an output signal of the 2nd monostable multivibrator circuit 8 and an output signal of the 1st monostable multivibrator circuit 2 are ANDed to obtain a field identification signal. Thus, a field identification signal in an accurate output timing not affected by noise and amplitude fluctuation included in the composite synchronizing signal A is detected and even/odd number fields are easily identified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a detection circuit for detecting a field identification signal from a composite synchronization signal. 2. Description of the Related Art Conventionally, a method has been widely used for field detection circuits in which a composite synchronization signal is integrated and a pulse generator is inverted at the timing when the integrated signal exceeds a reference level to obtain a field signal.

Problems to be Solved by the Invention Since the field signals obtained by the above method are output in the same format for each field, it is not possible to distinguish between odd and even fields. Furthermore, the signal obtained by dividing the frequency of the above field signal by two is a signal that is inverted for each field, but its level is H.
At the l level, it is not univocally determined whether the corresponding field is an odd field or an even field. The present invention solves the above problems,
The present invention provides a field identification signal detection circuit that can easily identify fields. Means for Solving the Problems In order to achieve the above object, the present invention uses a logic circuit to detect a field identification signal having accurate output timing from a composite synchronization signal. Specifically, it is cleared by the first monostable multivibrator triggered by the composite synchronization signal and the output signal of the first monostable multivibrator. a first flip-flop with the composite synchronization signal as a cross-clock input; a second frimbflop that is cleared by the first flip-flop output signal; and a count operation is started by the output signal of the second flip-flop. It is equipped with a counter whose clock input is the composite synchronization signal, and a second monostable multivibrator which is triggered by the output signal of the second flip-flop whose clock input is a signal output from the counter every round of counting. However, a field identification signal is obtained by performing the logical product of the output signal of the second monostable multivibrator and the output signal of the first monostable multivibrator. Operation Since the present invention has a logic circuit structure, it is possible to detect a field identification signal with accurate output timing that is not affected by noise or amplitude fluctuations contained in a composite synchronization signal. Embodiment FIG. 1 shows the structure of an embodiment in which the present invention is adapted to the NTSC system, FIG. 2 is a timing chart for an odd field, and FIG. 3 is a timing chart for an even field. In the embodiment of FIG.
0 is an input terminal to which a decoupled synchronization signal is applied, l is an inversion gate, 5.6 is a JK type flip-flop, 7 is a decimal down counter that decrements at the timing of the composite synchronization signal, and 2.8 is a monostable multivibrator. , 1l
is an AND gate, and 50 is an output terminal for the field identification signal detected from the composite synchronization signal. The monostable multivibrator 2 has a timing circuit composed of a capacitor 3 and a resistor 4, and its time constant is selected so that the output pulse amplitude T of the multivibrator 2 satisfies T,<T<T%/2. It has been done. Here, T and l represent one horizontal scanning period, and T1 corresponds to the sum of the cutting pulse width and the equalization pulse width. In addition, the monostable multivibrator 8 has a capacitor 9
and a resistor 10 have a timing circuit whose time constant is such that the output pulse width T of the multivibrator 8 is (TI
/ 2 Tt)<T<(Ti+Tz). Here, T. represents the equalization pulse width. The above is the circuit configuration in Figure 1, and the following is the circuit configuration in Figures 2 and 3.
The operation of the circuit shown in Figure 1 will be explained using the timing chart shown in the figure. The composite synchronizing signal A applied to the input terminal 30 is inverted by the inverting gate 1, and the monostable multi-bicycle signal B is triggered at the falling timing of the signal B. ! The polarizer 2 has a tying circuit consisting of a capacitor 3 and a resistor 4, so that T + < T < T
Outputs a signal C with a pulse width T of s/2. At this time, when the multi-by-break 2 is a little rubble, its output signal has a pulse width of (T + T +) only in the portion where the composite synchronization signal A transitions from the vertical synchronization pulse period to the post-equalization period, Fig. 2 is shown in this state (however, the multivibrator 2 does not necessarily have to be retriggerable). The JK flip-flop 5, which operates at the falling timing of the signal B using the signal B as a clock signal, normally holds the Q output at the Hi level because the signal C is at the Lo level at the falling edge of the signal B, and the signal B Only when is the first equalization pulse in the post-equalization period, the signal C at the falling timing is at Hi level, so the Q output changes to Lo level. This state persists while the signal C maintains the Hi level, but when the signal C shifts to the Lo level, the Q output returns to the Hi level again. By the above operation, a signal D having a period of l field is obtained. Now, at the timing when the field signal D changes from the H1 level to the Lo level, the JK flip-flop 6 sets its Q output (one signal E) to the LO level, and sets the down counter 7 to a counting operation state. At the same time, the down counter 7 receives the given brisset data (0101).
! is set to the output terminal, and the ripple clock signal F is set to H1 level. After that, the field signal D becomes H
Return to i level. Since the JK flip-flop 6 keeps its Q output at LO level while the signal F is H1, the down counter 7 is decremented at the timing of the signal B, and the down counter 7 is decremented at the timing of the signal B.
When becomes the last equalization pulse during the post-equalization period, the count output is (0000)! , so the signal F changes to Lo level. Since the signal D is at Hi level when the signal F falls, the JK flip-flop 6 returns its Q output (one signal E) to the Hl level. The system enters a stopped state. Due to the above operation, the Lo
The level signal E triggers the monostable multivibrator 8 with its rising edge. The multivibrator 8 is constructed by a tying circuit consisting of a capacitor 9 and a resistor 10, so that (TN/2-T!)<T<(TM-T
■) Outputs a signal G with a pulse width T. If we take the AND of the signal G and the signal C according to the game l, we get the signal H.
is obtained from the output end 50. In odd fields, the signal H becomes the old level at the rising edge of the post-equalizing pulse after Ik and at the rising edge of the first horizontal synchronizing pulse, and in even fields, at the rising edge of the last post-equalizing pulse. This is a signal that becomes Hl level at timing. In this way, odd and even fields are output in different formats, so the fields can be easily identified. If the present invention is compatible with the PAL system, the preset data of the down counter 7 should be (0 1 0 0)! It is sufficient to do this. Effects of the Invention As is clear from the above embodiments, the present invention detects the field identification signal using a logic circuit, so that stable and accurate operation is achieved. Since the form of the obtained field identification signal changes for each field, it is possible to easily distinguish between even and odd fields. In the above embodiment, the down counter 7 may be an up counter if the preset data is changed. Furthermore, if the polarity of the composite synchronization signal is taken into account, the JK flip-flops 5 and 6 can also be configured with D flip-flops.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a field identification signal detection circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are timing charts for explaining the operation of the circuit shown in FIG. l... Inversion gate, 2.8... Monostable multivibrator, 5.6... JK flip-flop, 7... Decimal down counter, 3,
9... Capacitor, 4, 10... Resistor, 11... AND gate, 30...
Composite synchronization signal input terminal, 50...Frame signal output terminal.

Claims (1)

[Claims] a first monostable multivibrator triggered by the composite synchronization signal; a first flip-flop whose clock input is the composite synchronization signal, which is cleared by the output signal of the first monostable multivibrator; a second flip-flop that is cleared by the flip-flop output signal; a counter that starts counting by the output signal of the second flip-flop; and which uses the composite synchronization signal as a clock input; a second monostable multivibrator that is triggered by the output signal of the second flip-flop whose clock input is a signal from the second monostable multivibrator; A field identification signal detection circuit obtains a field identification signal by performing a logical product of the output signals of.