JPH03195283A - Data decode circuit having nonlinear characteristic - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to make the circuit scale small by using an address decoder, a data decoder and a data selector to obtain a nonlinear characteristic close to a desired nonlinear characteristic. CONSTITUTION:An input data inputted to a data input terminal 11 is decoded by data decoders 151, 152, 153 so that each data is on straight lines p, q, r whose slope is 2 to the -1 power, 2 to the 0 power and 2 to the 1 power and inputted to a data selector 17. An address decoder 13 discriminates to which of 1st, 2nd and 3rd input level ranges the level of the input data inputted to the data input terminal 11 belongs and outputs a discrimination signal relating to 1/2, 1 or 2 as to the slope. The data selector 17 selects a relevant data among output data of the data decoders 151, 152, 153 based on a discrimination signal of X1/2, X1 or X2 from the address decoder 13 and outputs the result to an output terminal 19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data decoder path with nonlinear characteristics (for example, a nonlinear de-emphasis circuit of a MUSE signal receiver).

"Prior art" Data decoding circuit with non-linear characteristics, such as M
US E (Multiple 5ub-Nyqui
nonlinear day emphasis of a receiver (for example, a satellite broadcast receiver for high-definition television) that receives the st SamplingEncoding signal.
r de-emphasis) circuit converts the demodulated signal (
For example, in order to increase the S/N ratio (signal-to-noise ratio) of a video signal, non-linear emphasis
This is a circuit that restores the signal to which it has been applied (near emphasis). Generally, such a non-linear de-emphasis circuit is composed of a non-linear circuit 1 and a de-emphasis filter 3, as shown in FIG. By storing predetermined data in this ROM, desired nonlinear characteristics as shown by the dotted line in FIG. 2 can be obtained. That is,
This nonlinear characteristic divides the input signal level range from the center point (
This shows the characteristics of the positive side when divided from the center point O into the negative side and the positive side. )
The signal level is expressed as 9 bits (0 to 9 bits) on the vertical axis (y axis).
512), the input signal level is at the center point 0 (
x = o, y = 0) to point A (x = 224, y = 112
), the signal level increases along a straight line with a slope of 1/2, and the human signal level increases from point A to point B (x=512,
y=512), the signal level increases along an elliptic curve with a slope of 172 at point A and a slope of 572 at point B. The negative side characteristic is a characteristic that is symmetrical to the center point O compared to the positive side characteristic.

[Problems to be Solved by the Invention] However, in nonlinear circuits that use conventional ROM to obtain nonlinear characteristics as shown by the dotted line in Figure 2, the circuit size is limited because data is stored in ROM. There was a problem in that it became larger. Also, R.O.
When M is not used, there is a problem that the circuit configuration becomes extremely complicated. A similar problem exists in data decoding circuits having general non-linear characteristics.

The present invention has been made in view of the above-mentioned problems, and provides a data decoding circuit that can simplify the circuit configuration, reduce the circuit scale, and has nonlinear characteristics that can almost satisfy the desired nonlinear characteristics. The purpose is to provide

[Means for Solving the Problems] A data decoding circuit with non-linear characteristics according to the present invention is capable of determining to which of m (m is an integer of 2 or more) input signal level ranges the level of input data belongs. An address decoder that discriminates and outputs a discrimination signal, and an address decoder that outputs a discrimination signal, and an address decoder whose slope is 2 (n is an integer including O).
power, 2 to the (n+1) power, ..., 2 to the (n + m −
1) m data decoders that perform decoding so as to ride on a straight line, and corresponding data J is selected and output from the output data of the m data decoders based on the discrimination output of the address decoder. The device is characterized in that it is equipped with a data selector.

[Operation] The address decoder determines to which of m input signal level ranges the level of input data belongs, and outputs a determination signal. The m data decoders convert the human data into slopes of 2 to the nth power, 2 to the (n+1.) power, . . .
It is decoded so that it rides on a straight line of 2 to the (n+m 1) power. The data selector selects and outputs corresponding data from among the output data of the m data decoders based on the discrimination output of the address decoder. That is, when the level of input data belongs to the first level range of m signal input level ranges, the data selector selects the output data (input data) of the first data decoder based on the discrimination output of the address decoder. data decoded so that the slope lies on a straight line with a slope of 2 to the nth power) is selected and output.

When the level of the human data belongs to the second level range, the data selector selects the output data of the second data decoder (input data with a slope of 2) based on the discrimination output of the address decoder. (data decoded so that it rides on the straight line of the power) is selected and output. Similarly, when the level of the input data belongs to the m-th level range, the data selector selects the output data of the m-th data decoder (input data with a slope of 2) based on the discrimination output of the address decoder. (data decoded so as to lie on a straight line raised to the power of (n+m-1)) is selected and output. Therefore, a data decoding circuit having nonlinear characteristics performs data processing that satisfies nonlinear characteristics that approximate desired nonlinear characteristics.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a nonlinear de-emphasis circuit of a MUSE signal receiver. In this figure, 11 is a data input terminal.

The data input terminal 11 receives, for example, data received by a receiving antenna, input level converted by a BS converter, tuned and demodulated by a tuning demodulation circuit, and analog/digital by an A/D conversion circuit.
The input is data that has been digitally converted and has non-linear emphasis applied to it, like a video clip that has been separated by a video/audio separation circuit. The data input terminal 11 has the input data level set at the center point (origin) of the input signal level range.
The first, second, and
The address decoder 13 determines which of the third input level range it belongs to and outputs a determination signal.
2), 2 to the 0th power (i.e., the slope is 1), a straight line of 2 to the 1st power (i.e., the slope is 2) (i.e., for the positive side from the center point O to the highest input level, y = (1/2) x
straight line p, y = straight line q of x-128, y =
2x -512, and for the negative side from the center point 0 to the lowest input level, the positive side lines p, q,
Three data decoders 151.15□, 1 decode so as to ride on a straight line (not shown) symmetrical to the center point O of r.
5. are combined. , the data decoder 15□
, 15□, and 153 are coupled to an output terminal 19 via a data selector 17. The data selector 17
is configured to select corresponding data from the output data of the data decoders 151, 15□, 153 based on the discrimination output of the address decoder 13 and output it to the output terminal 19. The output terminal 19 is coupled to the input side of a de-emphasis filter 3 as shown in FIG.

Next, the operation of the embodiment described above will be explained with reference to FIG. 2.

Figure 2 shows the input signal level range of input data at the center point O.
This shows the non-linear characteristics on the positive side from the center point O to the highest input level when divided into negative and positive sides.The non-linear characteristics on the negative side from the center point O to the lowest input level are shown at the center point. Since it is symmetrical with respect to 0 (x=01y=0), explanation and illustration will be omitted. In Figure 2, the X-axis (horizontal axis) represents the positive side from the input data level center point 0 to the highest input level in 9 bits (0 to 512), and the y-axis (vertical axis) represents the signal level in 9 bits. (O~512
), and when this input level range on the positive side is divided into three, it is shown as follows: (when m=3). That is, the center point 0 (x=
0) to the highest point B (x=512), 172 α points (
X: 256) as the first, and β point 1/2 of the range from α to B from this α point (x = (512-256)
1/2=384) as the second, and from this β point to B point (
x=512) as the third range.

The input data input to the data input terminal 11 is processed by the data decoders 15□, 15□, and 153 into straight lines with slopes of 2 to the 11th power (in the case of n=-1), 2 to the 0th power, and 2 to the 1st power, respectively. It is decoded so as to be placed on p, q, and r and input to the data selector 17. The address decoder 13 determines that the level of the input data input to the data input terminal 11 is the first level,
It is determined which of the second and third input level ranges it belongs to, and a corresponding determination signal (X (1/2), ×1 or X2) having a slope of 1/2.1 or 2 is output. The data selector 17 receives ×17 from the address decoder 13.
Based on the determination signal 2, Xl or ×2, the corresponding data is selected from among the output data of the data decoders 151, 15□, 153 and output to the output terminal 19. That is, the input data input to the data input terminal 11 is
The signal is processed according to approximate nonlinear characteristics as shown by solid lines (straight lines p, q, r) in the figure, and is sent to the output terminal 19.

In the above embodiment, the case where m = 3 and n = -1 was explained, but the present invention is not limited to this, and m may be an integer of 2 or more (for example, 2.4.5, . . . ). Good luck,
n is an integer including O (e.g., -3, 2, 0, 1,
2, 3, ...).

In the above embodiment, the input signal level range is defined as the center point (origin).
Although the present invention is not limited to this, m level ranges are formed on both sides of the center point O by sequentially dividing them into 1/2 parts from O toward the negative side and the positive side. Any method may be used as long as the signal level range is divided into m (m is an integer of 2 or more) level ranges.

In the embodiment described above, the present invention is applied to a non-linear de-emphasis circuit of a MUSE signal receiver, but the present invention is not limited to this, and can be applied to general data decoding circuits having non-linear characteristics. can.

[Effects of the Invention] As described above, the data decoding circuit with non-linear characteristics according to the present invention has the address decoder, data decoder, and data selector that can reduce the circuit scale for digital signal processing. Since it is possible to obtain nonlinear characteristics similar to the nonlinear characteristics of At the same time, the circuit scale can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data decoding circuit with non-linear characteristics according to the present invention, and FIG. 2 is a characteristic diagram explaining the operation of FIG. 1 (the solid line indicates the approximate characteristic according to the present invention, and the dotted line FIG. 3 is a block diagram of a nonlinear de-emphasis circuit of a general MUSE signal receiver. DESCRIPTION OF SYMBOLS 1...Nonlinear circuit, 3...Diephasis filter, ]1...Data input terminal, 13...Address decoder, 151.15□, 153...Data decoder, 17...Data selector, m ...an integer greater than or equal to 2,
n...Integer including 0, O...Center point (origin), p,
q, r... Straight line, α, β... Delimits the input level range and connects the straight lines p and q, q and r.

Claims (2)

[Claims] (1) An address decoder that determines which of m (m is an integer of 2 or more) input signal level ranges the level of input data belongs to and outputs a determination signal; is 2 to the n (n is an integer including 0) power, 2 to the (n+1) power, ..., 2 to the (n+m-1) power
m data decoders that perform decoding so as to ride on a multiplicative straight line; and a data selector that selects and outputs corresponding data from among the output data of the m data decoders based on the discrimination output of the address decoder. A data decoding circuit having non-linear characteristics. (2) A data decoding circuit having non-linear characteristics according to claim (1), wherein m=3 and n=-1.