JPH03195170A - signal receiving circuit - Google Patents
signal receiving circuitInfo
- Publication number
- JPH03195170A JPH03195170A JP33535389A JP33535389A JPH03195170A JP H03195170 A JPH03195170 A JP H03195170A JP 33535389 A JP33535389 A JP 33535389A JP 33535389 A JP33535389 A JP 33535389A JP H03195170 A JPH03195170 A JP H03195170A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- signal
- input signal
- level
- voltage level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
- Meter Arrangements (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
周波数が一定で振幅値が変動する交流信号を受信する信
号受信回路に関し、
与えられた規格を満足する信号受信回路の提供を目的と
し、
入力信号と所定電圧レベルとを比較する比較器と、
該比較器に与える該所定電圧レベルを変更する閾値変更
手段を備え、
前記入力信号に対して第1の電圧レベル以上の信号を検
出した時、前記閾値変更手段により、該第1の電圧レベ
ルより小さい第2の電圧レベルを前記比較器に与え、以
後受信する入力信号を前記第2の電圧レベルにて判定す
るように構成する。[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a signal receiving circuit that satisfies a given standard regarding a signal receiving circuit that receives an alternating current signal whose frequency is constant and whose amplitude value fluctuates. a comparator for comparing the predetermined voltage level with a voltage level, and a threshold value changing means for changing the predetermined voltage level applied to the comparator, and when a signal of a first voltage level or higher is detected with respect to the input signal, the threshold value is changed. A second voltage level smaller than the first voltage level is applied to the comparator by means of the comparator, and input signals received thereafter are determined at the second voltage level.
〔産業上の利用分野]
本発明は、局交換機よりの課金信号を受信する構内交換
機(以下PBXと称す)の信号受信回路に係り、特に周
波数が一定で振幅値が変動する交流信号を受信する信号
受信回路に関するものである。[Industrial Application Field] The present invention relates to a signal receiving circuit for a private branch exchange (hereinafter referred to as PBX) that receives billing signals from a central office exchange, and in particular receives an alternating current signal whose frequency is constant and whose amplitude value varies. This invention relates to a signal receiving circuit.
第4図は1例の本発明を適用する通信システムのブロッ
ク図及び信号受信回路の規格を示す図である。FIG. 4 is a block diagram of an example of a communication system to which the present invention is applied, and a diagram showing standards of a signal receiving circuit.
第4図(A)において、PBXが局交換機10を介して
通話中は、局交換機10より正弦波の課金信号が送られ
、PBXIIの信号受信回路21はこれを受信する。In FIG. 4(A), while the PBX is communicating via the central office exchange 10, a sinusoidal billing signal is sent from the central office exchange 10, and the signal receiving circuit 21 of the PBX II receives this.
この信号受信回路21の規格として、国によっては下記
の如き規格がある。As standards for this signal receiving circuit 21, there are the following standards depending on the country.
局交換機10の課金信号発振器の出力レベルは、例えば
5%程度変動するものとし、又第4図(B)に示す如(
、雑音レベルに近い電圧■1と、電圧■1より課金信号
のレベル変動幅より僅か高い電圧■2を定め、第4図(
B)の(e)に示す如く入力信号のピークの最大値が電
圧■1以下の時は信号を受信せず、第4図(B)の(d
)(C)(b)に示す如く、入力信号のピーク値の内、
電圧■1と■2の間に入るものがあれば入力信号と同じ
周波数の信号を出力するか又は受信せず、第4図(B)
の(a)に示す如く入力信号のピークの最小値が電圧7
2以上の時は入力信号と同じ周波数の信号を出力せねば
ならないとなっている。It is assumed that the output level of the billing signal oscillator of the central office exchange 10 fluctuates, for example, by about 5%, and as shown in FIG. 4(B).
, voltage ■1 close to the noise level and voltage ■2 slightly higher than the level fluctuation width of the billing signal than voltage ■1 are determined, and as shown in Fig. 4 (
As shown in (e) of Fig. 4 (B), when the maximum value of the input signal peak is less than the voltage ■1, no signal is received, and (d) of Fig. 4 (B)
) (C) As shown in (b), among the peak values of the input signal,
If there is anything between voltages ■1 and ■2, it will output a signal with the same frequency as the input signal or will not receive it, as shown in Figure 4 (B).
As shown in (a), the minimum value of the peak of the input signal is at voltage 7.
When it is 2 or more, a signal with the same frequency as the input signal must be output.
従って、上記規格を満たす信号受信回路が必要となる。Therefore, a signal receiving circuit that meets the above standards is required.
尚以下電圧Vl、V2は上記定義した電圧を示すものと
する。Note that the voltages Vl and V2 hereinafter refer to the voltages defined above.
第5図は従来例の信号受信回路のブロック図及び入力信
号、出力信号のタイムチャートである。FIG. 5 is a block diagram of a conventional signal receiving circuit and a time chart of input signals and output signals.
第5図(A)の信号受信回路は、比較器1を用い、一方
の端子には例えば5%ピーク値が変動し周波数が略一定
な正弦波が入力し、他方の端子には、抵抗R6,R7に
て電圧Vを分圧し閾値電圧Vいが与えられ、出力には抵
抗R5を介して電圧■が印加されており、入力信号が閾
値電圧v th以上になると、出力はOレベル、閾値電
圧Vい以下ではルベルとなる。The signal receiving circuit of FIG. 5(A) uses a comparator 1, and a sine wave whose peak value fluctuates by, for example, 5% and whose frequency is approximately constant is input to one terminal, and a resistor R6 is input to the other terminal. , R7 divides the voltage V to give a threshold voltage V, and voltage ■ is applied to the output via the resistor R5. When the input signal exceeds the threshold voltage Vth, the output goes to O level, the threshold. If the voltage is less than V, it becomes a level.
この信号受信回路では、閾値電圧Vいを電圧■lとする
と、第5図(B)(出力)に示す如く、(a)(b)(
c)の場合は入力信号と同じ周波数の信号を出力し、(
e)の場合は受信しないが、(d)の場合は、閾値電圧
Vい以上となるのは一部のピーク値であるので、出力は
入力信号と異なる周波数の信号となり、この場合が規格
を満足しない。In this signal receiving circuit, if the threshold voltage V is the voltage ■l, then (a), (b) (
In the case of c), a signal with the same frequency as the input signal is output, and (
In case e), it is not received, but in case (d), some of the peak values exceed the threshold voltage V, so the output is a signal with a frequency different from the input signal, and this case does not comply with the standard. Not satisfied.
又閾値電圧v thを電圧■2とすると、第5図(B)
(a)の場合は入力信号と同じ周波数の信号を出力し、
第5図(B)の(c)(d)(e)の場合は受信しない
が、(b)の場合は、閾値電圧v th以上となるのは
一部のピーク値であるので、出力は入力信号と異なる周
波数の信号となり、この場合が規格を満足しない。Also, if the threshold voltage v th is the voltage ■2, then Fig. 5 (B)
In case (a), output a signal with the same frequency as the input signal,
In cases (c), (d), and (e) of Fig. 5 (B), no reception is received, but in case (b), some peak values exceed the threshold voltage v th, so the output is The signal will have a frequency different from that of the input signal, and in this case the standard will not be met.
又第5図(B)に示す如く、閾値電圧v thを電圧■
1と■2の間とすると、第5図(B)の(a)(b)の
場合は、入力信号と同じ周波数の信号を出力し、第5図
(B)の(d)(e)の場合は受信しないが、(C)の
場合は、閾値電圧Vい以上となるのは一部のピーク値で
あるので、出力は入力信号と異なる周波数の信号となり
、この場合が規格を満足しない。In addition, as shown in FIG. 5(B), the threshold voltage v th is
1 and ■2, in the case of (a) and (b) in Fig. 5(B), a signal with the same frequency as the input signal is output, and in the case of (d) and (e) in Fig. 5(B) In the case of (C), the signal is not received, but in the case of (C), some of the peak values exceed the threshold voltage V, so the output is a signal with a frequency different from the input signal, and this case does not satisfy the standard. .
従来例の信号受信回路では、閾値電圧v thをどこに
選んでも第5図(B)(a)〜(e)の内の4何れかで
条件を満足しない。In the conventional signal receiving circuit, no matter where the threshold voltage v th is selected, any of the four conditions shown in FIG. 5(B) (a) to (e) is not satisfied.
上記説明の如〈従来の信号受信回路では与えられた規格
を満足しない問題点がある。As explained above, there is a problem that conventional signal receiving circuits do not meet the given standards.
本発明は、与えられた規格を満足する信号受信回路の提
供を目的としている。The present invention aims to provide a signal receiving circuit that satisfies given standards.
第1図は本発明の原理ブロック図である。 FIG. 1 is a block diagram of the principle of the present invention.
周波数が一定で振幅値が変動する交流信号を受信する信
号受信回路において、
第1図に示す如く、
入力信号と所定電圧レベルとを比較する比較器1と、該
比較器1に与える該所定電圧レベルを変更する閾値変更
手段2を備え、
前記入力信号に対して第1の電圧■2のレベル以上の信
号を検出した時、前記閾値変更手段2により、該第1の
電圧v2のレベルより小さい第2の電圧■1のレベルを
前記比較器1に与え、以後受信する入力信号を前記第2
の電圧■1のレベルにて判定するように構成する。In a signal receiving circuit that receives an alternating current signal whose frequency is constant and whose amplitude value varies, as shown in FIG. A threshold changing means 2 is provided for changing the level, and when a signal higher than the level of the first voltage v2 is detected with respect to the input signal, the threshold changing means 2 controls the input signal to be lower than the level of the first voltage v2. The level of the second voltage (1) is applied to the comparator 1, and the input signal to be received thereafter is applied to the second voltage.
The configuration is such that the determination is made at the level of the voltage (1).
本発明によれば、比較器1の通常の閾値電圧は■2であ
るので、第4図(B)の(c)(d)(e)に示す如く
、入力信号のピークの最大値が電圧■2以下の時は、受
信せず、又第4図(B)の(a)に示す如く、入力信号
のピークの最小値が電圧72以上の時は、入力信号と同
じ周波数の信号を出力する。According to the present invention, since the normal threshold voltage of the comparator 1 is 2, the maximum value of the peak of the input signal is the voltage as shown in (c), (d), and (e) of FIG. ■When the voltage is 2 or less, no reception is received, and as shown in Figure 4 (B) (a), when the minimum value of the peak of the input signal is 72 or more, a signal with the same frequency as the input signal is output. do.
第4図(B)の(b)に示す如く、ピークの最大値は電
圧72以上で、最小値は電圧■2以下で電圧■1以上の
場合は、入力信号のピーク値が電圧v2を越えた時点で
、閾値電圧は■1となるので、入力信号と同じ周波数の
信号を出力する。As shown in (b) of Figure 4 (B), if the maximum value of the peak is voltage 72 or more, and the minimum value is voltage 2 or less and voltage 1 or more, the peak value of the input signal exceeds voltage v2. At this point, the threshold voltage becomes 1, so a signal with the same frequency as the input signal is output.
即ち、与えられた規格を全て満足することになる。In other words, it satisfies all the given standards.
[実施例〕
第2図は本発明の実施例の信号受信回路のブロック図、
第3図は第2図の各部のタイムチャートで、(A)は入
力信号、(B)は出力信号。[Embodiment] FIG. 2 is a block diagram of a signal receiving circuit according to an embodiment of the present invention.
FIG. 3 is a time chart of each part in FIG. 2, where (A) is an input signal and (B) is an output signal.
(C)は単安定マルチバイブレーク3の出力、(D)は
ノット回路4の出力を示している。(C) shows the output of the monostable multi-by-break 3, and (D) shows the output of the NOT circuit 4.
第2図のスイッチSWは通常は実線側で、電圧■を抵抗
R1,R2にて分圧し、比較器1の閾値電圧として電圧
■2を与え、スイッチSWが点線側となると、抵抗R3
が、抵抗R2と並列になり閾値電圧は電圧■1となるよ
うになっている。The switch SW in FIG. 2 is normally on the solid line side, and the voltage ■ is divided by resistors R1 and R2 to give voltage ■2 as the threshold voltage of the comparator 1. When the switch SW is on the dotted line side, the resistor R3
is connected in parallel with the resistor R2, so that the threshold voltage becomes voltage ■1.
従って、第4図(B)の(c) (d) (e)に示す
如く、入力信号のピークの最大値が電圧■2以下であれ
ば、信号を受信しない。第4図(B)の(a)の如く、
入力信号のピークの最小値も電圧72以上であれば、次
に入力信号と同じ周波数の信号を出力する。Therefore, as shown in (c), (d), and (e) of FIG. 4(B), if the maximum value of the peak of the input signal is less than the voltage 2, no signal is received. As shown in (a) of Figure 4 (B),
If the minimum value of the peak of the input signal is also voltage 72 or higher, then a signal with the same frequency as the input signal is output.
次に、第4図(B)の(b)に示す場合を、第2図、第
3図を用いて説明する。Next, the case shown in FIG. 4(B)(b) will be explained using FIGS. 2 and 3.
第3図(A)に示す如く、入力信号のピークが電圧V2
を越えると、第3図(B)に示す如く、出力は0レベル
となり、単安定マルチバイブレーク3を起動する。As shown in Figure 3 (A), the peak of the input signal is at voltage V2.
When the value exceeds 0, the output becomes 0 level, as shown in FIG. 3(B), and the monostable multi-by-break 3 is activated.
すると、抵抗R4,コンデンサCによる時定数にて定ま
る、第3図tにて示す、入力信号の1周期より大きい幅
の間、単安定マルチバイブレーク3の出力は、(C)に
示す如く0レベルとなり、ノット回路4の出力は第3図
(D)に示す如くルベルとなり、スイッチSWを点線側
とする。Then, during a width larger than one cycle of the input signal as shown in Figure 3 t, which is determined by the time constant of resistor R4 and capacitor C, the output of monostable multi-bi break 3 is at the 0 level as shown in (C). Therefore, the output of the knot circuit 4 becomes a level as shown in FIG. 3(D), and the switch SW is set to the dotted line side.
すると閾値電圧は電圧■1となる。Then, the threshold voltage becomes voltage ■1.
こうなると、入力信号のピークは全て閾値電圧v1を越
え、越える度に、比較器1の出力はOレベルになり単安
定マルチバイブレーク3は起動され、出力は(C)に示
す如く0レベルの侭で、ノット回路4の出力は(D)に
示す如くルベルの侭で、スイッチSWは点線側の侭で、
出力よりは(B)に示す如く、入力信号と同じ周波数の
信号が出力される。In this case, all the peaks of the input signal exceed the threshold voltage v1, and each time the peak of the input signal exceeds the threshold voltage v1, the output of the comparator 1 becomes O level, the monostable multi-vibration break 3 is activated, and the output remains at the 0 level as shown in (C). The output of the knot circuit 4 is on the side of the rubel as shown in (D), and the switch SW is on the side of the dotted line.
As shown in (B), a signal having the same frequency as the input signal is output from the output.
尚入力信号が断となると、スイッチSWは実線側となり
、元に戻る。Note that when the input signal is disconnected, the switch SW changes to the solid line side and returns to its original state.
第4図(B)の(a)の如く、入力信号のピークの最小
値も電圧v2以上であれば、入力信号のピークが電圧■
2を越えると、上記の如く閾値電圧が電圧■1となるの
で、入力信号と同じ周波数の信号を出力するのは勿論で
ある。As shown in (a) of FIG. 4(B), if the minimum value of the peak of the input signal is also higher than the voltage v2, the peak of the input signal is at the voltage
If it exceeds 2, the threshold voltage becomes voltage 1 as described above, so of course a signal having the same frequency as the input signal is output.
即ち、第2図の信号受信回路は全ての規格を満足する。That is, the signal receiving circuit shown in FIG. 2 satisfies all standards.
尚入力信号は正弦波の場合で説明したが、これは、矩形
波でも三角波でも勿論全ての規格を満足する。Although the input signal has been described as a sine wave, it goes without saying that even a rectangular wave or a triangular wave satisfies all standards.
以上詳細に説明せる如く本発明によれば、与えられた規
格を満足する信号受信回路が得られる効果がある。As explained in detail above, according to the present invention, it is possible to obtain a signal receiving circuit that satisfies the given standards.
第1図は本発明の原理ブロック図、
第2図は本発明の実施例の信号受信回路のブロック図、
第3図は第2図の各部のタイムチャート、第4図は1例
の本発明を適用する通信システムのブロック図及び信号
受信回路の規格を示す図、第5図は従来例の信号受信回
路のブロック図及び入力信号、出力信号のタイムチャー
トである。
図において、
■は比較器、
2は閾値変更手段、
3は単安定マルチバイブレーク、
4はノット回路、
10は局交換機、
11は構内交換機、
21は信号受信回路、
R1−R7は抵抗、
Cはコンデンサ、
開
竿2二〇吉郭の9・仏子ヤード
13 記
杢弛日月の賓誇例の侶号受イ占旦万&のブ゛口7フ2j
2 図
(a)
(C)
Cd’)
(e)
485−Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of a signal receiving circuit according to an embodiment of the present invention, Fig. 3 is a time chart of each part of Fig. 2, and Fig. 4 is an example of the present invention. FIG. 5 is a block diagram of a conventional signal receiving circuit and a time chart of input signals and output signals. In the figure, ■ is a comparator, 2 is a threshold value changing means, 3 is a monostable multivib break, 4 is a knot circuit, 10 is a central office exchange, 11 is a private branch exchange, 21 is a signal receiving circuit, R1-R7 are resistors, and C is a Capacitor, open rod 220 Kichikuo 9, Butsuko yard 13, record of the number of guests of the sun and moon, receiving the title of a priest, Zhandan 10,000 &'s mouth 7f 2j
2 Figure (a) (C) Cd') (e) 485-
Claims (1)
号受信回路において、 入力信号と所定電圧レベルとを比較する比較器(1)と
、 該比較器(1)に与える該所定電圧レベルを変更する閾
値変更手段(2)を備え、 前記入力信号に対して第1の電圧レベル以上の信号を検
出した時、前記閾値変更手段(2)により、該第1の電
圧レベルより小さい第2の電圧レベルを前記比較器(1
)に与え、以後受信する入力信号を前記第2の電圧レベ
ルにて判定することを特徴とする信号受信回路。[Claims] A signal receiving circuit that receives an alternating current signal having a constant frequency and varying amplitude values, comprising: a comparator (1) that compares an input signal with a predetermined voltage level; and a voltage applied to the comparator (1). A threshold changing means (2) for changing the predetermined voltage level is provided, and when a signal of a first voltage level or higher is detected for the input signal, the threshold changing means (2) changes the first voltage level to the first voltage level. A smaller second voltage level is applied to the comparator (1).
), and determines an input signal to be received thereafter at the second voltage level.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33535389A JPH03195170A (en) | 1989-12-25 | 1989-12-25 | signal receiving circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33535389A JPH03195170A (en) | 1989-12-25 | 1989-12-25 | signal receiving circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03195170A true JPH03195170A (en) | 1991-08-26 |
Family
ID=18287580
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33535389A Pending JPH03195170A (en) | 1989-12-25 | 1989-12-25 | signal receiving circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03195170A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114221641A (en) * | 2022-02-21 | 2022-03-22 | 成都芯翼科技有限公司 | Rapid comparator circuit for wide common-mode input voltage |
-
1989
- 1989-12-25 JP JP33535389A patent/JPH03195170A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114221641A (en) * | 2022-02-21 | 2022-03-22 | 成都芯翼科技有限公司 | Rapid comparator circuit for wide common-mode input voltage |
CN114221641B (en) * | 2022-02-21 | 2022-05-20 | 成都芯翼科技有限公司 | Rapid comparator circuit for wide common-mode input voltage |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA1190653A (en) | Digital waveform conditioning circuit | |
US4433256A (en) | Limiter with dynamic hysteresis | |
US5907254A (en) | Reshaping periodic waveforms to a selected duty cycle | |
US5498985A (en) | Dual comparator trigger circuit for glitch capture | |
US5394022A (en) | Pulse width modulation circuit apparatus | |
WO1988005227A1 (en) | Digital receiver with dual references | |
JPH03195170A (en) | signal receiving circuit | |
US3810026A (en) | Duty factor correction circuit | |
JPH04223789A (en) | Signal slope sharpening circuit disposition | |
US4549143A (en) | F.M. Demodulator with waveform correction circuit | |
JPH08139689A (en) | Signal receiver | |
US6160792A (en) | Pulse amplitude modulated tone generator | |
JPH03112231A (en) | Circuit device for reproducing clock | |
JPH06224711A (en) | Digital signal reception circuit | |
JP3096365B2 (en) | DTMF signal generation circuit | |
JPH01191548A (en) | Frequency detection demodulation circuit | |
JP2809518B2 (en) | Method and apparatus for regenerating timing information from an NRZ pulse train | |
JPH04342315A (en) | Burst signal reception circuit | |
JP2626191B2 (en) | AMI signal receiving circuit | |
SU1688412A1 (en) | Delta-codec | |
JPS6013364A (en) | A circuit device for reproducing data contained in a binary data signal | |
JPH02296419A (en) | Balanced element selection method for balanced network | |
CA1067589A (en) | Tracking oscillator and use of the same in a frequency to voltage converter | |
JPS60181659A (en) | Phase comparator | |
JPH03256457A (en) | Digital signal separator circuit |