JPH0319176A - Data encoding circuit - Google Patents

Abstract

PURPOSE:To simplify circuit constitution and to reduce the number of external connection pins by providing memories for shuffling a video signal and memories for shuffling and audio signal in one memory space. CONSTITUTION:The memories M1-M3 for shuffling the video signal and the memories MAU1 and MAU2 for shuffling the audio signal are provided in the memory space of one memory device. When three sectors are secured for enlarging time for writing and reading as a memory capacity required for the sector shuffle of the video signal, memory blocks M1-M3 and memory blocks MAU1 and MAU2 can be provided in the memory space of 128k bytes such as a real memory IC and the like. Thus, circuit constitution can be simplified and the number of the pins of an IC package can be reduced.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to data used in an encoder circuit of a digital VTR (video table recorder), etc. [Summary of the Invention] In a data encoding circuit that divides a signal into a predetermined number of recording blocks and shuffles each divided signal for block encoding, a memory for shuffling a video signal and a memory for shuffling an audio signal are used. By providing it within the memory space of one memory device, it simplifies the circuit structure and reduces the number of external connection pins when integrated into an IC. [Prior art] Digital VT that digitizes and records video signals
R (video tape recorder) formats include the so-called D1 format, which digitizes component signals of luminance signals and chroma signals, NTSC and P
The so-called D2 format, etc., which directly digitizes a composite signal of a television standard system such as AL, is known. In the formats of these digital VTRs, one field of input digital signals is divided into a predetermined number of blocks, and the divided signals are block encoded by so-called shuffling or the like. For example, FIG. 4 shows a data encoding circuit, a so-called encoder circuit, on the recording side of the so-called D2 format digital VTR. In FIG. 4, the digital video signal supplied to the input terminal 1l is sent to the line shuffle circuit 12 and shuffled for one line (l horizontal period, 1
(1) After the valid data in 1) is shuffled, it is sent to the outer ECC encoder (or outer parity addition circuit) 13. For example, in the case of the so-called PAL system, the input video signal V▲9 I}I-64μsec as shown in FIG.
After extracting 948 samples as valid data from the data and performing the above-mentioned intra-line shuffling, they are sent to the outer ECC encoder 13. The word length of each sample data is 8
It is set as bit (l byte). In addition, the so-called NTS
In the case of C method, l H
= 63.55 usec, and the number of valid data is 768 samples. The numerical values in the following explanation are for the PAL system, and those for the NTSC system are shown in parentheses.
The outer ECC encoder 13 sends the shuffled valid data to two channels, namely channel 0.
and channel l, 474 of each channel
(384) Divide each byte of data into 6 equal parts, 79
(64) Generate 6 outer parity blocks in which a 4-byte outer parity code is added to the byte data, and
Output the data DPA and DPB shown in the figure. These output data [lPA, DPB are the sector shuffle circuit 14
The data for one sector and 76 (85) lines is written/outputted to the shuffle memory, thereby being shuffled. Here, FIG. 6 shows valid data in one field, with 948 (768) samples per line and 3
04 (255) lines of sample data are distributed to channel 0 and channel l in a so-called checkerboard pattern in which one sample is alternated and reversed between lines. Also, the valid data in one field is 76 (8
5) Each line is divided into four (3) segments, and channel O and channel I of each segment constitute a sector. In other words, the l sector is 474 (384) per line and 76 (85
) line, the number of sample words or bytes per sector is 474X76=36024
(One byte is sorted) :PAL( 38
4X85=32640 (with hood +1 is part-time job): NTSC). FIG. 7 shows the state of data arrangement within one sector when writing/sequentially outputting data to one sector memory provided in the sector shuffle circuit 14. That is, first of all, 474 (
474 (384) + 6 = 79 (6
4) By adding 4 words of outer parity code to each block of words and doing this for the above 76 (85) lines, 76 (85) x 6-45 in the horizontal direction
6 (510) bytes, 79 (64) +4- vertically
Constructs a capacity space of 83 (68) words. The data within each line is rearranged (shuffled) at 12 sample periods. The amount of data in this one sector is 83X456=37848 [bytes]: PAL
(68X510=34684 [bytes]:
NTSC). In the horizontal direction of this sector array,
Six sub-arrays (small arrays) with a height of 76 (85) are arranged, and when recording data, they are sequentially read in the horizontal direction from the lower left corner in the figure, and 8 words = 8 for each sub-array of 76 (85) bytes. Add the inner ECC (inner parity code) of the byte. At this time, as shown in FIG. 7, a SYNC (synchronization pattern) and an ID (identification pattern) are added to each of the two parity blocks to form one sync block. Note that the first inner parity block in one sync block also includes the above-mentioned ID (J" different pattern). Returning to FIG. 4 again, the sector shuffle circuit 14 has four sector memories H^1. , M.A.
2, MBI, MB2 are provided, and the channels 0 and ! from the outer CC encoder l3 are provided. The sample data respectively distributed to the sector shuffling circuit 14 is sent to the sector memories MAL, MA2 and MBI, MB2 via the changeover switches S^1 and SBI, respectively, in the sector shuffle circuit 14. FIG. 8 shows write (W) and subsequent write (R) to these four sector memory bars ^1 to MB2.
) is shown for the case of the above PAL system, and two memories of one channel, for example h^
1, M^2 is controlled so that while data for one sector is written to one, it is read from the other. Channel O data read from sector memories h^1 and M^2 is output via changeover switch S^2, and channel 1 data read from sector memories MBI and MB2 is outputted through changeover switch SR2. Output via . Here, the data write operation to the sector shuffle circuit 14 is performed using the input video signal V+a from the input terminal 11.
The data read operation is controlled by a write control signal etc. generated by a timing generation circuit 31 based on a synchronization signal etc. of It is controlled by successive control signals, etc. this is,
Considering that the recording data is output by the queuing read from the sector shuffle circuit 14, this is made to match the recording reference signal. The respective data of channels 0 and l from the sector shuffle circuit 14 are sent to SYNC, Ill, and inner[!] via changeover switches 15A and 15B, respectively. CC addition circuit l6
It is being sent to A and 16B. This additional circuit 16A, 16
The output data from B uses a sync block as a basic unit, in which a SYNC (synchronization pattern) and an ID (1! another Bakun) are added to the two parity blocks, as shown in Figure 7 above, and multiple sync blocks are used as the basic unit. Together they make up a video sector. Audio disks, which will be described later, are added to the front and back positions of this video sector, and recording data DA and DB for each channel as shown in FIGS. 8 and 9 are formed. On the other hand, (7) SYNC. In,
4th F. The recording data DA from the cc addition circuit 16A is directly channel-encoded by the channel encoding circuit 18A and taken out from the output terminal 19A, and the recording data DB from the other addition circuit 16B is sent to the delay circuit 17 to adjust the phase of the recording head, which will be described later. Delayed data DD delayed by the difference
After becoming B, it is channel encoded by the channel encoding circuit 18B and taken out from the output terminal 19B. The recording timing signal from the timing generation circuit 33 is
The signal is taken out directly through the output terminal 34A, and through the delay circuit 17 and then through the output terminal 34B. As the basic pulse of this tie-up signal, for example, the segment pulse SP shown in FIG. 9 can be considered. This segment pulse SP is a switching timing pulse for producing the above-mentioned helical track, and is 1/4 of one field in the case of PAL system (l in NTSC system)
It has a period of 1/3 of the field. The recording signal taken out from the output terminal 19A is sent to the recording heads HA and HC of the rotary head device shown in FIG. 10, and the recording signal taken out from the output terminal 19B is sent to the recording head HB.
, is being sent to the HD. Here, the recording heads HA, HB
are arranged at approximately the same position, and the recording heads IIC and HD are arranged at approximately the same position, and these head pairs HA and H
B and head pairs HC and HD are arranged with an angle difference of 180° on a rotating drum 1 rotating in the direction of arrow r, and a magnetic tape 2 is wound around the rotating drum l in an angular range of approximately tso''. and is guided in the direction of arrow t, and one of the heads comes into sliding contact with the magnetic tape 2 every half rotation of the rotating drum 1. From this, the output terminal 19A
The recording signal from the output terminal 19B is switched and sent to the side of the recording head HA, HC that comes into sliding contact with the magnetic tape 2 every half rotation of the rotating drum l, and the recording signal from the output terminal 19B is sent to the side of the recording head HA, HC that comes into sliding contact with the magnetic tape 2. The feed is switched every half rotation of the rotating drum l to the side that comes into sliding contact with the magnetic tape 2. At this time,
Recording heads HA and HB (or recording heads HC and HD
), a pair of helical tracks TA and TB (or TC and TD) are placed on the magnetic tape 2 as shown in FIG.
are recorded at the same timing. Note that in the PAL system, one field of video signals is recorded on four pairs (eight) helical tracks, whereas in the NTSC system, one field of video signals is recorded on four pairs (eight helical tracks).
The field is recorded on three pairs (six) helical tracks. By the way, each recording head HA and HB (or recording heads HC and H
D) cannot be physically placed at the same position, so they are placed with a predetermined angle difference (for example, 4.22 degrees) (and a difference in head height, although not shown). This means that each recording head HA and HB (or IC and H
D) is the drum rotation phase difference, which appears as a deviation in the tape sliding start timing, that is, a deviation in the recording timing. Therefore, for the recording signal of channel 0 supplied to the recording head HA (HC), the recording head H
By delaying the recording signal of channel 1 supplied to B (HD) by a predetermined time corresponding to the drum rotational phase difference, the recording timing shift based on the rotational phase difference of each head is corrected. Next, regarding the audio signal, the sampling frequency is 48 kHz, the sample length is 20 bits, and each audio sector has 240 samples in the PAL system (NTS
In the case of the C system, four channels of audio signals of 266 or 267 samples (hereinafter the numerical values for the NTSC system are shown in parentheses) are supplied to the input terminal 21 in FIG. For this human audio signal Alt, a conversion is performed in the byte conversion circuit 22 such that five words of 8 bits are assigned to the two samples of 20 bits,
In the next AIIX data addition circuit 23, auxiliary AUX data is added to 608 yen per audio sector (
680) bytes of data. The outer ECC adding circuit 24 adds 76 (85
) The block is activated. Next audio shuffle circuit 25
In this example, sector shuffling is performed by writing one sector of the outer parity block to the shuffle memory and then reading it out. Therefore, the data written to the audio shuffle memory is (8+4) x 76 x 4 stomach 3648 (bytes) :PAL( (8+4)xssX 4
-4080 (bytes): NTSC). The audio shuffle circuit 25 outputs each channel 0 at each timing according to the format shown in FIG.
and channel 1 have 4 sectors of audio data ＾υ0
, ^υ1, ^U2, and ^U3 are read out, and the above-mentioned SYNC,
10, sent to inner ECC addition circuits 16A and 16B. Note that each of the audio data ^uO to ^U3 is written twice, and for example, the audio data ^uO and ^U1 in the area sent to the head HA of the recorded data of channel 0 shown in Fig. 9 are written immediately before that. This is the same as the audio data ^UO and AUI in the recorded data of channel l. Therefore, the recording track corresponding to one segment of the audio signal and video signal is as shown in the shaded area in FIG. 11, where the audio data in the four sectors at the top end of the tape is the first copy, and the bottom end is the second copy. [Problem to be Solved by the Invention] By the way, the storage capacity of an actual memory device such as the memory tC is usually a value of 2, and the above sector shuffle circuit 14 is actually implemented using components such as ICs. The amount of memory required to configure is as follows. In other words, the sample data capacity of one video sector is P
37,848 bytes for AL system (34 bytes for NTSC system)
680 bytes (shown in parentheses below), and the two sectors above are 75,696 (69,360) bytes. This is larger than the value of 2'' = 65536, so a memory IC of 21-131072 bytes must be used. Also, the audio shuffle circuit 25
A memory IC is also required, and the above encoder circuit is
When converting to C, connection bins for the video sector shuffle memory and connection pins for the audio shuffle memory are required, resulting in disadvantages such as an increase in the number of pins of the IC package and an increase in size. Furthermore, in the above-mentioned so-called D2 format, the timing of writing/reading data to and from the memory gates ^1 to MB2 in the full circuit l4 during sector transfer is very tight.
Particularly in the case of the above-mentioned PAL system, as it is clear from Fig. 8, there is very little time margin, so if a phase shift occurs between the input video signal and the recording reference signal, for example, the write operation cannot be performed. A situation may occur where the read operation overlaps with the
There is also a risk that normal operation may no longer occur. The present invention has been made to solve these drawbacks, and takes into consideration the capacity of actual devices such as memory ICs and the memory capacity required for shuffling, and is designed to be used as a memory for shuffling video signals. A memory for shuffling audio signals is provided in the same memory device, and
The purpose is to provide a data encoding circuit that can increase the time margin for writing/reading data to/from memory. [Means for Solving the Problems] The data encoding circuit of the present invention encodes an input digital video signal and an input digital audio signal into predetermined numbers of recording blocks (video sectors and audio sectors), respectively.
In a data encoding circuit that shuffles the divided signals to encode each block,
The above problem is solved by providing a memory for shuffling the video signal and a memory for shuffling the audio signal in the memory space of one memory device. [Function] By providing a memory for shuffling video signals and a memory for shuffling audio signals in the same memory device, the circuit structure is simplified and the memory is used when converting the data encoding circuit into an IC. The number of connection pins can be reduced. (Embodiment) FIG. 1 is a block circuit diagram showing a data encoding circuit as an embodiment of the present invention. The data encoding circuit of this embodiment is a so-called D2 format digital VTR.
This is preferable for application to the recording-side encoder circuit of a video table recorder. In FIG. 1, a digital video signal of 1 sample word of 8 bits (1 byte) is supplied to an input terminal 1l. This input video signal v,7 is sent to a line shuffling circuit 12, where valid data within one line is shuffled. In the outer ECC encoder l3, the shuffled valid data is divided into two channels,
That is, after dividing into channel 0 and channel 1,
The data of each channel is divided into six equal parts, a 4-byte outer parity code is added, and the data is sent to sector shuffle circuits 2OA and 20B for each channel. The audio signal ^Dim supplied to the input terminal 21 is
As mentioned above, one sample word is 20 bits, and the byte conversion circuit 22 converts the 20 bits into an 8-bit word, and the next AUX data addition circuit 23 adds auxiliary AIIX data to one sample word. This is 608 (680) bytes of data per audio sector. In the outer ECC addition circuit 24, 4
Seventy-six (85) outer parity blocks with byte outer parity codes added are generated and sent to sector shuffle circuits 2OA and 20B for each channel. In the memory in the sector shuffle circuit 2OA or 20B, for example, as shown in FIG. 2, the sector shuffle memory for the video signal and the sector shuffle memory for the audio signal are provided in the memory space of the same memory device. It is being done. That is, FIG. 2A shows a specific example of the memory space division format in the case of the PAL system, and FIG. 2B shows a specific example of the form of memory space division in the case of the NTSC system. First, if we try to secure 3 sectors as the memory capacity required for the full video signal sector in order to expand the time margin for writing/reading, 37848x 3 = 113544 [＾ite]
:PAL(34680x3=104
040 [byte]: NTSC) or less NT
In the case of the SC method, the number {Iif is shown in parentheses. Also, for sector shuffling of audio signals, if there is a capacity for 2 sectors, there is sufficient margin for writing/reading, so the required memory capacity is 3648X 2 = 7296 [
Byte]: PAL (4080x 2 = 8
160 [bytes]: NTSC).
In order to fit these into a memory device with a capacity of 2 widths, 113544+7296=120840<131072
= 2": PAL (104040+8160=112
200<131072=2”:NTSC”),
It is sufficient to use a memory device of 2"r+4t, that is, 128kli{}.
The memory capacity is the same as that required for 4, and there is no increase in the number of parts. In this way, 128 of the actual memory IC etc.
Within the k-byte memory space, three memory blocks M1 to M3 for sector shuffling of video signals and two memory blocks MAu for sector shuffling of audio signals.
1 and Mau2 can be provided. Next, consideration will be given to the writing/reading timing of such sector shuffle circuits 2OA and 20B to and from the memories. Regarding memory succession, video data and audio data are read out according to the so-called D2 format as shown in FIG. There is no problem even if the video memory and audio memory are integrated.

Next, regarding memory writing, a video data write request and an audio data write request are generated independently in terms of time. However, considering the processing time during one field period, the above-mentioned valid write data of the video signal is 4 sectors in the PAL system (3 sectors in the NTSC system), which is 37848X 4 - 151392 [
Byte] FPAL (34680X 3
=104040 [byte] :NTSC)
Also, the write data for one field of audio signal is 3648X 4 -14592 [bytes]
:PAL(4080X3=12240
[byte]: NTSC), and if the write operation to the memory is performed based on the RF recording frequency, r o = 154.2182/16 = 9.46 [MHz
] :PAL( f eh”12B/16=8 1MH
z]: NTSC) Therefore, the amount of data that can be written during the l field period is 9.46 x 10/50 = 192800 [+G
Light/Feel Fl: PAL (8X10'/
59.94-133466 [Pi}/Feel El
:NTSC) Therefore, from these values, the above frequency f. It is clear that by appropriately allocating time using the clock of , it is possible to obtain sufficient processing time for writing video data and audio data into the integrated memory. In reality, for example, as shown in FIG.
The horizontal period = II1 is divided into a video signal writing period and an audio signal writing period, so that the video data can be written in the first 498 (498) clocks, and the audio data can be written in the next <96 clocks (when not writing). (There are some) ``You just have to control it.'' As for the audio data, it is necessary to stop the data until writing becomes possible, but this can be easily achieved by, for example, controlling successive output in the byte conversion circuit 22. The structure and operation of the circuit shown in FIG. 1 are the same as those of the data encoding circuit shown in FIG. 4 described above, so corresponding parts are denoted by the same reference numerals and a description thereof will be omitted. According to the above configuration, the memory for video sector shuffling and the memory for audio shuffling are allocated and provided within the memory space of the same memory device, which was previously required separately. Audio shuffling memory can be reduced, and this data encoding circuit can be integrated into an IC.
Since external pins for connecting to the audio shuffling memory are not required when converting the audio shuffling memory, the number of pins on the IC pancake can be reduced and the IC can be made smaller. Moreover, according to the embodiment of the present invention, each channel of the video signal has a three-block configuration, each having a memory capacity of three sectors, so that writing (W)/reading (R) of each memory is The time margin is significantly increased and it is possible, for example, to cope with a few lines of deviation in write timing due to the sequence of color fields, as well as phase shifts between the input video signal and the recording reference signal. However, it can sufficiently deal with phase differences of, for example, about ten lines, and the allowable phase shift amount can be expanded. Furthermore, the above-mentioned head pair H
The delay to correct the rotational phase difference between ASHB (or between HC and HD) can be easily realized by shifting the successive output timing from each channel, and the above can be achieved with a simple arrangement.・Compensate for the throat rotational phase difference The delay circuit 17 in FIG.
This eliminates the need for circuit configuration, which greatly simplifies the circuit configuration. It should be noted that the present invention is not limited to the above-mentioned embodiments; for example, the outer ECC encoder l3 for the video signal and the outer ECC encoder 24 for the audio signal may be made common. Further, the memory used for these outer ECC encodings may be provided in the memory space of the same memory device as the memory for sector shuffling. In addition, the memory for video sector shuffling is 4
It may be made up of blocks (4 sectors) or more. It goes without saying that various other changes can be made without departing from the gist of the present invention. [Effects of the Invention] According to the data conversion circuit of the present invention, a video signal shuffling memory and an audio signal shuffling memory are provided in the same memory device within the memory space of the same memory device. The audio shuffling memory that was previously required separately can be reduced. Furthermore, when converting the data encoding circuit into an IC, external pins for connection to the audio shuffling memory are no longer required, so the number of pins on the IC package can be reduced, and the IC can be made smaller. Further, according to the embodiment of the present invention, three blocks (three video sectors) of memory for sector shuffling of video signals are provided.
As a result, the time margin for writing to/reading from the memory is greatly increased, and for example, the allowable phase shift between the input digital signal and the recording reference signal can be greatly expanded. In addition, it is possible to correct discrepancies in recording ties caused by differences in the position of the recording head for each recording channel.
Since the above memories can be used simultaneously, it is not necessary to separately provide a delay memory for correcting the deviation, and the circuit structure can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a schematic configuration of an embodiment of a data encoding circuit according to the present invention, FIG. Figure 3 is a time chart for explaining the memory write operation, Figure 4 is a block circuit diagram showing a conventional example of a data encoding circuit as an encoder circuit provided on the recording side of a digital VTR, and Figure 5 is a diagram of the input video signal. A time chart showing valid data within one line and outer parity blocks, FIG. 6 is a diagram showing channel distribution and segment division of valid data within one field,
FIG. 7 is a diagram showing the arrangement state of sample data in one sector and sync bronch, and FIG. 8 is a diagram showing write/! to each sector memory 17 in the sector shuffle circuit. 5'! FIG. 9 is a time chart showing recording data corresponding to the recording track/socket; FIG. 10 is a schematic plan view of the rotary head device;
FIG. 1 is a schematic front view showing a recording track pattern on a magnetic tape. 11...Video input terminal l2...Line shuffle circuit 13...
...Outer ECC addition circuit 14...Sector shuffling circuit 16A, 16B...SYN
C, TO, inch ECC addition circuit 17...
・Delay circuit 21...Audio input terminal 24...
...Outer ECC addition circuit 25 ...Audio shuffling circuit Ga^1 to MB2 ... Sector memory 31, 33 ...Tie ξ generation circuit

Claims (1)

[Scope of Claims] A data encoding circuit that divides an input digital video signal and an input digital audio signal into a predetermined number of recording blocks, and shuffles the divided signals to encode each block, comprising: A data encoding circuit characterized in that a memory for shuffling the audio signal and a memory for shuffling the audio signal are provided in a memory space of one memory device.