JPH03189621A - Liquid crystal display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field 1 The present invention relates to a method for driving a liquid crystal display device.

[Conventional technology]

Conventionally, when driving a simple matrix type liquid crystal display device, a driving method generally called a voltage averaging method has been used. However, an actual liquid crystal panel is made of scanning/signal electrodes with a non-O resistance, and the liquid crystal layer acts as a dielectric.For this reason, when the liquid crystal panel is driven using the conventional voltage averaging method, the characters and The effective voltage applied to the display dots formed by crossing the scanning electrode and the signal electrode varies depending on the graphic pattern. As a result, the display becomes uneven.

This problem has been known for a long time, and as a countermeasure, for example, a method (hereinafter referred to as the line inversion drive method) of reversing the polarity of the voltage applied to the liquid crystal panel multiple times during one frame was developed in Japanese Patent Application Laid-Open No. No. 62-31825, Kaikai 60-19
No. 195, No. 60-19196, and the like.

Furthermore, the patent application No. 1599, 1983, which the authors proposed earlier,
There is a method for improving display unevenness according to No. 14.

[Problems to be Solved by the Invention] However, the above-mentioned line inversion driving method is effective to some extent in improving display unevenness caused by changes in the optical characteristics of the liquid crystal sandwiched between the liquid crystal panels depending on the frequency component of the applied voltage. However, it does not completely eliminate display unevenness.

Furthermore, the improvement method (hereinafter referred to as the voltage correction method) proposed by the authors in Japanese Patent Application No. 63-1-59914 was able to significantly improve the display unevenness, but the following display unevenness occurred. It turned out that it remained unimproved.

Here, with reference to FIG. 14, the display unevenness that remains even after performing this voltage correction method will be explained. Figure 14 shows the liquid crystal panel l.
This shows the displayed content. This liquid crystal panel 1 has a liquid crystal (not shown) sandwiched between a pair of substrates 2.3, a plurality of scanning electrodes Y1-Y6 are formed horizontally on the substrate 2, and a plurality of signal types tNX1-Y6 are formed vertically on the substrate 3. x6 is formed. and,
The locations where scanning electrodes Y1 to Y6 and signal electrodes X1 to X6 intersect, respectively, become display dots. Here, this liquid crystal panel 1 has 6 x 6 display dots, but this is for the purpose of simplifying the explanation, and normally there are far more display dots.In addition, in the same figure, the hatched display dots are lit. (Hereafter, a display dot that is lit is called a lit dot, and a display dot that is not lit is called a non-lit dot.)
This figure shows the display contents in a checkered pattern. Then, on the left side of the scanning electrode, there is a
In the method for improving display unevenness according to Japanese Patent No. 59914, a voltage is applied to a group of scanning electrodes that changes depending on the display pattern using a voltage correction method for every other display. That is, when the selection shifts from one scan electrode to the next, the voltage is corrected to the non-selection voltage according to the difference between the number of lit dots on one scan electrode and the number of lit dots on the scan electrode to be selected next. The voltage is superimposed. However, in the case of the display content shown in this figure, since the difference I is always O, no correction voltage is applied to the non-selected voltage, and every other signal electrode receives the signal from the upper and lower sides. A voltage waveform is applied. In addition,
Here, it is assumed that the liquid crystal panel 1 performs a so-called positive display when the effective voltage applied to the display dots is thick (or black).

When the display pattern shown in the figure is actually displayed, the signal electrode x1
The display dots created by , x3, and X5 become thinner toward the top, and blacker toward the bottom.

Conversely, the display dots formed by the signal electrodes x2, In other words, the closer a display dot is to the side to which the signal voltage waveform is applied, the smaller the effective voltage actually applied to it is.

As a result of further investigation and research into this display unevenness, we discovered the following.

This will be explained with reference to FIGS. 15(a) to (C).

Figures 15(a) to (c) show the liquid crystal panel 1 in Figure 14.
15-(a) shows the voltage waveform on the signal electrode x3 at the position of the display dot D31 in FIG. 14 with a solid line. The voltage waveform on the signal electrode x2 at the position of the display dot D21 is shown by a dotted line. Here, the solid line waveform and the dotted line waveform are drawn slightly shifted, but this is to make it easier to see, and they actually match.

15-(b) shows the voltage waveform on the signal electrode xl at the position of display dots D21 to D31 in FIG. 14, and FIG. 15-(C) shows the voltage waveform at the position of display dot D31 in FIG. Indicates the difference between the voltage waveform on scanning electrode Yl and the voltage waveform on signal electrode x3, ie.

The waveform of the voltage applied to the display dot D31 is shown by a solid line, and similarly, the waveform shown by the dotted line in FIG. 15-(C) shows the waveform of the voltage applied to the two display dots D21.

The hatched area indicates the difference in voltage applied between the lit dot and the non-lit dot, and is not the voltage difference that causes display unevenness. In the figure, VO, Vl, F2, F3, F
4. F5 indicates voltage. And voltage V5, F3
, VO1V4 as the lighting, non-lighting, selection, non-selection voltage of the first set, voltage 0, F2, F5, Vl as the lighting, non-lighting, selection, non-selection voltage of the second set, 1 selection, non-selection. The selection voltage is applied to the scanning electrode, and the lighting and non-lighting voltages are applied to the signal electrode. (Hereinafter, the voltage waveform applied to the scan electrodes will be referred to as the scan electrode group, and the waveform applied to the signal electrodes will be referred to as the signal voltage waveform.) The first and second voltage sets are switched periodically. In this example, switching occurs after selection voltages are applied to all scan electrodes Y1 to Y6. (This period is called one frame, and is shown as Fl and F2 in the figure.) Here, as shown in FIG. Since the distance between the ends to which the voltage waveform is applied is short, there is almost no attenuation in the voltage waveform, and almost the applied signal voltage waveform is applied as is. However, as shown in Figure 15-(b), the dot 02
Since the distance between the dot D21 and the end to which the signal voltage waveform is applied is long, a signal voltage waveform in which the voltage waveform is greatly attenuated or rounded is applied to the signal electrode N2 at the first position. In other words, attenuation and large rounding occur in the voltage waveform due to the electrical resistance of the signal electrodes X1-X6 and the integration circuit formed by the capacitor using the liquid crystal as a dielectric. Therefore, when the signal electrodes X1, N3, and N5 switch from the lighting (non-lighting) voltage to the non-lighting (lighting voltage) voltage, the signal electrodes
2, when N4 and N6 switch from a lighting (non-lighting) voltage to a non-lighting (lighting voltage) voltage, a larger spike-like noise is generated on the scanning electrode Vl. As a result, the signal electrodes x1, N3, and N5 are switched from the lighting (non-lighting) voltage to the non-lighting (lighting voltage) N voltage, so that the scanning electrode
The spike-like noise generated on l becomes dominant. Therefore, as shown by the solid line waveform in FIG. 15-(C), the effective voltage applied to the display dot D31 becomes small. Then, as shown by the dotted waveform, the effective voltage applied to the display dot D21 increases.

At this time, conversely, the noise generated on the scanning electrode F6 in FIG. The voltage increases.

Here, a general explanation will be provided. First, the n-th scan electrode from the top is called a scan electrode Yn, the m-th signal electrode from the left is called a signal electrode Xm, and the display dot formed by crossing the signal electrode Xm and the scan electrode Yn is called a display dot Dmn. (Hereinafter, unless otherwise specified, it will be referred to as such.) Here, each signal electrode and scanning electrode Yn to which a signal voltage waveform is applied from one end (upper side in Fig. 14) The number of display dots created by scan electrode Yn+1 are both lit dots, bl is the number of non-lighted dots, and the display dots created by scan electrode Yn are lit dots, and scanning electrode Yn+1 The number of display dots formed with scan electrode Yn is a non-lighting dot is 01, the number of display dots formed with scan electrode Yn+1 is a non-lighting dot, and the number of display dots formed with scanning electrode Yn+1 is a lighting dot is di.
In the figure, the number in which the display dots formed by each signal electrode of the signal electrodes to which the signal voltage waveform is applied from ) and the scan electrode Yn, and the display dots formed by the scan electrode Yn+1 are both lit dots is 82, The number where both are non-lighting dots is 62, the display dot formed with scanning electrode Yn is a lighting dot, the number where the display dot forming with scanning electrode Yn+1 is a non-lighting dot is 02, and the display dot forming with scanning electrode Yn is a non-lighting dot. Let d2 be the number of display dots formed with scan electrode Yn+1 that are lit dots.

Also, among the display dots formed by each signal electrode and scanning electrode Yn of the signal electrode to which a signal voltage waveform is applied from one end (the upper side in FIG. 14), the number of lighting dots is N1°8, and the number of non-lighting dots is N1°8. Among the display dots formed with the scanning electrode Yn+1, the number of lit dots is Ml. 8. The number of non-lit dots is M
IOFF, and similarly, the other end (lower side in Figure 14,
), the number of lit dots among the display dots created by each signal electrode and scanning electrode Yn to which a signal voltage waveform is applied is N.
2°8, the number of non-lit dots is N2°F7, the number of lit dots among the display dots made with scan electrode Yn11 is set to N2, ON,
Let the number of non-lit dots be N2°FF.

Then, N los =a 1 +c INl. rr
=bl+d1 MION=al+d1 MIOFF=b1+c1.

Here, the number 11 is 11=cl-di ” N 1 ON M l oH.

Similarly, N20N = a2 + c2 N2 oyr = b2 + d2 M 2011 = a 2 + d 2M2orr
=b2+c2.

Here, the number I2 is I2=c2-d2 =N2°8-N2°8.

And further I (k)=f (k)II 1+f (L-k
) II2 and the function I (k).

Here, f (k) is a function whose value decreases as k increases. What this function f(k) means is that the magnitude of the spike-like noise generated by each signal electrode on the scanning electrode is the same as that of the scanning electrode near the end to which the signal voltage waveform is applied (hereinafter simply referred to as the drive end). The thicker the electrode, the thicker it is.

Further, L is the total number of scanning electrodes. is 1≦≦.

Then, to conclude, from scan electrode Yn to scan electrode Y
When the selection shifts to n+1, the kth scanning electrode Yk
Above, spike-like noise is generated whose size corresponds to the absolute value of the value of the function I (k).

That is, as the value of the function I (k) increases, large noise occurs. The direction in which this noise is generated depends on the sign of the value of the function I (k).

That is, when the direction of the voltage of the spike-like noise corresponding to the value of this function I (k) and the change in the voltage waveform applied to each signal electrode are in phase at the scanning electrode Yk, this signal electrode and the scanning The effective voltage applied to the display dots formed by the electrode Yk becomes smaller and the display becomes lighter, and when the phase is reversed, it becomes larger and becomes darker.

Due to the mechanism described above, display unevenness remains.

Further, with reference to FIGS. 16 and 17, different display unevenness that remains even after performing the voltage correction method will be explained. Figures 16 and 17
The figure is a diagram 0 showing different display contents from the liquid crystal panel 1, and the liquid crystal panel 1 has exactly the same structure as the liquid crystal panel 1 shown in FIG. In FIGS. 16 and 17, scanning electrodes Y1 to
On the left side of Y6 is the patent application submitted by the authors (1986-1).
According to the voltage correction method for display unevenness caused by weft threading, which is one of the methods for improving display unevenness according to No. 59914), a scanning electrode group voltage that changes depending on the display pattern is applied.

In other words, a correction voltage is superimposed on the selected voltage according to the number Z of lighting dots on one scanning electrode to be selected.The display contents of FIGS. 16 and 17 are as follows. This indicates that the image is displayed at a closer position. Therefore, when the displays shown in FIGS. 16 and 17 are performed, exactly the same correction voltage is applied to each scanning electrode Y1 to Y6 of the liquid crystal panel 1 shown in FIGS. 16 and 17.

However, in the case of Fig. 16, the correction voltage is too large, and dark (uneven) display occurs in the lateral direction of the displayed square.On the contrary, in the case of Fig. 17, the correction voltage is too small, and the display unevenness occurs in the lateral direction of the displayed square. Display unevenness due to the drawing remains. In other words, display unevenness that becomes thinner in the lateral direction of the displayed square remains.

This is for each scanning electrode Yl-Y6 that constitutes the liquid crystal panel l.
This is because the resistance of the display dot and the capacitor formed by the display dot form an integrating circuit, and the lit dot forms a capacitor with a larger capacitance than the non-lit dot. In other words, the waveform of the lighted dots located far from the end to which the scanning electrode group is applied (hereinafter simply referred to as the drive end) is not distorted, and the influence thereof is greater than that of the lighted dots located close to the end. For this reason, if a lit dot is located far away, a large distortion will occur.

As a result, if a lighting dot is located far from the driving end of each scan electrode Y1-Y6, the scan electrode group level including the correction voltage becomes dull. This is because the effective voltage applied to the display dots becomes smaller.

Here, to explain it to boat fishing, five scanning electrodes Y1 to Y
For the scan electrode selected among s, this scan electrode and each signal electrode Xi of p signal electrodes X1-xp (
Let the position of the display dot created by i = 1.2..., p) be i, and the degree of weft tension according to the value Z' calculated by z' = Σq (i) *δ (i) i = 1 This causes uneven display.

Here, s and p are the numbers of scanning electrodes and signal electrodes.

Further, the function q(i) is an increasing function that becomes thicker as the variable i becomes larger.

Then, the function δ(i) is i on the selected scanning electrode.
This is a function that becomes 1 when the display dot at the position is lit and becomes 0 when it is not lit.

Therefore, the numerical value Z' is the number of lit dots determined by giving greater weight to lit dots that are farther from the supply end of the scanning electrode.

Therefore.

Z=Σδ (i) The conventional voltage correction method for display unevenness due to weft threading using the numerical value Z determined by i=1 could not completely eliminate the display unevenness.

Display unevenness also occurs due to the mechanism described above. Therefore, display quality has been degraded.

Therefore, the present invention is based on the patent application filed in 1983-15 proposed by the authors.
In the method for improving display unevenness according to No. 9914, that is, in the method of quantitatively extracting the regularity of the display contents and making corrections corresponding to this extraction amount, when calculating the extraction amount, the display position of the display pattern is By considering the positional relationship between the drive end of the scanning electrode or the signal electrode, unevenness in display is further improved, and a liquid crystal display device with improved display quality and easy viewing is provided.

[Means to solve the problem]

That is, the first aspect of the present invention provides a liquid crystal panel in which a scanning electrode group is formed on a pair of substrates sandwiching a liquid crystal layer, and a signal electrode group is formed on the other substrate. and apply a signal voltage waveform to the signal electrode group to display figures and characters, and at least one of the scanning electrode group and the signal voltage is applied to the signal voltage waveform to display figures and characters, and depending on the pattern of figures and letters displayed by the liquid crystal panel. In liquid crystal display devices that change
The position of the figure or character pattern displayed by the liquid crystal panel from the end of the scanning electrode group to which the scanning electrode group is applied, and the position from the end of the signal electrode group to which the signal voltage waveform is applied. The present invention is characterized by comprising means for changing the amount of the correction voltage depending on at least one of the positions.

(2) In the second aspect of the present invention, the amount of the correction voltage is applied to the scanning electrode group or the signal electrode to which a voltage waveform of at least one of the signal voltage waveform and the scanning electrode group on which the correction voltage is superimposed is applied. It is characterized in that it is changed for each electrode in the group.

[Function] With the above configuration, it is possible to supply a correction voltage that takes into consideration the positional relationship between the display position of the character or graphic pattern displayed by the liquid crystal panel and the drive end of the electrode.

Further, the amount of correction voltage can be varied and supplied to each electrode.

[Example 1 Example 1 The following is a detailed explanation using examples. First, an example for dealing with display unevenness that occurs when a checkered pattern is displayed will be described.

As mentioned above, the degree of display unevenness is determined by calculating the difference between the number of lit dots on the selected scan electrode and the number of lit dots on the next selected scan electrode, taking into account the position from the drive side end of the signal electrode. It is determined by adding it up. Therefore, it is sufficient to calculate this addition while operating the liquid crystal display device and perform waveform correction corresponding to the result.A specific embodiment of a liquid crystal display device for performing such correction will be described.

FIG. 1 shows the configuration of this embodiment. In the figure, 101 is a liquid crystal unit, which includes a liquid crystal panel 201 and a scanning electrode drive circuit 205.
and a signal electrode drive circuit 213. 102 is a series of control signals for controlling the operation of the liquid crystal display device, including a latch signal LP, a frame signal FR, a data-in signal DIN,
It consists of an X driver shift clock signal X5CL and others. A data signal 103 is a signal that determines a display pattern. The data signal 103 changes at the rising edge of the signal X5CL, and is taken into the liquid crystal unit lO1 and the voltage waveform correction circuit 104 at the falling edge. 104 is a voltage waveform correction circuit (hereinafter abbreviated as a correction circuit), 105 is a power supply circuit, and 108 is a circuit that generates a clock signal 110 synchronized with the signal LP. 106 is a power supply for two sets of scanning electrodes (hereinafter referred to as Yii source) necessary to drive the scanning electrodes output from the power supply circuit 105; 107 is a signal electrode output from the power supply circuit 105; The power supply for the two sets of signal electrodes required to drive the
), and 109 is a correction signal that determines the amount of correction voltage output by the correction circuit 104. Furthermore, 110 is a signal synchronized with the signal LP output from the frequency dividing circuit 108 (hereinafter referred to as a correction clock).

Here, in FIG. 2, which shows an example of a specific configuration of each component shown in FIG. 1, and FIG. Scan electrodes Y1 to Y6 are formed on one of the pair of sandwiched substrates 202 and 203, and signal electrodes x1 to x6 are formed on the other substrate 203. Here, signal electrodes X1, x3, and X5 have terminals on the upper side that supply signal voltage waveforms, X2, x4, and x6 have terminals on the lower side, and scan electrodes Yl-Y6 and signal electrodes X1-X
6 intersect to form a display dot 204. The liquid crystal panel 201 has a 6×6 dot configuration, but this is for the purpose of simplifying the explanation and is not limited to this. 205 is a scanning electrode drive circuit (hereinafter referred to as Y driver). ), a shift register circuit 206, a shift register circuit 207 in which a register consisting of a plurality of bits shifts simultaneously, a latch circuit 208, and a counter circuit 209.
, a coincidence detection circuit 210 , a switch circuit 211 , and a level shifter circuit 212 . The output of the level shifter circuit 212 is then guided to each scan electrode Yl-Y6 of the liquid crystal panel 201. Here, in Fig. 3, the Y driver 2
In Figure 1, which shows a more detailed example of 05 and provides a detailed explanation of the Y driver, 206 is a shift register circuit that takes in the signal DIN at the falling edge of the signal LP, and sequentially inputs the signal at the falling edge of the signal LP. DIN is transferred into each register of shift register circuit 206. here,
The signal DIN is active at a high potential "H" and is normally output once at intervals of the number of signals LP, which is equal to or greater than the number of scan electrodes Y1 to Y6. Therefore, shift register 2
°1” data passes through 06, otherwise it is inactive °
It becomes “0”. Here, each register outputs the contents of the register as a control signal CO.

Reference numeral 207 denotes a shift register circuit composed of registers each consisting of a plurality of bits, and in this embodiment, one register is composed of 5 bits. This shift register is a Y correction shift clock (hereinafter referred to as
signal YCSCL), and the correction signal 1
An intensity signal (4 bits, IO to I3 in this embodiment) that determines the amount of correction voltage constituting 09 and a code signal F that determines the polarity of the correction voltage are sequentially taken in as a signal YC5CL.

208 is a latch circuit that takes in the contents of the shift register circuit 207 in response to a signal LP.

209 is a counter circuit, which is an up counter having the same number of bits as the number of bits of the intensity signals 0 to 3. This counter 209 is counted up by the correction clock 110 and reset to 0 by the signal LP.

210 is a coincidence detection circuit, and each circuit 210 is a latch circuit 2.
Each corresponding register of 08 and the output of the counter circuit 209 are compared to detect whether they match. That is, when a match occurs, a control signal C2 that becomes active "1" is output.At this time, the contents of the code signal F taken into the register (this is referred to as the control signal C1) indicate that the code signal F is negative. (code signal F is active "1"), then
It is detected whether each bit of the shift register is inverted and the result is equal to the value represented by 1 added to the value. The detection result is held until the next signal LP arrives.

211 is a switch circuit. Ten voltages VO1VltJ, V1, VIL, V2, which constitute the Yli source 106,
Among V3, V4U, V4, V4L, and V5, voltage vO1V
4U, V4, V4L as the first voltage set, voltages V5, VI
L, Vl, VIU are divided into a second set of voltages, and the signal FR
This is a switch circuit that switches to one of these two sets of voltages.

The voltages VO1V4U, V4, and v4L will be referred to as the selection voltage, correction voltage (U), non-selection voltage, and correction voltage (L) of the first voltage set, respectively. In addition, the correction voltage (U
) and (L) are collectively referred to as the correction voltage. Similarly, voltages v5, VIL, Vl, and VIU are the selection voltage, correction voltage (U), non-selection voltage, and correction voltage (L) of the second set of voltages. ).

A level shifter circuit 212 is composed of a plurality of four-circuit one-contact switches.

When the control signal CO is "1", each switch selects Sl. That is, a selection voltage is selected.

Then, the control signal CO is °0", and the control signal C2
When is "1", each switch selects S3. That is, the non-selection voltage is selected.

The control signals CO and 02 are both “0”,
When the control signal C1 is 0'', each switch selects S2, and when CI is 1'', each switch selects S4.

The configuration of the Y driver 205 is as described above. Note that the shift register circuit 207 has a 5-bit configuration for the intensity signals 10 to I3 and the code signal F, but by increasing or decreasing the number of bits of the intensity signal, the number of bits of this shift register circuit 207 can be increased or decreased as appropriate. I don't mind.

The number of registers configuring the shift registers 206 and 207, the number of latch circuits 208, the number of circuits composing the level shifter circuit, and the number of switches configuring the level shifter circuit are as shown in the figure. The number is equal to the number of electrodes Y1 to Y6.

Here, the operation of the Y driver 205 will be explained.

In FIG. 3, the signal DIN is taken into a shift register 206 in synchronization with the signal LP and transferred. As a result, the level shifter circuit 212 sequentially outputs the selected voltage in response to this (hereinafter, the switch that outputs the selected voltage will be referred to as the selected switch, and the switches that output the other voltages will be referred to as unselected switches). Also, in synchronization with this, during one period of the signal LP, the intensity signal l0-I3
, code signal F are taken into the shift register circuit 207 by the signal YCSCL. and.

Each switch whose correction voltage (TJ) or L) is not selected until the absolute value of the numerical value represented by the intensity signals IO to I3 and the numerical value counted up by the counter 209 by the correction clock match. outputs. Here, which of the correction voltages (U) and (L) is output depends on the control signal C1. In other words, the code signal F is °°0
” or “l”.Then, counter circuit 2
09, each unselected switch outputs a non-selection voltage. Therefore, the larger the absolute value of the numerical value represented by the intensity signals IO to I3, the longer the unselected switch outputs the correction voltage. The configuration and operation of the Y driver are as described above.

Here, in FIG. 0, which returns to FIG. 2, 213 is a signal electrode drive circuit (hereinafter referred to as an
It consists of And level shifter circuit 216
The output of is guided to each signal electrode X1-X6 of liquid crystal panel 201.

The shift register circuit 214 determines the display pattern.
The data signal 103 indicating whether the light is lit or not is sent to the signal X5CL.
as a clock (Here, turn on the active
After all the data signals 103 corresponding to the signal electrodes x1 to x6 are taken in, they are taken into the latch circuit 215 by the signal LP.

Then, according to the contents of the latch circuit 215 and the signal FR,
The level shifter circuit outputs a predetermined voltage. That is, four voltages VO, V2, V3 . V5
In (7), voltages v5 and v3 are the first voltage set, 11 voltage ■
0 and v2 are divided into a second set of voltages, and one of these two sets of voltages is selected by signal 1 FR. (Here, the first set of voltages 5 and V3 are called the first set of lighting voltage and non-lighting voltage, respectively, and the second set of voltages 0 and V2 are respectively called the second set of lighting voltage, ), and if the content of the latch circuit 215 is °°l'', the signal FR
Outputs one set of lighting voltage determined by
”, outputs the non-lighting voltage.

The liquid crystal unit 101 has the above configuration.

Therefore, in the liquid crystal unit 101, a selection voltage is sequentially applied to the scanning electrodes Y1 to Y6 in synchronization with the signals DIN and LP, and in synchronization with this, a lighting or non-lighting voltage is applied to the signal electrode x1 in accordance with the display pattern. ~X6 and is displayed on the liquid crystal panel 201. At this time, a correction voltage with a length and polarity corresponding to the intensity signal 0 to ■3 of the correction signal 109 and the code signal F is applied instead of the non-selection voltage to the scan electrodes Y1 to Y6 to which the selection voltage is not applied. .

The liquid crystal unit 101 has the configuration and operation described above.

Next, in FIG. 1, 104 is a correction circuit that connects one scan electrode Yn and the next scan electrode Yn+1 of the liquid crystal panel 201 in FIG.
(r+=1.2,...5.6 However, when n:6, it becomes 1 instead of n+1.)Lighting dot 204 on the top
The number of signal electrodes Xi to X6 is counted in consideration of the distance from the end to which the drive waveform is applied, and from the difference, the intensity signal I
This is a circuit that generates O to ■3 and a code signal F. A specific configuration example is shown in FIG. 4 and will be explained in detail. In Figure 4, 40
1 is a toggle flip-flop circuit (hereinafter referred to as T-F/F), 402U and L are gate circuits, 403.404
is a counter circuit, 405U and L are multiplier generation circuits, 406
U and L are counter circuits, 407U and L are latch circuits, 4
08U and L are arithmetic circuits that perform subtraction, 409U and L are storage elements, 410U and L are latch circuits, 411U and L are arithmetic circuits that perform multiplication, and 412 is an arithmetic circuit that performs addition and division.

Here, the T-F/F circuit 401 is reset by the signal LP and outputs "0", acts as an active input to the gate circuit 402L, acts as an inactive input to the gate 402U, and When the clock starts,
This is reversed. Therefore, when the data signals corresponding to the even-numbered electrodes x2, x4, x6 of the signal electrodes x1 to X6 of the liquid crystal panel 201 in FIG. 2 enter the gate circuits 402U and L in FIG. becomes active and outputs the data signal as it is.Then, the gate circuit 40
The output of 2U is inactive regardless of the data signal. Conversely, when data signals corresponding to the odd-numbered electrodes x1, Then, the output of the gate circuit 402L becomes inactive regardless of the data signal. That is, these three circuits separate data signals for electrodes driven from above and data signals for electrodes driven from below. These separated data signals are the upper data signal,
This is called the lower data signal.

Counters 406U and 406L count the number of "l" states indicating lighting for each of the above-mentioned separated data signals.

That is, when the signal X5CL falls, the gate 402U,
Counters 506U and L add up only when the output of L is active. This addition result (this value is 1M1oH, M2a
− and ) are taken into the latch circuits 407U and 407L, respectively, in synchronization with the signal LP. The value of the latch circuit 407U and L that is about to be taken in (this value is NlO,
, N2. Let it be N. ) and the numerical values M of counters 406U and L
1 The subtraction of each of os and I2゜8 is performed by the calculation circuit 4.
08U.Here, the result of this calculation is I1=N1. N-Ml, N.

I2”N2N20N-+IN.

Here, the counter 403 corresponds to the scanning electrodes Y1-Y6 in FIG.
In this embodiment, the up-counter circuit is capable of representing states as many as 0 to 5, and is reset to 0 by the signal DIN. This counter 40 in FIG.
The output of 3 is a memory element (hereinafter referred to as memory) 409L.
Used as J and L addresses. The value of the address is n-1 when a selection voltage is applied to the scanning electrode Yn of the liquid crystal panel 201 in FIG.

Then, the numbers 11 and I2 mentioned above are stored in the memory 4.
09U and L are written to the address indicated by the counter 403.

To explain the operation specifically, during the period when the selection voltage is applied to the scanning electrode Yn in FIG.
2 Count oN. Then, just before the selection voltage is applied to the scan electrode Yn+1, the latch circuit 408U and L hold the value N1111N+N2on, that is, the number of lit dots on the scan electrode Yn, and calculate the difference 1 and I2,
Write to address n-1 of memory 409U and L, respectively.
This operation is repeated until n reaches 0 or 66 and returns to 0. That is, in memories 409U and L, the difference in the number of lighting dots on scanning electrodes Yl and I2 is stored at address 0.
and 12 are stored respectively.

Scan electrodes Y2 and I3, I3 and I are located at addresses 1 to 5, respectively.
4. Difference in number of lit dots on I4 and I5, I5 and Yl 11
, I2 are stored.

Here, the counter 404 is an up-counter circuit that can represent the states of the scan electrodes Y1 to Y6, and in this embodiment counts up from 0 to 5, and is reset to 0 by the signal LP. The clock input to this counter 404 (this clock is referred to as a signal YC3CL) may be any clock that changes by the number of scan electrodes Yl-Y6 within one period of the signal LP, and in this embodiment, the signal X5C
L is the signal YCSCL. The output of this counter 404 is used as an address for multiplier generation circuits 405U and 405L.

405U and L are circuits that generate multipliers, which are numerical tables made up of read-only memory elements (hereinafter referred to as ROM), diode matrices, etc., and generate the value of a function using the input address as a variable. It is a circuit. That is,
405U is a function table that returns a numerical value f (K) when the address is k.

The function f (k) is a decreasing function whose value decreases as k increases. For example, the form of the function is determined through experiments. Here, to simplify the explanation, we will use a function that changes linearly as follows.

When k = 0, f (0) = 1'5 when = 1, f (1) = 14 when = 2, f (2) = 13 when = 3, f (3) = 12 When = 4, f(4) = 11 When = 5, f'(5) = 10 Similarly, the 1st multiplier generation circuit 405L is a circuit that generates a function that can be defined by f (L-k). . Here, L is the number of scanning electrodes Yl-Y6 minus 1. In this embodiment, L=5.

During the period when the selection voltage is applied to the scanning electrode Yn of the liquid crystal panel 201 in FIG. 2, the arithmetic circuits 411U and 411L that perform the multiplication in FIG. The contents of the memories 409U and L are multiplied by the multiplier generation circuit 405U and L. At this time, the counter 404 is incremented by the signal YCSCL, so the values output by the multiplier generation circuits 405U and L are synchronized with the signal YC3CL. and change. In other words, if λ is
The calculation results of the calculation circuits 41IU and 41L in synchronization with the signal YC3CL are as follows.

f(0)I11. f(5)*l2f(1)III
, f (4) *12f (]III, f(
3) *l2f(3)III, f (2) *l2f
(4) I11. f(1)*l2f(5)III,
f(0)*I2 Then, an arithmetic circuit 4 that adds and divides this result.
Add these two together by 12 and divide the result by 4. If that number is engineering, I= f(0)*11+
f(5)I12)/4I= f(1)*Il+f(4
)*I2)/4I= f (2)*I l+f (3
)*I2)/4I= f(3)*It+f(2)*I
2)/4I= +f (4)*11+f (1)*I2
)/4I= f(5)*Il+f(0)*I2)/4
are sequentially output in synchronization with the signal YC3CL. Here, the reason for dividing by 4 is the shift register circuit 207 in FIG.
Since the signal has a 4-bit structure excluding the code signal F, the numerical value (2) is made to fall within this 4-bit range. Therefore, it is not essential.

Generally speaking, during the period when scan electrode Yn of liquid crystal panel 201 in FIG. 2 is selected, scan electrode Yn and Yn
The difference in the number of lit dots on +1 is 11, and f for each of I2.
After multiplying (n-1) and f (L-n+1), the result of adding these two results is I = f (n-1)
*I 1+F (L-n+1)*I2 as signal YCSC
Sequentially in sync with L.

Output. The magnitude of this result is output as an intensity signal IO to step 3, the sign signal F is the positive/negative sign, and the signal YCSCL is output as a correction signal 109 in FIG. 1. The correction circuit 104 has the configuration and operation described above. Here, this configuration is not limited to this; for example, in FIG. 4, I=f(
n-1)*I 1+F (L-n+1)*I2 to 405
The circuits U, L, 411U, L, and 412 calculate in real time, but they are calculated in advance by a CPU, etc., written to a newly provided memory, and read out sequentially using the outputs of counters 403 and 404 as addresses. , may be output as the correction signal 109.

An example of a specific configuration of the power supply circuit 105 in FIG. 1 is shown in FIG. 5, which shows resistors 501 to 509 connected in series. And a voltage VO1v5 is applied to both ends of it. These resistors 501-509 work as a voltage divider circuit, where the voltages generated in each resistor 501-509 are divided into VOlVIU, Vl, VIL, V2, V3 from above.
, V4U, V4, V4L, V5 and root, V = VO - V 1 = V 1 - V2 = V3 - V4 = V4 - V5, V2 - V3 = a * V, a is a constant of about 1 to 50. Takes a value.

The resistance values of the resistors 501 to 509 are set so that the following four formulas: VIU-V1=V4-V4L, V1-VIL=V4U-V4, hold true.

510 is a voltage stabilizing circuit that lowers only the impedance without changing the voltages generated by the resistors 501-509, and is composed of a voltage follower circuit using an operational amplifier circuit, an emitter follower circuit using transistors, etc. The voltage stabilizing circuit 510 includes resistors 501 to 5 as shown in the figure.
09 is provided for each voltage divided by 09.

The above configuration has the voltage ■0, VIU, Vl, V
IL, V4U, V4, V4L, and V5 are supplied to the liquid crystal unit 101 in FIG. 1 as a Y power supply 106, and voltages VO, V2, ■3, and ■5 as an X power supply.

In FIG. 1, 108 is a circuit that generates a correction clock 110, which generates a clock synchronized with the signal LP.

This clock 110 may be, for example, a signal obtained by dividing or multiplying the signal X5CL, or may be configured by a PLL circuit. The period of this clock may be gradually increased or decreased in synchronization with, for example, the period of this clock, which is determined by experiment. In this embodiment, one period of the signal LP has 16 periods.

The liquid crystal display device shown in FIG. 1 has the above structure.

Here, the operation of this embodiment will be explained in the case where a checkered pattern is actually displayed. FIG. 6 is a diagram showing the display contents displayed by the liquid crystal panel 201 of FIG. 2.

In FIG. 6, hatched display dots indicate lighting, and this display example indicates that a checkered pattern is displayed. When this display is displayed, the present embodiment operates as follows.

First, when Yn is selected among the scanning electrodes Y1 to Y6 of the liquid crystal panel 201 in FIG. 2, the correction circuit 104 in FIG.
The number MloN of display dots that are lit among the display dots formed by i, X3, and I5, and the signal electrodes x2 and I4 whose driving ends are below.
, the number M of lit display dots created by I6
Count 2°8 separately.

Immediately before scan electrode Yn+1 is selected next, this counted value and a signal indicating that scan electrode Yn and the drive end are on top, which were held in latch circuits 407U and 407L shown in FIG. Number N of display dots that are lit among the display dots formed by electrodes XI, I3, and I5 10. and signal electrodes X2, I4 . whose driving ends are below. The difference between the number of lit display dots created by I6 and N2°8 is 11. I
2 is calculated as 11=N1ON-Ml, , l2=N2°, -M2°, and the memory 409
Write to address n-1 of U and L, where n is 1 to 5.
．． Repeats from 5 to 1. Therefore, the memories 409U and L have differentials 1 and I for all scanning electrodes Yl to Y6.
2 is written. In the case of the display shown in Fig. 6, the memory 4
09U has -2, 2, -2, 2, - in order from address 0 to 5.
2, 2 are written in the memory 409L, and 2, -2 are written in the memory 409L in order.
．． 2, -2.2, -2 are written.

In parallel with the write operation to this memory 409U and L, the value 11 and I2 at address n-1 of this memory 409U and L are (f (k-1) * 11 + f (+1 to L-) II2
)/4 is performed sequentially on =1.2, . . . 6, and the results are sequentially transferred to the shift register circuit 207 in the Y driver shown in FIG.

Here, for example, when n = 3, the above calculation is performed with the memory 409U at address n-1 = 2 and the value of L -2, 2 as numerical value 11, L2.
Immediately before ``n+1'' is selected next, the shift register circuit 207 contains I= (f (0)II t+f) from above.
(5) Water I2)/4=15* (-2)+lO*2)/
4 #-3 I= (f (1)*11+f (4)II2)/4=
14* (-2)2+11*2 #-2 I= (f (2)*r l+t (3) II2)
/4=13* (-2)+12*2)/4 square-1 1= (f (3)*Il+f (2)II2)/
4=12* (-2)2+13*2 # l I= (f (4)II l+f (t)II2>/
4=11* (-2)+14*2)/4#2 i= (f (5)II 1+f (0)II2
)/4=10*(-2)2-15*2 43 is taken in. Here, each numerical value I is rounded off to the nearest whole number.

Then, when the signal LP falls and scan electrode Yn+1 is selected, these values are taken into the latch circuit 208. At the same time, the counter 209 is reset to zero. Thereafter, the correction clock 110 counts up.

Here, since n=3, the selected scan electrode Yn+1 becomes the scan electrode Y4, so the switches of the level shifter circuit 212 are 34 from the top (correction voltage (L)), S2 (correction voltage (U)), S4 (correction voltage (L)), Si selection voltage), S4 (correction voltage (L)), S2 (correction voltage (U))
, and select each scan electrode Y of the liquid crystal panel 201.
Output to 1 to Y6.

And each switch selecting S2 to S4 is
The number of correction clocks 110 indicated by the corresponding latch circuits 208 is input to the counter 209, and the counter 2
This state is maintained until the outputs of 09 match the numbers indicated by the corresponding latch circuits 208. If they match, each switch selects S3 (non-selection voltage) and outputs it. In other words, either the correction voltage (Ll) or (L) is selected depending on whether the numerical value I is positive or negative; the larger the absolute value of the numerical value, the longer the correction voltage will be selected in place of the non-selected voltage. .

In this way, the scanning electrodes Y1 to Y of the liquid crystal panel 201
6 is supplied with voltage.

At this time, each signal electrode
If the display dots produced by X1-X6 are lit, apply one lighting voltage, and if they are not lit, apply one non-lighting voltage to each signal electrode X1-
The X driver 213 operates to supply the signal to X6.

The liquid crystal display device of this embodiment operates as described above. Here, the voltage waveforms applied to the scanning electrodes Yl-Y6 and the signal electrodes Xl-X6 of the liquid crystal panel 201 when performing the display shown in FIG. 6 are shown in FIGS. The operation will be explained in detail. Fig. 7(a) is Fig. 6;
Position of display dots D31, D51 Teno signal electrodes x3, x
The voltage waveform of No. 5 is shown by a solid line, and the display dot D21.041
The voltage waveforms of the signal electrodes x2 and x4 at the positions are shown by broken lines. In FIG. 3B, the voltage waveform applied to the scanning electrode Yl is shown by a solid line, and the waveform disturbance that is about to occur at the position of the display dot D31 of the scanning electrode Y1 is shown by a broken line. Similarly, the figure (c) shows the voltage waveform applied to the scan electrode Yl and the waveform disturbance that is about to occur at the position of the display dot D32, and the figure (d) shows the voltage waveform applied to the scan electrode Yl. (e) shows the voltage waveform applied to the scanning electrode Y1 and the waveform disturbance that is about to occur at the position of display dot D34. Figure (f) shows the disturbance of the voltage waveform applied to the working electrode Y1 at the position of the display dot D35, and Figure (g) shows the voltage waveform applied to the scanning electrode Y1 at the position of the display dot D35. The waveform disturbance that is about to occur at the position D36 is shown by a solid line and a broken line, respectively. From FIGS. 7(a) to 7(g), it is clear that the influence of the change in voltage waveform shown by the solid line in FIG.
2, Y3, and scan electrodes Y1, Y2, . It can be seen that waveform disturbances are about to occur on Y3 depending on the magnitude of the influence. Similarly, scanning electrode Y6. Y5. It can be seen that Y4 is affected by changes in the voltage waveforms of the signal electrodes x2 and x4 to which signal voltage waveforms are supplied from below, and corresponding waveform disturbances are about to occur. However, in the same figure (b) ~ (
As can be seen from the waveform shown by the solid line in g), each scanning electrode Y1
In response to the waveform disturbance that is about to occur at ~Y6, the Y driver 205 in FIG.
Alternatively, (L) is output instead of the non-select voltage. The output time increases or decreases depending on the magnitude of the waveform disturbance that is to occur in each of the scanning electrodes Yl to Y6. That is, for large disturbances, a correction voltage is supplied for a long time, for small disturbances, a correction voltage is supplied for a short time, and then a non-selection voltage is supplied.

Therefore, the waveform disturbances that would occur in each of the scan electrodes Yl-Y6 are substantially canceled. As a result, there is no difference in the effective voltage applied to each display dot on the liquid crystal panel 201, and the display error is eliminated.

As mentioned above, when calculating the difference in the number of lit dots on one selected scan electrode and the next selected scan electrode, the position of one display pattern and the end of the drive voltage waveform is taken into account. Furthermore, display unevenness can be eliminated by varying the amount of correction voltage applied to each scanning electrode based on this difference.

Embodiment 2 In Embodiment 1, a liquid crystal panel was described in which the signal electrodes alternately supply signal voltage waveforms from above and below, but it is of course effective even when the signal voltage is supplied from one side. think. The gate circuit 402U always sends a signal that is “1” instead of the output of the T-F/F 401 in FIG.
(This applies to each circuit 402L, 402L.
This means the same as making 06L to 410L inactive. Therefore, these circuits become unnecessary.

Additionally, the circuit 405L is also no longer needed, and the circuit 412 can be simplified as the input from 411L is always O.) As a result, the numerical value I becomes I= (I 1+l2)If (k). Calculated.

By performing the same operation as in the first embodiment based on this numerical value (■), the same effect can be obtained.

Embodiment 3 Furthermore, in Embodiment 1.2, a liquid crystal panel was described in which a signal voltage waveform is supplied only from one side of the signal electrode, but the effect can be obtained even when the signal voltage waveform is supplied from both ends of the signal electrode.

That is, in Example 1, when calculating the numerical value I, the function f (
k) by the function g (I k-L/2 l ), where the function g (x) is.

It is an increasing function that increases as the numerical value X increases.

By performing the same operation as in the first embodiment based on this numerical engineering, the same effect can be obtained.

In Examples 1 to 3, the method of adjusting the correction amount is to keep the voltage difference between the correction voltage and the non-selection voltage constant and increase or decrease the time during which the correction voltage is applied (hereinafter, this will be referred to as time axis correction). ), but it is also possible to fix the time for which the correction voltage is applied and vary the difference between the correction voltage and the non-selection voltage (this is called voltage axis correction). It is also possible to change both the applied time and voltage (this is called time-voltage axis correction).Also, it is possible to change both the applied time and voltage (this is called time-voltage axis correction). Embodiment 4 In which the waveform may be used as a correction voltage (this is referred to as function waveform correction) Next, an example for dealing with display unevenness due to weft stringing will be described.

As described above, for one scan electrode selected among the scan electrodes Yl-Ys, this scan electrode and each signal electrode Xp
Let p be the position of the display dot created by (p = 1.2..., r), and the degree of weft according to the numerical value Z' calculated by z' = Σq (i) *δ (i) i = 1. Unevenness in display occurs due to scratches. In other words, the effective voltage applied to the display dots on the scanning electrodes becomes smaller in accordance with this numerical value Z'. Therefore, it is sufficient to calculate the numerical value Z' while operating the liquid crystal display device and perform correction according to this numerical value Z'.This will be explained using a specific example of the configuration.

FIG. 8 shows the configuration of this embodiment.
03 is the same control signal and data signal as in FIG. 1, so the same number is given and the explanation will be omitted. 801 is a liquid crystal unit, which includes the liquid crystal panel 201 and the scanning electrode drive port 18.
805 and a signal electrode drive circuit 213. 804 is a voltage waveform correction circuit (hereinafter abbreviated as correction circuit), which is expressed by Equation 4.
1! Z' is calculated and a correction signal 809 that is active for a length of time corresponding to this value is created. 805 is a power supply circuit. 806 is a power supply for two sets of scan electrodes (consisting of a selection voltage and a non-selection voltage, hereinafter referred to as Y power supply) necessary to drive the scan electrodes output from the power supply circuit 805; , the power supply circuit 805 receives the correction signal 80
Y power supply 8 with different voltages when 9 is active and inactive
06 selection voltage. 106 is a power supply circuit 80
This is the power supply for the two sets of signal electrodes (hereinafter referred to as
This is the same as the xti source 107 in the figure. Further, 809 is a correction signal that determines the amount of correction voltage output from the correction circuit 804.

Here, in FIG. 9 showing an example of a specific configuration of each component in FIG. 8 and FIG. 9 showing an example of a specific configuration of a liquid crystal unit 801, 201 is a liquid crystal panel; is the same as Reference numeral 805 denotes a scanning electrode drive circuit (hereinafter referred to as Y driver), which is composed of a shift register circuit 206, a switch circuit 911, and a level shifter circuit 912. The output of the level shifter circuit 912 is then guided to each scan electrode Y1 to Y6 of the liquid crystal panel 201. The shift register circuit 206 is the same as in the first embodiment, and its explanation will be omitted. The switch circuit 911 selects one voltage set from the two voltage sets of the Y power supply 806 output from the power supply circuit 804 in FIG. 8 in accordance with the signal FR. That is, the four voltages VO', Vl, ■4, V5' (7
), voltage ■0', V4 is the first voltage set, voltage V5
This is a switch circuit that divides V1 into a second set of voltages and switches to one of these two sets of voltages using a signal FR. Here, the voltages VO' and V4 are respectively set to the first
The set of voltages will be called the selection voltage and the non-selection voltage.

Similarly, the voltages V5' and Vl are referred to as selection voltages and non-selection voltages of the second voltage set.
One of the voltages in the set is supplied to level shifter circuit 912.

A level shifter circuit 912 is composed of a plurality of two-circuit one-contact switches, and is switched depending on the contents of the shift register 20G.

That is, when the content is °°l'', each switch selects the selection voltage, and each corresponding scan 11t
Output to pole Yl-Y6.

When "O", each switch selects a non-selection voltage and outputs it to each corresponding scan electrode Yl-Y6.

The configuration of the Y driver 905 is as described above. Here, the operation of the Y driver 905 will be explained. Signal DIN
is taken into the shift register 206 and transferred in synchronization with the signal LP. As a result, one of the level shifter circuits 912
Correspondingly, one switch sequentially outputs a selection voltage, and the remaining switches output a non-selection voltage.

The configuration and operation of the Y driver are as described above. 2
13 is a signal electrode drive circuit (hereinafter referred to as X driver)
is the same as in Example 1, so the explanation will be omitted.

The liquid crystal unit 801 has the above configuration.

Therefore, in the liquid crystal unit 801, a selection voltage is sequentially applied to the scanning electrodes Yl-Y6 in synchronization with the signals DIN and LP, and in synchronization with this, a lighting or non-lighting voltage is applied to the signal electrode x1 in accordance with the display pattern. ~x6 and is displayed on the liquid crystal panel 201.

The liquid crystal unit 801 performs the above operations.

Next, in FIG. 8, 804 is a correction circuit, and the scanning electrode Y1-Y
Regarding the scan electrode selected next among the scan electrodes 6, the position of the display dot created by this scan electrode and each signal electrode Xp (p=1°2..., 6) is p, and z'=Σq (i) *δ
(i) ...Equation (1) is calculated, and when the scanning electrode to be selected next is selected, the active correction signal 809 is synchronized with the signal LP by the length corresponding to the value Z'. This is a circuit that outputs A specific configuration example is shown in FIG. 10 and will be explained in detail. In FIG. 10, 1001 is a counter, 1002 is a constant generation circuit, 1003 is a gate circuit that performs the logical product of each of a plurality of output signals representing the numerical value output from the constant generation circuit 1002 and the data signal 103;
04 is an arithmetic circuit that performs addition; 1005 is an arithmetic circuit 10
First latch circuit 1006 that holds the operation result of 05
1007 is a second latch circuit, and 1007 is a correction signal generation circuit (hereinafter abbreviated as generation circuit) that generates a correction signal 809 that is active for a time corresponding to the content of the second latch circuit in synchronization with the signal LP. .

The counter circuit 1001 is a counter that is reset to 0 by the signal LP and counts up by the signal X5CL. The output of this counter 1001 is supplied to a constant generation circuit 1002.

The constant generation circuit 1002 is constituted by a ROM, a diode matrix, etc., and outputs different numerical values according to the output of the counter circuit 1001. That is, as the numerical value output by the counter circuit 1001 increases, the counter circuit 1001 outputs a correspondingly large numerical value. This is the function q of equation (1)
This corresponds to (i). Here, i is the value output by the counter circuit 1001 plus 1.

The value of the function may be determined by experiment, etc. (in this embodiment, it is simply as follows.

When i=1, q (1) = 1 When 1=2, q (2) = 1. When 1i=3,
q(3)=1.2 When 1=4, q(4)=1.3 When i==5, q(5)=1.4 When i=6,
q (6) = 1.5 The gate circuit 1003 generates an AND between the numerical value output from the constant generation circuit 1002 and the data signal 103.

That is, when a certain signal X5CL falls, if the data signal is active "1", the value of the constant generation circuit 1002 is output as is, and if it is inactive "0", 0 is output. This corresponds to q (i) *δ(i) in equation (1). Here, i is the number of times the signal X5CL falls after the falling of the signal LP, and the counter 100
It is equal to the output value of 1 plus 1.

1004 is an arithmetic circuit that adds the numerical value output from the gate circuit and the contents of the first latch circuit 1005 in synchronization with the signal X5CL, and returns the result to the first latch circuit 1005.

1005 and 1006 are first and second latch circuits;
The latch circuit holds the result of the arithmetic circuit 1004. The first latch circuit 1005 is reset to 0 by the signal LP. This latch circuit 100 on the verge of being reset
The content of 5 corresponds to the numerical value Z' in equation (1): z'=Σq (i) *δ(i) . . . That is, the number of lit dots on the next selected scanning electrode is weighted according to the position of the lit dot and counted.

Then, just before the first latch circuit is reset, this content is transmitted to the second latch circuit 1 at the falling edge of the signal LP.
Incorporated into 006. Here, since the next scan electrode is selected at the fall of the signal LP, the numerical value indicated by the second latch circuit 1006 indicates the weighted number of lighting dots on the selected scan electrode.

1007 outputs a correction signal 809 that is active "L" for a length of time corresponding to the value indicated by the second latch circuit 1006 as a signal L.
This is a generation circuit that outputs in synchronization with P.

For example, this circuit 1007 receives the signal X5CL as it is,
Alternatively, an oscillation circuit 1008 that generates a frequency-divided or multiplied clock (hereinafter referred to as a correction clock), a counter circuit 1009 that counts up by this correction clock and resets to 0 by a signal LP, and this counter circuit 1009 This can be easily realized using the coincidence detection circuit 101O which generates an active signal until the numerical value indicated by the output of the second latch circuit matches the numerical value indicated by the second latch circuit. Here, the periods of the correction clocks do not need to be at regular intervals and are determined by experiment, for example.

Since the correction circuit is configured as described above, it weights and counts the number of lit dots on the scan electrode to be selected next, and activates the dot for a length corresponding to the number Z'. A correction signal 809 is outputted in synchronization with the signal LP when the next selected scan electrode is selected.

Next, the power supply circuit 805 in FIG. 8 will be explained with reference to FIG. 11. FIG. 11 is a diagram showing an example of a specific configuration of the power supply circuit 805, in which 1101-1107 are resistors connected in series. And voltages VOU and V5L are applied to both ends thereof. These resistors 1101-1107 act as a voltage divider circuit, where each resistor 1101-1107
From the top, the voltages generated are vou, vo, ■1, V2, V
3, V4, V5. Assuming V5L, V=VO-Vl=V1-V2=V3-V4=V4-V5, V2-V3=a*V, where a is a constant and takes a value of about 1 to 50.

VOU-VO=V5-V5L, each resistor 1 lo1~1107 is set so that the following three formulas hold true.
The resistance value is set.

Reference numeral 510 is the same as the voltage stabilizing circuit 510 of the first embodiment, and a description thereof will be omitted.

1108 and 1109 are switch circuits, which select the voltage VOU when the correction signal 809 is active "1", and select the voltage VO when the correction signal 809 is inactive "0".
Similarly, let the selected voltage be voltage VO'.
The switch 1109 selects the voltage V5L when the correction signal 809 is active "1", and selects the voltage V5 when the correction signal 809 is inactive "0".

Then, the voltage selected in 5 is set as voltage V5'.
Here, the voltages VOU and V5L are referred to as correction voltages.

The above configuration has voltages VO', V4, V5'
, Vl as Y power supply 106, voltage ■0, v2, V3, v5
is supplied to the liquid crystal unit 801 in FIG. 8 as an X power source.

The liquid crystal display device shown in FIG. 8 has the above structure.

Here, the operation of this embodiment will be explained in the case where a rectangle is actually displayed. FIGS. 12 and 13 are diagrams showing display contents displayed by the liquid crystal panel 201 of FIG. 9. In Figures 12 and 13, hatched display dots represent lighting, and in this display example, congruent rectangles are displayed with left and right sides, respectively, in Figures 12 and 13. I'm glad you're here. When this display is displayed, the present embodiment operates as follows.

First, when displaying as shown in FIG. 12 or 13, the correction circuit 804 in FIG. Counting is weighted according to the position of the lit dot. That is, the numerical value Z' is determined. Here, each scanning electrode Yl-
The numerical value Z'' for Y6 is as follows.

When the display shown in Figure 12 is performed, Scanning electrode Y1... z’　=o+o+o+o+o+.

=0 Scanning electrode Y2...Z' =1.0*l+1.1*1+0+0+0+0=2
．． 1 Scanning electrode Y3... z'=l, 0*1+1.1*1+O+O+O+0=2.
1 Scanning electrode Y4...Z'=1.0*1+1. t*t+o+o+o+.

=2.1 Scanning electrode Y5...Z' =1. O*l+1. 1*1+O+O+O
+0=2.1 Scanning electrode Y6... z' =o+o+o+o+o+.

20 When displaying as shown in Fig. 13, scanning electrode Y1... z' =O+O+O+O+O+0 =0 scanning electrode Y2... Z'==O+O+0+O+1.4*1+1.5*1=2
．． 9 Scanning electrode Y3... Z' =O+O+O+O+1.4*1+1.5*1=2
．． 9 Scanning electrode Y4...Z' =O+O+O+O+1.4*1+1.5*1=2
．． 9 Scanning electrode Y5... Z' =O+O+O+O+1. 4*l+1. 5*1
=2.9 Scanning electrode Y6...Z'=O+O+O+0+o+0 =0 Then, the correction circuit 804 in FIG. 8 outputs the active correction signal 809 for a period of time corresponding to the numerical value 2'.

The power supply circuit 805 uses the correction voltage V instead of the voltage vO1V50 as a selection voltage only while the correction signal 809 is active.
Outputs OU and V5L.

Here, scanning electrodes Y2 to Y when the display is shown in FIG.
The numerical value Z' for 5 is smaller than that when the display is shown in FIG. 13. Therefore, when the display is shown in FIG.
The time during which V5L is applied as a selection voltage is shorter than when the display shown in FIG. 13 is used. The Y driver 905 in FIG.
sequentially applies a selection voltage to each scanning electrode Y1 to Y6 of the liquid crystal panel 201.

The operation of the X driver 213 is the same as in the first embodiment, so a description thereof will be omitted.

In order to perform the above operation, as shown in the display example shown in FIG. In order to prevent waveform rounding from occurring too greatly, a selection voltage with a small amount of correction voltage is supplied to the selected scan electrode. That is, the correction voltage VO1J,
A voltage to which V5L is applied for a short time is supplied as a selection voltage instead of voltages VO and V5. On the other hand, as shown in the display example of FIG. 13, when the lighting dots are far from the driving ends of the scanning electrodes Y2 to Y5, the voltage waveform on the scanning electrodes is rounded. In response to a larger amount of correction voltage being generated, a selection voltage with a larger amount of correction voltage is supplied to the selected scan electrode. That is, a voltage to which the correction voltages VOU and V5L are applied for a long time instead of the voltages VO and V5 is supplied as the selection voltage. Therefore, when counting the number of lighted dots on each scanning electrode, the position of the lighted dots can be approximately corrected by the position shown in FIGS. 12 and 13. The results are calculated by weighting and counting, and from this result,
Display unevenness can be eliminated by changing the selection voltage supplied to each scan electrode.

Embodiment 5 Furthermore, in Embodiment 4, a liquid crystal panel was described in which the scan electrode group was supplied from only one side of the scan electrodes, but the effect can be obtained even when the scan electrodes are supplied from both ends. That is, in Example 4, when calculating the numerical value Z', the function q(i) is converted into the function p (!i
-3/21), where the function p (x) is a decreasing function that decreases as the value X increases.

The same effect as in the fourth embodiment can be obtained by performing the same operation as in the fourth embodiment based on this numerical value Z'.

In the fourth embodiment, as a method of adjusting the correction amount, the difference between the voltages VOU and VO and the difference between the voltages v5 and v5 are kept constant,
A method of increasing/decreasing the time during which voltages VOU and V5L are applied as selection voltages, that is, time axis correction was used, but voltage axis correction, time-voltage axis correction, and function waveform correction methods may also be used.

Further, since Examples 1 to 2.3 change the non-selection voltage, and Examples 4 to 5 change the selection voltage, for example, the methods of correcting display unevenness according to Example 1 and Example 4 can be performed at the same time. Needless to say.

[Effects of the Invention] As described above, according to the present invention, when extracting a rule included in a figure or character displayed on a liquid crystal display device, the drive voltage waveform of each electrode of the liquid crystal panel and the figure or character are extracted. The conventional display unevenness can be significantly improved by extracting the voltage in consideration of the positional relationship with the end supplying the voltage and changing at least one of the scan electrode group height and the signal voltage waveform based on this.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the device configuration of a first embodiment of the liquid crystal display device of the present invention. FIG. 2 is a diagram showing the configuration of a liquid crystal unit. FIG. 3 is a diagram showing the configuration of a scanning electrode drive circuit. FIG. 4 is a block diagram showing the configuration of a voltage waveform correction circuit (correction circuit). FIG. 5 is a diagram showing the configuration of the power supply circuit. FIG. 6 is a perspective view of a liquid crystal panel showing an example of display contents. FIGS. 7(a) and 7(g) are voltage waveform diagrams applied to the liquid crystal panel when performing the display shown in FIG. 6. FIG. 8 is a diagram showing the device configuration of a fourth embodiment of the liquid crystal display device of the present invention. FIG. 9 is a diagram showing the configuration of the liquid crystal unit. FIG. 10 is a block diagram showing the configuration of the correction circuit. FIG. 11 is a diagram showing the configuration of a power supply circuit. FIG. 12 is a perspective view of a liquid crystal panel showing another example of display contents. FIG. 13 is a perspective view of a liquid crystal panel showing another example of display contents. FIG. 14 is a perspective view of a liquid crystal panel showing an example of display contents in the prior art. FIGS. 15(a) to 15(c) are voltage waveform diagrams actually applied to the liquid crystal panel when the display shown in FIG. 14 is performed. FIG. 16 is a perspective view of a liquid crystal panel showing another example of display contents. FIG. 17 is a perspective view of a liquid crystal panel showing another example of display contents. Liquid crystal unit control signal data signal voltage waveform correction circuit (correction circuit) Power supply circuit Y power supply 106. 107 ・ 108 ・ 101, 801 102 ・ ・ ・ ・ 103 ・ ・ ・ ・ 104, 804 805 ・ 806 ・ 110...More than clock signal

Claims (2)

[Claims] (1) A scanning electrode group is formed on one of a pair of substrates sandwiching a liquid crystal layer, and a signal electrode group is formed on the other substrate, and a scanning electrode is applied to at least one end of the scanning electrode group. A signal voltage waveform is applied to at least one end of the signal electrode group to display a figure or character, and the scanning voltage waveform and the In a liquid crystal display device having a means for superimposing a correction voltage on at least one of the signal voltage waveforms, an end of the scanning electrode group to which the scanning voltage waveform is applied, of a figure or character pattern displayed by the liquid crystal panel. A liquid crystal display device comprising means for changing the amount of the correction voltage according to at least one of a position from the end of the signal electrode group and a position from an end of the signal electrode group to which the signal voltage waveform is applied. (2) The amount of the correction voltage is changed for each electrode of the scanning electrode group or the signal electrode group to which at least one voltage waveform of the scanning voltage waveform and the signal voltage waveform on which the correction voltage is superimposed is applied. The liquid crystal display device according to claim 1, characterized in that: