JPH03188530A - Program prefetching device - Google Patents

Abstract

PURPOSE:To efficiently execute plural tasks in parallel time division by recognizing execution states of plural tasks to prefetch instruction program data. CONSTITUTION:An instruction program prefetch control part 3 successively recognizes the execution states of tasks outputted from a task switching control part 2 to discriminate the task executed at present and the task to be next executed and generates control signals 11 to 13. Instruction program data is read out from a program storage area 6 by the signal 13, and a prefetch queue A5a or B5b is determined as the storage destination of this data by a data distributing circuit 15. A multiplexer B4b determines the prefetch queue A5a or B5b, from which data is sent to an instruction decoder 7 or the like, by the signal 12. Since two prefetch queues are provided and are dynamically switched in this manner, an efficient instruction program is executed with the small circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a system controlled using a microprocessor, etc., in which two or more tasks (works) are executed in a time-sharing manner by one microprocessor, etc. This invention relates to an instruction program prefetching device for increasing execution efficiency and speed.

BACKGROUND ART When a task is executed using a microprocessor, a program counter, a stack pointer, etc. are required for one microprocessor.

A set of register files consisting of general-purpose registers and the like is prepared, and the instruction program at the address indicated by the program counter is read from the program storage area and the instruction is executed. In this case, the program data for the next instruction is read after all currently executed instructions have been completed, resulting in a large amount of time loss. Therefore, many microprocessors improve their execution efficiency by controlling the reading of the next instruction program data during instruction execution, that is, by prefetching the instruction program.

In this case, when looking at the program execution state locally, only one task is being executed, and the instruction programs are normally lined up in order, so the next instruction program data can be easily read in advance. However, in recent control systems, some programs have to be controlled by simultaneously executing multiple tasks, even if the program execution state is viewed locally. Therefore, microprocessors that can execute up to two tasks completely in parallel in time division have also appeared. This microprocessor has two register files, and by switching a multiplexer in accordance with instructions from a program, switches the register files and realizes time-sharing parallel execution of two tasks. In this way, one register file is prepared for one task, so task switching can be performed at high speed. In this case, the execution state of the program is often such that the task is switched for each instruction and two tasks are executed in a manner similar to upward parallel processing. When performing instruction prefetching to improve program execution efficiency, it is necessary to have an instruction prefetching device for each task. In this case, by using two systems of instruction prefetching devices, it is possible to recognize the status of other tasks. This enables high-speed execution by pre-fetching instructions. However, when the number of tasks to be executed in parallel increases, it is necessary to implement instruction prefetching devices corresponding to the number of tasks, resulting in a problem that the circuit size increases. In this case, if there is only one system of instruction prefetching device, the next instruction of the current task will be in the instruction prefetching device when the current task executes the current instruction, but the next instruction to be actually executed will be of the next task. Since it is a command, it is necessary to throw away the data stored in the command prefetching device and read a new command, which results in a time loss.

In order to solve such problems, multiple register files are prepared for one microprocessor, etc., and the multiplexer is switched according to instructions from the microprocessor (program), and the multiple register files are sequentially switched. In systems that execute multiple tasks in parallel in a time-sharing manner, to increase instruction execution efficiency,
It is necessary to provide two or more systems of instruction prefetching devices, provide a function to recognize the task to be executed next, and provide a function to efficiently prefetch instructions by sequentially switching the relationship between the instruction prefetching device and the task.

Problems to be Solved by the Invention As described above, conventionally, when multiple tasks are executed by one microprocessor, if the instruction prefetching device is
Even if there was a system, the instruction prefetch data would become invalid every time the task was switched, and it would be necessary to prefetch the instructions again. Further, in order to improve instruction execution efficiency, if one system of instruction prefetching device is provided for each task, the logic circuit scale becomes large and difficult to realize.

The present invention solves the conventional problems by providing two systems of instruction prefetching devices and switching the instruction prefetching devices each time a plurality of tasks are switched, thereby making it possible to first capture the instruction to be executed by the next task. It is something.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention adds a function to the function of controlling time-division parallel execution of multiple tasks to recognize the execution task of the next instruction in advance, and uses the information Based on 2
The instruction program prefetching devices in the system are sequentially switched to perform efficient instruction prefetching operations.

By doing this, when performing time-division parallel execution control of multiple tasks using multiple register files, it is possible to minimize the waiting time for reading instruction program data, and high-speed and highly efficient execution is possible. Even if there are multiple tasks to be executed in parallel, by recognizing the execution status of the tasks, the instruction program prefetching device can be implemented by implementing only two systems, allowing efficient control without increasing the circuit scale.

Embodiment An embodiment of the present invention will be described in detail using the block diagram shown in FIG. In the example, N register files 1a to 1n
, and performs N time-division parallel executions.

One of register files A-N (la to in) is selected from among register files 1a to 1n by multiplexer A4a and connected to path 9. The multiplexer A4a selects the register file to be used by the execution task via the signal line 10 by the task switching 41112 that performs part of the control of time-division parallel execution.
control through. Connected to the bus 9 are functional circuits 8 necessary for microprocessor processing, such as control and arithmetic processing functions, and conventional microprocessor control is performed. The instruction program prefetching device performs instruction program prefetching control3. Multiplexer B4b, prefetch key, a-
It is constituted by A, B11, 5b% data distribution circuit 15. The instruction program prefetch control 3 sequentially recognizes the execution status of the tasks output from the task switching control 2, determines the currently executed task and the task to be executed next, and creates control signals 11, 12, and 13. An outline of the control will be described. The instruction program data is read from the program storage area 6 by the signal 13 created by the instruction program prefetch control 3, and the data distribution circuit 15 transfers the read instruction program data to the prefetch queue A5a.
or the brief fetch queue B5b. The multiplexer B4b uses the signal 12 to determine which data from the brief fetch queues A5a and B5b is to be sent to the instruction decoder 7, etc.

Next, we will describe the operation during time-sharing parallel execution of multi-tasks. For simplicity, consider executing three tasks.

The register files used are la, lb, and lc, and multitask execution is performed in a mode in which tasks are switched for each machine language instruction. In other words, when one instruction related to register file 1a is executed, next one instruction related to register file 1b is executed, then one instruction related to register file IC is executed, then an instruction related to register file 1a is executed, and so on. Consider a mode in which the register file changes automatically. Currently, register file 1
Consider the case where an instruction related to a is given. Assume that the brief fetch key x-A5a is used for this task. In a typical microprocessor, if there is free space in the briefetch queue, data is read from the program storage area, and this operation continues until the briefetch queue is filled. When the brief fetch queue is filled, data reading operations from the program storage area are stopped until it becomes empty.

In the present invention, at this timing, when the data read operation is stopped, the execution of the next task is analyzed in advance,
In this case, the instruction data regarding the register file 1b is read from the program storage area 6, the data distribution circuit 15 is switched, and the brief fetch key -B5
Import the data into b. At this time, this operation does not occur if the brief fetch queue is not filled when the instruction regarding the register file 1a is executed. When the instruction related to the register file 1a is completed, the register file is switched from 1a to 1b, and the brief fetch queue is also switched from A5a to B5b. At this time, since there is a possibility that the instruction program data is stored in the brief fetch queue B5b, the instruction can be executed without waiting for instruction data to be read. Also, if the briefetch keys a-B5b are filled during the execution of this instruction, the data of the instruction related to the register file IC is read in advance and stored in the briefetch queue A5a which is not currently in use, as before. This eliminates loss when switching tasks. When the instruction related to the register file IC is executed using the brief fetch queue A5a, if the brief fetch queue is filled, the instruction data related to the register file 1a to be executed next is read in advance and sent to the brief fetch key -B 5 b. Store. In this way, by providing two systems of brief fetch queues and dynamically changing them, it is possible to efficiently execute an instruction program with a small circuit scale.

As described in detail, according to the present invention, it is possible to perform time-division parallel execution of multiple tasks with high efficiency with a simple and small control circuit scale, and to achieve high-speed execution that could not be controlled with a microcomputer or the like until now. It becomes possible to realize control by executing multi-tasks.

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment of the program prefetching device of the present invention. 1a-ln...Register file A-N, 2.
...Task switching control, 3...Instruction program preemption control s 4a, 4b...Multiplexer A. B, 5a, 5b...Brifuetsuchiki, -A, B
, 6...Program storage area, 7...
Instruction decoder, etc., 8... Control, arithmetic processing functions, etc., 9... System path, 10.11
．． 12.13.14... Control signal line, 15...
...Data distribution circuit.

Claims (1)

[Claims] In a device such as a single microprocessor that has multiple register files (program counter, stack pointer, general-purpose registers, etc.) and performs parallel execution of time-sharing multitasking using hardware, prefetching instruction program data can be performed by multiple tasks. A program prefetching device that recognizes the execution state of a program.