JPH0318745B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, and particularly to a dynamic memory device that uses a capacitor as a means for storing information.

Metal-insulator-semiconductor field-effect transistor (MISFET) memory, so-called MOS (Metal-
Oxide−Semiconductor) represented by FET
MOS memory is widely used from the viewpoint of high integration and low cost because it is easy to utilize the dynamic memory effect of capacitors and stray capacitance.
Among MOS memories, the one that has recently received the most attention is the so-called 1Trs/cell memory (hereinafter referred to as 1-element memory), which uses one pair of MOSFET and capacitor for each bit. One-element memory has the disadvantage that the readout level of stored information is low, but since the number of constituent elements per one bit is small, the area occupied by one bit can be essentially reduced as the readout circuit is made more sensitive. It has the advantage of being able to

While working to improve the readout level of single-element memories, the present inventors found that the information retention period of memory cells placed at the ends of a memory cell array was 1/2 to 1/10 that of the center. I found that the ratio is getting shorter. If the information retention period is short, the rewriting or refresh cycle of stored information must be increased, which imposes a large usage restriction on the entire memory system.

The main object of the present invention is to lengthen the information retention time of a dynamic storage device that utilizes the information retention effect of a capacitor or stray capacitance.

Another object of the present invention is to provide a dynamic storage device that has a simple configuration and can extend information retention time.

According to the present invention, a capacitor in which a semiconductor portion of a main surface of a semiconductor substrate of one conductivity type is used as one electrode, and a conductor layer formed on an insulating film covering the semiconductor portion forming the one electrode is used as the other electrode. and a MISFET connected in series to the capacitor, within a predetermined region of the main surface of the semiconductor substrate,
The memory cell mat is provided with a plurality of memory cells arranged in rows and columns, and the memory cell mat is formed corresponding to the plurality of memory cells arranged in rows and columns. a plurality of data lines arranged to transmit information signals;
a plurality of word lines arranged to transmit control signals to gate electrodes of MISFETs of the plurality of memory cells, respectively; is formed on the main surface of the semiconductor substrate outside the region, and the memory
a semiconductor region of an opposite conductivity type to the semiconductor substrate extending along and adjacent to the semiconductor portions of the memory cell capacitors in the outermost row or column of the cell mat; an oxide layer thinner than a thick oxide layer formed between the semiconductor region and the semiconductor portion of the capacitor in the outermost row or column is formed on the region, and the semiconductor region is held at a fixed potential. It is characterized by being made to connect to.

The semiconductor region having the elongated thin oxide layer described above acts to prevent leakage of the charge stored in the storage capacitor at the end of the memory cell mat, contributing to an improvement in information retention time. This makes it possible to bring the information retention time of the storage capacitors placed at the ends of the memory cell mat closer to the information retention time of the storage capacitors placed in the center of the memory cell mat. .

The present invention and other objects thereof will become more apparent from the following description with reference to the drawings.

In storage devices that utilize charge retention effects such as capacitors and stray capacitances, the charge stored in the capacitors inevitably leaks through various routes.
Therefore, since information can only be held temporarily, this type of storage device is called a dynamic storage device.

Possible causes of charge leakage in a one-element memory cell include leakage at the source-drain junction of a switching MISFET, leakage caused by activation of a parasitic circuit element, and leakage at the capacitor itself. The inventor of the present invention has analyzed the phenomenon of the reduction in information retention time of memory cells at the end of the memory mat, taking into consideration the above-mentioned factors, and has determined that the most significant cause seems to be leakage in the capacitor itself. Ta.

In the memory cell row at the center of the memory mat, other memory cell rows are arranged immediately adjacent to each other, but of course, at the ends of the memory mat, other memory cell rows are arranged immediately next to each other. Unlikely, and other circuit groups are often placed at a considerable distance. Therefore, the thin oxide region or the recess in the thick oxide film of the capacitor section at the end of the memory mat is larger than the other thin oxide region (the recess in the thick oxide film) compared to that at the center. placed apart. When the spacing between the thin oxide regions is large like this, that is, when the width of the thick oxide film located between the thin oxide films is large, large stress is exerted on the semiconductor substrate surface at the boundary between the thin oxide film and the thick oxide film. it is conceivable that. In particular, when the substrate surface is selectively thermally oxidized to form a thick oxide film, the stress is thought to become even greater. When such stress acts on the substrate surface, crystal defects occur, and heavy metals such as gold, silver, copper, and lead are likely to be trapped by the crystal defects. It is thought that the trap effect caused by such crystal defects or crystal defects increases the leakage current in the nearby PN junction or in the channel region induced by applying an electric field, especially the latter induced leakage current. The impact on channels is thought to be even greater.

In other words, in conventional memory devices, when a thick oxide film with a wide width is formed adjacent to the edge of a memory cell mat, stress acts on the substrate surface.
Many crystal defects occur on the substrate surface around the memory cell mat. Due to these crystal defects, more fractional carriers are likely to be generated, and these fractional carriers flow into the semiconductor region that constitutes the memory cell capacitor at the end of the memory cell mat. It is thought that this reduces the information retention time of the capacitor at the end of the mat.

There are still many aspects of semiconductor surface phenomena that are not yet understood, and it is not possible to definitively determine the cause of the above-mentioned problems, but the information retention time at the edge of the memory mat is reduced compared to a thin thermal oxide film. This is thought to be due to the surface effect of the substrate at the boundary of the thick thermal oxide film with a wide range of areas.

Based on this idea, the present inventors developed a memory cell array or memory cell mat.
Along near the ends of MCA ₁ to _{MCA 4} , recesses (thin oxide layer sequences) THIN1 to THIN8, which were drilled in the thick oxide film as shown by diagonal lines in FIG. 1, were arranged. Regarding the left end of memory cell mat MCA ₁ ,
For comparison, a thin oxide layer sequence in the -y direction from the 0 point.
Although THIN1 is placed, no measures are taken in the +y direction. This memory cell mat
When we measured the information retention time _tS of the memory cell row at the left end of MCA ₁ , we found that the memory cell information retention time _tS where no measures were taken was 40 to 50 (as shown in Figure 2). msec), whereas the information retention time _tS of the memory cell with the thin oxide film array THIN1 placed nearby is 80 to 100 (msec).
This was accompanied by an improvement of about twice as much.

The present invention seeks to develop these improvements further and to extend the information retention time of memory cells at the ends of the memory cell mat.

The present invention will be explained below with reference to FIGS. 3 to 6.

FIG. 3 shows a circuit diagram of a dynamic memory device using a one-element memory cell to which the present invention is applied.

In Figure 3, a 1-bit memory cell is 1
It consists of several MISFETM _S and a capacitor C _s . The capacitor C _S has the function of holding information, and the MISFETM _S becomes conductive when writing or reading information or refreshing, and connects the capacitor C _S and the data line.
Selectively connect with DL.

The preamplifier is for reading out the information stored in the selected memory cell, and it reads out the information stored in the memory cell by comparing it with the readout level of a dummy cell connected to the opposite data line. It is determined whether the logic is "1" or "0".

The main amplifier is used to amplify the output of the preamplifier to speed up data readout. M ₁ , M ₂ select data lines DL ₃ , DL ₄ . . . according to the contents of address signals a ₈ to a ₁₃ in the Y direction. PC ₁ is used to charge the stray capacitance of data lines DL ₁ and DL ₂ on the opposite side prior to cell selection, and MISFET M ₃ and M ₄ are symmetrical with data lines DL ₃ and DL ₄ on the opposite side. In order to have
It is added corresponding to MISFET M ₁ and M ₂ .

Next, the structure of the memory cell column and its surroundings will be explained with reference to the plan view of FIG. 4 and the cross-sectional views of FIGS. 5 and 6.

In FIG. 4, M is a MISFET, C is a capacitor, and a 1-bit memory cell is, for example,
Consists of MISFET M ₂₆ and capacitor C ₂₆ . W is a word line, and during writing, reading, or reading, MISFETs in columns connected to the selected word line become conductive.
For example, if word line W ₂ is selected,
MISFETs M ₁₂ , M ₂₂ , M ₃₂ ... become conductive.

The structure of the memory cell may be better understood with reference to the cross-sectional view of FIG. FIG. 5 is a sectional view taken along line V-V in the plan view of FIG. 4 as a cutting line. In the figure, 1 is a P-type Si substrate. Reference numeral 2 denotes a thick Si oxide film, which is formed by selectively thermally oxidizing the Si substrate 1 using a Si ₃ N ₄ film or the like as a mask, and has a thickness of, for example, 1 μm. 3
is a thin Si oxide film formed by lightly thermally oxidizing the Si substrate 1 after removing the Si ₃ N ₄ film used as a selective oxidation mask, and its thickness is
700-3000Å. 4 is polycrystalline Si, which is structurally used as gate electrodes, capacitor electrodes, and wiring layers, and a thin Si oxide film 3 is used in the process.
used as an etching mask and a diffusion mask. This use of polycrystalline Si is called a Si gate MOS integrated circuit, and is well known to those skilled in the art.

The thick Si oxide film 2 is formed on almost the entire surface of the substrate except for the areas where circuit elements such as MISFETs and capacitors are to be formed, and this area is often used as a wiring area.

Reference numeral 5 denotes a region doped with an N-type impurity such as phosphorus, which is used as a source/drain region or a wiring layer of the MISFET. N-type region 5 is formed, for example, by diffusing phosphorus using thick oxide film 2 and polycrystalline Si layer 4 as a mask. This diffusion is often performed in an oxidizing atmosphere, and in this case, a thin thermal oxide film is formed on the substrate surface of the diffusion layer 5, although not shown. In this example, the diffusion region 5 in the THIN region shown in FIG. 6 and the diffusion region used as the wiring layer are formed prior to the growth of polycrystalline Si, and the diffusion region which becomes the source/drain region and its extension wiring is formed prior to the growth of polycrystalline Si. is formed using polycrystalline Si as a mask after growth. 6 is a phosphorus glass film doped with phosphorus ( _P2O5 - _SiO2 ), which is formed by chemical vapor deposition at a low _temperature . The phosphorus glass film 6 is useful as a passivation to stabilize the characteristics of MISFET and the like, and as an insulating layer between layers in multilayer wiring. 7 is an Al film.

Reference numeral 8 indicates the end of the thick oxide film 2, which corresponds to the shaded boundary line in the plan view of FIG. In addition, in FIG. 4, ○ marks are used to electrically connect the polycrystalline Si layer 4 and the Al layer 7, the polycrystalline Si layer 4 and the diffusion layer 5, and the diffusion layer 5 and the Al layer 7. These are so-called contact holes provided in which the respective electrical connections are made.

Returning to Figure 5 again, the memory cell is
It consists of MISFET M ₂₆ and capacitor C ₂₆ . Capacitor C ₂₆ has a thin oxide film 3 as a dielectric, and a polycrystalline Si layer 4 and the surface of a Si substrate as both electrodes.
Consists of MIS capacity. The dielectric 3 is made thin to obtain a large capacitance value. V _DD in polycrystalline Si layer 4
A fixed voltage is applied, which causes the substrate surface to
N connected to the source and drain of MISFET M ₂₆
A channel layer 9 of the type is induced. Therefore, one electrode of the capacitor _C26 is connected to the source and drain of the MISFET _M26 , and charging and discharging operations for the capacitor _C26 are performed through the MISFET _M26 . The N-type channel layer 9 is used to electrically isolate one electrode of the capacitor from the P-type substrate, but an N-type diffusion layer can also be used instead of the channel layer 9 of the capacitor C ₂₆ . In this case, it is necessary to form a diffusion layer prior to forming the polycrystalline Si layer 4.

In FIG. 4, memory cells are regularly arranged in rows and columns along word lines W and data lines DL. A collection of such arrays constitutes a memory mat MCA as shown in FIG. The memory cell row at the end of the memory mat MCA, i.e. the word row in FIG.
Capacitors C ₂₁ , C ₃₁ , connected to lines W ₁ , W ₂ ,
The information retention time of C _{41 .} . . and C ₁₂ , C ₂₂ , C ₃₂ . According to the present invention, the THIN area indicated by diagonal lines is provided to lengthen the information retention time at this end. As is clear from FIG. ₆ , which is a cross-sectional view taken along the - line in _FIG . arranged along the immediate vicinity of

In this THIN region, an N-type semiconductor region 5 having a conductivity type opposite to that of the region 1 is formed.
Furthermore, a very thin thermal oxide film formed during the diffusion is formed on this semiconductor region.
This semiconductor region 5 is electrically connected to a polycrystalline silicon power supply wiring V _DD (see FIG. 4) through a contact hole provided in a thin oxide film. That is, the THIN region is formed by diffusing impurities of a conductivity type opposite to that of the semiconductor substrate into a hole or recess provided in the thick oxide film 2.

This recess in the THIN region allows the capacitor to
The width of the thick oxide film 2 located on the left side of C ₃₁ becomes narrower, and the width of the thick oxide film 2 located on the left side of capacitor C ₃₁ becomes smaller.
It is thought that the stress applied to the channel layer 9 is reduced and the leakage current in the channel layer 9 is reduced. Furthermore, in this case, since the N-type diffusion region 5 is formed in the THIN region, the leakage current can be further reduced by connecting this diffusion region 5 to the fixed potential V _DD . One reason for this is that by fixing this diffusion region 5 to the V _DD potential (+ potential), free electrons moving as carriers are transferred to the capacitor.
This is thought to be because the free electrons are attracted to the diffusion region 5 rather than C ₃₁ and the potential reduction effect of the capacitor C ₃₁ due to the induction of free electrons into the capacitor C ₃₁ can be weakened. That is, the semiconductor region 5 absorbs undesirable minority carriers flowing into the end of the memory cell mat from outside the mat, thereby preventing leakage of information (charge) stored in the capacitor _C31 . be able to. This allows the memory cells in the center of the memory cell mat and the memory cells at the ends of the memory cell mat to
Information retention time in cells can be balanced.

In order to eliminate the limitations on the use of memory systems due to the reduced information retention time of memory cells at the edges of the memory mat, or to relax those limitations to a practical extent, it is necessary to The distance between the recess of the thick oxide film 8 in the memory cell (C ₃₁ ) is set as the distance between the memory cell (C ₃₁ and
C ₃₃ ) is preferably equal to or smaller than that of C 33 ).

The above discussion has focused on leakage current in a capacitor, but even when the wiring layer of a capacitor is configured with a diffusion region, leakage current in the diffusion region may also become a problem. Further, as seen in the memory cell of this embodiment, even when the source/drain region of the MISFET is connected to a capacitor, leakage current at the source/drain junction may become a problem. In such a case, it is considered that the leakage current can be reduced by similarly arranging the recessed part THIN of the thick oxide film near the corresponding part. For example, in Figure 4, by providing THIN, capacitor C ₂₂
Not only the leakage current in the Q part of
It is considered that the leakage current in the P portion of the source and drain of MISFET _M22 can also be reduced.

Although the present invention has been described above with reference to embodiments, the present invention is not limited to these embodiments, and various modifications can be made based on the above-mentioned technical idea.

INDUSTRIAL APPLICABILITY The present invention is extremely effective as a means for balancing the accumulation time of charges stored in storage capacitors arranged at the center and ends of a memory cell mat, and is useful for dynamic storage using memory cells. It can have the greatest effect on the device.

[Brief explanation of the drawing]

FIG. 1 is a plan view for schematically explaining the arrangement of a dynamic storage device considered by the present inventor, and FIG. 2 is a diagram showing the information retention time of a memory cell for explaining the effects of the present invention. The characteristic diagrams and FIGS. 3 to 6 are diagrams for explaining the dynamic storage device of the present invention, in which FIG. 3 is a circuit diagram thereof, FIG. 4 is a plan view, and FIGS. FIG. 4 is a sectional view taken along lines - and - in FIG. 4; MCA...Memory cell array (Matsuto),
PAA...Pre-amplifier array, MAA...main amplifier array, THIN...recess provided in thick thermal oxide film, DL...data line, W
...Word line, M...MISFET, C...
Capacitor, 1... P-type Si semiconductor substrate, 2... Thick Si thermal oxide film, 3... Thin Si thermal oxide film, 4... Polycrystalline Si layer, 5... N-type diffusion region, 6... Phosphorous glass Layer 7... Al film, 8... End (edge) of thick thermal oxide film 2, 9... N-type induced channel.

Claims (1)

[Scope of Claims] 1. A memory cell mat including a plurality of memory cells formed in rows and columns so as to occupy a predetermined area on the main surface of a semiconductor substrate, wherein the memory cells occupy a predetermined area on the main surface of the semiconductor substrate. The memory cell mat has a plurality of word lines formed corresponding to the plurality of memory cells, and a MISFET connected in series to the capacitor. and a main surface of the semiconductor substrate outside the memory cell mat in a dynamic memory device comprising a plurality of data lines formed corresponding to the plurality of memory cells and connected to preamplifiers outside the memory cell mat. , a region of the semiconductor substrate where a thick thermal oxide film is not formed, or a region with a film thickness greater than the thick thermal oxide film, which is disposed along and close to at least one edge of the memory cell mat. A semiconductor region having a conductivity type opposite to that of the semiconductor substrate is formed in the semiconductor substrate under the thin thermal oxidation film region of the semiconductor substrate, and a constant potential is applied to the semiconductor region in the direction of absorbing minority carriers. A dynamic storage device characterized by giving. 2. The edge of the memory cell mat has a concave-convex boundary according to the arrangement form of capacitor semiconductor parts arranged along the edge, and the semiconductor region of the opposite conductivity type has a concave-convex boundary of the memory cell mat. 2. The dynamic storage device according to claim 1, wherein the dynamic storage device has a protruding area at a boundary portion of the dynamic storage device. 3. The semiconductor region formed along at least one end of the memory cell mat and close to the end is comprised of a plurality of semiconductor region groups arranged so as to be separated from each other. A dynamic storage device according to any one of claims 1 to 2. 4. A patent claim characterized in that the semiconductor region formed along and close to at least one end of the memory cell mat is composed of a plurality of semiconductor regions having uneven boundaries. Dynamic storage device according to item 3. 5. A memory cell mat including a plurality of memory cells formed in rows and columns so as to occupy a predetermined area on the main surface of the semiconductor substrate, wherein the memory cells occupy a part of the semiconductor portion of the main surface of the semiconductor substrate. The memory cell mat has an information storage capacitor serving as an electrode or a connection wiring, and a MISFET connected in series to the capacitor, and the memory cell mat has a plurality of word lines formed corresponding to the plurality of memory cells and a plurality of memory cells. In a dynamic memory device formed corresponding to the memory cell and having a plurality of data lines for writing and reading information to and from the memory cells, the memory cell mats occupying the predetermined area are connected to a pair of opposing memory cells. and is arranged along a pair of opposing ends of the memory cell mat on the main surface of the semiconductor substrate outside the memory cell mat, and in close proximity to each of the two ends. The semiconductor substrate has a region where the thick thermal oxide film is not formed or a region of the semiconductor substrate where the thick thermal oxide film is thinner than the thick thermal oxide film. What is claimed is: 1. A dynamic memory device characterized by forming semiconductor regions of opposite conductivity type, and applying a potential to the semiconductor regions in a direction that absorbs minority carriers. 6. Each end of the memory cell mat has an uneven boundary according to the arrangement form of the capacitor semiconductor portions arranged along the end, and each of the semiconductor regions of the opposite conductivity type is connected to the memory cell mat. 6. The dynamic storage device according to claim 5, wherein the cell mat has a protruding area at the concave boundary. 7. Claims 5 to 7, wherein the predetermined area of the memory cell mat has a substantially rectangular shape, and the pair of end portions correspond to a pair of long sides of the rectangular shape. A dynamic storage device according to any one of clauses 6 to 6. 8. A patent claim characterized in that the semiconductor region formed along and close to each end of the memory cell mat is composed of a plurality of semiconductor region groups arranged and separated from each other. A dynamic storage device according to any one of items 5 to 7. 9. Claims characterized in that the semiconductor region formed along and close to each end of the memory cell mat is comprised of a plurality of semiconductor regions having uneven boundaries. 9. Dynamic storage device according to claim 8. 10 First spaced apart main surface of semiconductor substrate
and a second memory cell mat each having a plurality of memory cells formed in rows and columns so as to occupy a second predetermined area, the memory cells forming a part of the main surface of the semiconductor substrate. It has an information storage capacitor whose semiconductor portion is used as an electrode or connection wiring, and a MISFET connected in series to the capacitor, and each memory cell mat has a plurality of words formed corresponding to the plurality of memory cells. In the dynamic memory device, the dynamic memory device comprises a plurality of data lines formed corresponding to the plurality of memory cells and connected to a preamplifier outside the memory cell mat. disposed along and close to two opposing ends of the first and second memory cell mats on the main surface of the semiconductor substrate between them;
The semiconductor substrate has a region where a thick thermal oxide film is not formed, or a region of the semiconductor substrate where the thermal oxide film is thinner than the thick thermal oxide film, and the semiconductor substrate under the region has a region opposite to the semiconductor substrate. A conductive type semiconductor region is formed, a peripheral circuit is formed in association with the memory cell mat between the two rows of semiconductor regions, and a constant potential is applied to the semiconductor region in a direction to absorb minority carriers. A dynamic storage device characterized by: 11 The end of each of the memory cell mats has an uneven boundary according to the arrangement form of the capacitor semiconductor portions arranged along the end, and the semiconductor region of the opposite conductivity type is connected to the memory cell mat. 11. The dynamic storage device according to claim 10, wherein the dynamic storage device has a protruding area at a concave boundary. 12 Along the edge of each memory cell mat,
Claims 10 to 11 are characterized in that the semiconductor region of opposite conductivity type formed close to the end thereof is composed of a plurality of semiconductor region groups arranged and separated from each other. A dynamic storage device described in any one of the following. 13 Along the edge of each memory cell mat,
13. The dynamic memory according to claim 12, wherein the opposite conductivity type semiconductor region formed close to the end thereof is composed of a plurality of semiconductor regions having uneven boundaries. Device.