JPH03187095A - Multiport memory controller - Google Patents

Abstract

PURPOSE:To improve the operating ratio of a multiprocessor system by providing an address coincidence detecting means and an address change detecting means and preferentially processing the access from the access port which first designates and address. CONSTITUTION:An A port address change detecting circuit 22 of an address contention arbitrating circuit detects the change of the address signal inputted from an A port block. A, B port address change detecting circuit 23 detects the change of the address signal inputted from a B port block, and an A and B port address coincidence detecting circuit 21 detects the coincidence between A and B port addresses. In the case of simultaneous access from A and B port blocks, a preferential port discriminating circuit 24 gives a signal in the low level to the latter access and gives a signal in the high level to the first access. Even in case of just simultaneity, the circuit 24 outputs the signal which indicates pending/approval of access. Thus, the read/write operation from each access port is correctly performed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multiport memory control device, and in particular,
The present invention relates to a multiport memory control device that controls the timing of access to multiport memory from a plurality of access ports.

[Conventional technology] In recent years, there has been a growing demand for more sophisticated functions and performance in information processing systems, and there has been an increasing trend to implement the functions required for the entire system using multiprocessor systems that incorporate functional distribution. ing. this is,
A plurality of MPUs (microprocessor units) are incorporated into one system, and a subsystem is formed for each MPU to improve the operating rate of the system. Along with this, there is an increasing demand for the multi-port memory having a plurality of access ports for information transmission between MPUs.

FIG. 5 is a configuration diagram of a multiprocessor system incorporating two MPUs. Referring to FIG. 5, this multiprocessor system includes two MPUA62 and MPUA62.
RAM (Random Access Memory) A2B, ROM controlled by U[166 and one MPUA62
(Read-only memory) A64. and I10 controller A65, and RAMa 67, ROMa 68. which are controlled by the other MPU, 66. and I10 controller B69.

In this multiprocessor system, the MPUA
62 and the above-mentioned series of functional units controlled thereby (RAM^63.ROM^64゜I10 controller A
35), the MPUa 66, and the series of functional units (RAMI 1167, ROM
a68. I10 controller B69) via pass line A70 and pass line B71, respectively.
It is connected to a common memory (hereinafter referred to as shared memory) 61. Pass line A70 and pass line B71 are independent from each other. As the shared memory 61, the aforementioned multiport memory is used. In other words, the shared memory 61 is connected to the MPUA 62 and the path line A7 between the MPUA 62 and the MPUA 62.
an access route A (not shown) for transmitting and receiving signals with a series of functional units connected via the MPU 66;
It is a multi-port memory including a series of functional units coupled to the MPU 1166 via a path line B71, and an access port B (not shown) for transmitting and receiving signals.

FIG. 6 is a schematic block diagram showing the configuration of a two-bottom RAM, which is the most common multiport memory. Referring to FIG. 6, the two-point RAM is configured such that a single shared memory cell array 11 can be accessed from both of two access ports A and B.

Specifically, this 2-bot RAM consists of a memory cell array 11 and a shared memory cell array 11.
It includes functional blocks 100 and 200 of the same configuration for writing/reading data to/from. The functional block 100 exchanges data with the shared memory cell array 11 via one access port A, and the functional block 200 exchanges data with the shared memory cell 11 via the other access port B. Hereinafter, functional blocks 100 and 200 will be referred to as A port block and B port block, respectively.

The shared memory cell array 11 includes a memory cell array composed of memory cells arranged in a matrix, a word line provided corresponding to one direction of each row of the memory cell array, and a word line corresponding to each column direction of the memory cell array. and a bit line provided as a bit line.

The A boat block 100 has human output data l10o (A) to I10, (A) of n+1 bits (n is a natural number).
an I10 buffer (A) 12 having an I10 port (not shown) that receives the data, and n+1 bits of parallel data Ao (A) to Ao specifying the address of a memory cell to be selected in the shared memory cell array 11.
an address buffer 13 having n+1 address ports (not shown) receiving (A) as an address signal;
It includes a row decoder (A) 14 and a column decoder 15.

The front 5 I10 port and the address port are one access port A of this 2-bot RAM.

The address signal input to the address port is applied to row decoder 14 and column decoder 15 via address buffer 13. The row decoder 14 decodes the address signal from the address buffer 13 and selects the word line in the shared memory cell 11 that corresponds to the row address indicated by the address signal. On the other hand, the column decoder 15 decodes the address signal from the address buffer 13 and selects the bit line in the shared memory cell array 11 that corresponds to the column address indicated by the address signal. As a result, the memory cell located at the intersection of the corresponding word line and bit line becomes selected. When the A port block 100 is in a write mode in which data can be written to the shared memory cell array 11, write data is input to the I10 port of the I10 buffer 12. The manually entered write data is provided to the column decoder 15 via the I10 buffer 12.

Column decoder 15 writes the write data into the memory cell selected by row decoder 14 and column decoder 15 in response to an address signal from the address port of address buffer 13.

Conversely, when the A port block 100 is in a read mode in which data can be read from the shared memory cell array 11, the column decoder 15 selects the memory cell (row decoder 14) corresponding to the address signal from the address port A.
and memory cells selected by column decoder 15)
, the stored data is read out, and this successive data is stored in I1.
0 buffer 12. The I10 buffer 12 outputs successive data from the column decoder 15 to the outside via the I10 port.

The B port block 200, like the A boat block 100, has n+1 bits of human output data l10o (B
) to I10n (B) and an I10 buffer 16 having n+1 I10 ports receiving n+1 bit address signals Ao (B) to A.

(B); an address buffer 17 having n+1 address ports receiving (B);
a row decoder 18 and a column decoder 19 that select a memory cell corresponding to the address indicated by the address signal;
When the B boat block 200 is in read mode, data read from the corresponding memory cell is output to the outside, and when this B boat block 200 is in write mode, data to be written to the corresponding memory cell. and an I10 buffer 16 that takes in the data from the outside.

The I10 port of I10 buffer 16 and the address port of address buffer 17 are the other access port B of this two-point RAM.

In addition, in FIG. 6, the alphabetical character in 0 written at the end of the name of each functional unit indicates which of the access ports A and B it operates in response to access.

The 2-point RAM in FIG. 6 is the shared memory 6 in FIG.
1, access ports A and B constitute path line A 70 and path line B 71, respectively, in FIG. With reference to FIGS. 5 and 6,
In such a case, the MPUA 62 uses the ROMA 63. R.O.
MA64. and controls the I10 controller A65 to instruct write mode/read mode to the A boat block 100, output an address signal specifying an address in the shared memory cell array 11, and read data from memory cells in the shared memory cell array 11. , RAM of data read from the shared memory cell array 11
63, writing of data stored in RAMA 63 and ROMA 64 into shared memory cell array 11, etc. are all performed via pass line A70. In addition, I10
The controller A65 is an I in the A boat block 100.
10 buffer 12, I10 controller B69
controls the I10 buffer 16 in the B port block 200.

Similarly, the MPU 11163 has RAM [167, ROM
B68. and controlling the I10 controller B69,
Instructing write mode/read mode to B boat block 200, outputting an address signal specifying an address in shared memory cell array 11, reading data from memory cells in shared memory cell array 11, data read from shared memory cell array 11 RAMa6 of
7, writing of stored data in RAMB 67 and ROMB 68 to shared memory cell array 11, etc. are all performed via pass line B71. That is, in response to the command from the MPUA 62, the A boat block 100
The shared memory cell array 11 can be accessed, and the B boat block 200 can access the shared memory cell array 11 in response to instructions from the MPU [166. As a result, the fifth
In the figure, MPUA 62 and MPUa 66 can write/read data to/from shared memory 61 independently of each other and asynchronously.

[Issue to be solved by the invention'IB3 As described above, the conventional multi-port memory has multiple MP
It operates in response to independent and asynchronous commands from each of the U's. If the addresses selected by the plurality of MPUs at the same time are different from each other, only one of data writing and reading is performed in each of the selected memory cells. Therefore, in such a case, each of the plurality of MPUs can correctly read/write data to the selected memory cell without causing any problem. However, since MPU instructions are issued independently/asynchronously, multiple MPUs may simultaneously issue instructions to select memory cells at the same address in a shared memory cell array in a multiport memory via their corresponding access ports. Or they may be released at the same time. In such a case, the following problems arise. This problem will be explained using the 2-port RAM shown in FIG. 6 as an example.

The basic operation of the 2-point RAM shown in FIG. 6 is when both the A port block 100 and the B port block 200 are operating in read mode (first operating state).
When the A port block 100 is operating in read mode and the B port block 200 is operating in write mode (second operating state), the A port block 100 is operating in write mode and the B port block 200 is operating in write mode. When operating in read mode (operating state of m3), and when both A port block 100 and B port block 200 are operating in write mode (4th
There are four possible operating states.

First, when the 2-bot block RAM is in the first operating state, even if the same address is selected by the A port block 100 and the B port block 200, the stored data of the memory cell corresponding to the same address is is only read by both the A boat block 100 and the B boat block 200, the data stored in the memory cell will not change or the data stored will not be read correctly, and no particular problem will occur.

However, when the two-vote block RAM is in the second operating state, when the addresses selected by each of the A-vote block 100 and the B-vote block 200 coincide in time, the B-vote block 200, which is in write mode, Although the write data can be correctly written to the selected memory cell, the A port block 100 in the read mode may not be able to correctly read the stored data of the selected memory cell.

For example, while the B port block in write mode is writing data to a selected memory cell, if the A port block 100 in read mode performs a read operation by writing 1 to the same memory cell, the A port block 10
0, reading is performed from a memory cell in an unstable state in which stored data is not yet determined because data writing by the B port block 200 has not yet been completed. Therefore, in such a case, the A port block 100 reads unstable data that is being written by the B port block 200 from the selected memory cell. However, B
If the A-boat block 100 reads data from the same memory cell immediately before the port block 200 writes data to the selected memory cell, the A-boat block 100
The data read by B-vote block becomes old data before writing by B-vote block. Conversely, if the A boat block 100 reads the same memory cell immediately after the B boat block 200 writes data to the selected memory cell, the data read by the A boat block 100 will be transferred to the B boat. This is new data after block writing is performed. Therefore, with respect to the same memory cell, the data read by the A-vote block 100 may differ depending on at what point in the write cycle of the B-vote block 200 the read operation of the A-vote block is performed.

The opposite problem occurs when the two-point block RAM is in the third operating state. That is, regarding the same memory cell, the read operation of the B port block 200 is
The data read by B port block 200 may vary depending on where in the write cycle of A port block 100 the data is read.

As can be seen from the above, in the second and third operating states, writing and reading from the A port block 100 and the B port block 200 to the same memory cell are performed temporally overlapping. There is a possibility that successive data output from a port block during a read operation may change within one successive cycle.

When the 2-vote RAM is in the fourth operating state, two opposite data are simultaneously written to the memory cell.
There is a possibility that the data stored in that memory cell is neither "1" nor "0" and is uncertain.In other words, the A port block 100 and the B port block 20
If the same memory cell is selected by 0 and the data that the A port block 100 attempts to write and the data that the B port block attempts to write are different, the selected memory cell will have these two data. Two different data are given simultaneously. As a result, the data stored in the memory cell becomes uncertain after the writing by the A boat block 100 and the B boat block 200 is completed.

As described above, in a multiport memory having a plurality of access ports, a problem arises because a plurality of accesses may be simultaneously performed to the same memory cell.

To solve this problem, it is necessary to connect at least two access ports to the same location (
address) is selected, the problem can be solved by allowing access from one access port and suspending acceptance of access from the other access port until the processing operation from the one access port is completed. Conceivable. Therefore, in order to avoid the above-mentioned problems, a circuit section has been created that implements a function to suspend access from one access port until the access from the other access port is completed. provided externally. However, since this circuit section has a complicated configuration using gate arrays and the like, it requires many ICs.

An object of the present invention is to solve the above-mentioned problems that occur in multi-port memory due to multiple independent accesses, and to improve multi-port memory so that multi-port memory can efficiently respond to external accesses. An object of the present invention is to provide a multiport memory control device that can control access to memory without using a circuit with a complicated configuration.

[Means for Solving the Problems] In order to achieve the above objects, a multiport memory control device according to the present invention includes at least first and second access ports; A first address signal applied to a first access port and a second address signal applied to a second access port to control access to a multi-port memory including a shared memory cell array accessed from either side. Address match detection means for detecting a match with an address signal, first address change detection means for detecting a change in the first address signal, and second address change detection means for detecting a change in the second address signal. In response to the detection output indicating "match" from the address match detection means, the first and second address change detection means are detected based on the detection output of the first address change detection means and the detection output of the second address change detection means. and means for deriving a signal for interrupting access to the shared memory cell from an access port that receives one of the changed address signals among the second address signals.

[Operation] Since the multi-port memory control device according to the present invention is configured as described above, the first address signal manually input to the first access port or the second address manually input to the second access port Only when the first address signal and the second address signal indicate the same address due to a change in the signal does the signal from the access port receiving one of the first and second address signals A signal is derived for interrupting access to coexisting memory cells. Therefore, when the same address of the shared memory cell array is selected via the first and second access ports, the access port to the shared memory cell array from either the first or second access port is Access is now possible.

[Embodiment] FIG. 1 is a schematic block diagram of a two-point RAM according to an embodiment of the present invention.

Referring to FIG. 1, this 2-baud RAM differs from the conventional one shown in FIG.
．． A boat block 100. and B port block 2
00, an address conflict adjustment circuit 20 is included on the same chip. In the following description, it is assumed that this two-point RAM is used as the shared memory 61 in FIG. 5. A port block 100 is connected to MPUA 62 via pass line A70 in FIG. 5, and B port block 200 is connected to MPo, 66 via pass line B71 in FIG.

The address conflict adjustment circuit 20 is connected to the A port block 100.
Data A of each bit of the n+1 bit address signal input to the. (A) to Ao (A) and data A of each bit of the n-bit address signal input manually to the B port block 200.

(B) ~ Ao In response to (B), a signal No. instructing suspension/approval of access from the A boat block 100
t Ready A and B boat block 200
Signal indicating suspension/approval of access from Not
Outputs Ready B.

The instruction signal Not Ready A is applied to a predetermined terminal of the MPUA 62 connected to the A port block 100. The predetermined terminal is a so-called ready terminal that receives a control signal for enabling/disabling the access operation of the MPU, and has conventionally been generally provided in the MPU.

Similarly, the instruction signal Not Ready B is
It is given to the ready terminal of MPUB 66 connected to B port block 200. In this embodiment, both the MPUA 62, MPU, and 66 can perform an access operation when the signal applied to the ready terminal is at a high level, and can perform an access operation when the signal applied to the ready terminal is at a low level. It shall not be possible to do so.

Next, the internal configuration of address conflict adjustment circuit 20 will be explained. FIG. 2 is a schematic block diagram showing the internal configuration of the address conflict adjustment circuit 20.

Referring to Figure 2, address conflict y! The J adjustment circuit 20 is
The A-boat address change detection circuit section 22 detects a change in the address signal (hereinafter referred to as A-boat address) input from the A-boat block 100 in FIG. 1, and the B-port block 200 in FIG. A B port address change detection circuit 23 that detects a change in an address signal (hereinafter referred to as B port address), and an A and B port address match detection circuit 21 that detects that the A port address and B port address match. A port address change detection circuit 22. B port address change detection circuit 23. and A, B port address match detection circuit 2
In response to the detection output of 1, the instruction signal Not Read
y A and a priority port determination circuit 24 that outputs Not Ready B.

The priority port determination circuit 24 determines whether an access from the A port block 100 and an access from the B port block 200 overlap in time with respect to any memory cell in the shared memory cell 11 in FIG. ,
A low-level instruction signal is given to the MPU connected to the port block accessed later, and a high-level instruction signal is given to the MPU connected to the port block accessed first. Furthermore, even if access from the A port block 100 and access from the B port block 200 are performed on any memory cell in the shared memory cell 11 at the same time, the priority port determination circuit 24 determines whether the B port block I will be connected to
Instruction signal given to PU^62 Not Rea y
and the logic level of M connected to the B port block.
Instruction signal Not Ready given to PUa 66
Let B be different.

FIG. 3 is a circuit diagram showing an example of a specific circuit configuration of the address conflict adjustment circuit 20 having the configuration shown in FIG. FIG. 4 is a waveform diagram for explaining the operation of the circuit shown in FIG. 3. Hereinafter, the internal operation of the address conflict adjustment circuit shown in FIG. 3 will be explained in detail with reference to FIG. 4.

In Fig. 3, n+1 two-man EX-OR gates 2
11-0-211-n, n+l NOR gate 212. The inverter 213 constitutes the A and B port address coincidence detection circuit 21 in FIG. Data Ao of each bit of the address signal from the A port block 100
(A) to An (A) are each input to one input end of the two-man EX-OR gates 211-0 to 211-n,
Each bit of data Ao (B) to An (B) of the address signal from the B port block 200 is 2
Human power is input to the other input terminal of EXOR game) 211-0 to 211-n. In other words, EX-OR gate 211-
1 to 211-n each have an A port address and a B port address.
The data of corresponding bits of the port address are manually entered.

For example, the EX-OR gate 211-1 selects data Ao (A) and Ao of the least significant bit of the address signal.
The EX-OR gate 211-n outputs a low level signal only when the logic levels of (B) match, and the EX-OR gate 211-n outputs data A of the most significant bit of the address signal. (A) and A.

A low level signal is output only when the logic levels of (B) match.

In this way, EX-OR Age-211-1 to 211-n
Each outputs a low level signal only when the logic levels of the two human input signals match.

Therefore, EX-OR gates 211-1 to 211-n
The reason why all the output signals of are at low level is because the memory cell selected by the A port block and the memory cell selected by the B port block are the same, and the A port address and B port address are the same.
This is when all the data of the corresponding bits match with the port address.

The output of EX-OR gate 211-Cl-211-n is n
+1 is given to the human powered NOR gate 212.

The NOR gate 212 outputs a high-level signal only when the logic levels of all n+1 human input signals are low level, and if any one of the n+1 human input signals is high level, other signals are output. Outputs a low level signal regardless of the logic level of the human input signal. Therefore, A
Only when the port address and the B boat address match, the output of the NOR gate 212 becomes high level.

The output of the NOR gate 212 is inverted by an inverter 213 and input to the priority boat determination circuit 24 . Therefore, in this embodiment, the detection output of the A and B port address coincidence detection circuit 21 is at the frontage level where the A port address and the B port address match.

On the other hand, in FIG. 3, n+1 two-man EX-OR gates 221-0 to 221-n, n+11 fixed delay circuit
(denoted as Delay in the figure) 222-0 to 222-n and the n+1 manual OR gate 223 constitute the A boat address change detection circuit 22 in FIG. Similarly, n+
1 2-person EX-OR gate 231-0 to 231-n
, n+1 delay circuits 232-0 to 232-n, and n+1 manual OR gate 233 constitute the B boat address change detection circuit 23 in FIG.

One of the EX-OR gates 221-0 to 221-n manually inputs data Ao of each bit of the A port address.
(A) ~An (A) is input manually, and the other inputs of the EX-OR gates 221-0 to 221-n each receive data Ao (A) ~An of each bit of the A boat address.
(A) is delayed by a predetermined 0-opening delay by delay circuits 222Q to 222-n and then manually inputted. Therefore, data Ao (A) to Ao of each bit of the A boat address
When the data of any bit of (A) changes, the EX-OR gate corresponding to the changed bit receives the signal input through the delay circuit, that is, the data before the change and the delay circuit. Signals that are directly input without any intervention, that is, changed data, which are signals with different logic levels, are input manually. As a result, the output of this EX-OR gate switches from the logic level (low level) when the two human input signals are equal to the high level. Then, when the predetermined time has elapsed since the data changed, this EX
The changed data is input to both of the -OR gate's input, and the logic levels of the two input signals to the EX-OR gate match again, so the output of the EX-OR gate returns to low level. In this way, when the A boat address changes, the E
The output signal of the X-OR gate becomes high level for the delay time in the delay circuit.

The outputs of EX-OR gates 221-0 to 221-n are n
+1 human power OR gate 223 receives human power.

If at least one of the outputs of the EX-OR gates 221-0 to 221-n, which are input signals, is at a high level, the OR gate 223 outputs a high-level signal regardless of the logic level of other human input signals. EX-OR Age-
A low level signal is output only when the outputs of -221-0 to 221-n are all low level. Therefore, when there is no change in the A port address, the output signal of the OR gate 223 is at a low level, and when the A port address changes, the output signal of the OR gate 223 is at a high level for the predetermined period of time. The output of the OR gate 223 is given to the priority boat determination circuit 24 as the detection output of the A boat address change detection circuit 22.

The B boat address detection circuit 23 also performs the same operation as the A boat address change detection circuit 22.

That is, in the B boat address detection circuit 23,
EX-OR gates 231-0 to 231-n each input data Ao (B) to A of each bit of the B boat address, respectively.
(B) directly and delay circuits 232-0 to 2B2-n
are received through each, and the n+1 human OR gate 233 receives EX
-Receiving the outputs of OR gates 231-0 to 231-n,
When the B port address changes, a high level signal is output for the delay time by the delay circuit. OR gate 2
The output of 33 is given to the priority port determination circuit 24 as a detection output of the B port address change detection circuit.

For example, consider a case where the A boat address and the B port address each change at the timings shown in FIGS. 4(a) and 4(b).

Note that in FIGS. 4(a) and 4(b), periods al, a2 . and a3, respectively, during periods b1, b2 . and b
Assume that it is the same as the B boat address in 3. As mentioned above, the output of the A boat address change detection circuit 22 (FIG. 4(d)) and the output of the B boat address change detection circuit 23 (FIG. 4(e)) in FIG.
Each time the A port address and the B port address change, the level is set to high level for a predetermined period by the delay circuit. On the other hand, the detection output of the address match detection circuit 21 is shown in FIG.
As shown in c), it goes low every time the A port address and B port address match, and goes high again when either the A port address or the B port address changes and they become different. level.

In other words, the detection output is generated during the periods tI+t2+ and t during which the A port address and the B port address match.
It is at a low level during the period corresponding to .

The priority port determination circuit 24 includes a later arriving boat storage circuit 24a which receives the detection outputs of the A port address change detection circuit 22 and the B boat address change detection circuit 23, the detection outputs of the A and B port address coincidence detection circuit 21, and the latter A later arriving boat information latch circuit 24b receiving the output of the arriving boat storage circuit 24a, and a later arriving boat information latch circuit 24b.
and the detection output of the A and B boat address match detection circuit 21.
1.

The latter port storage circuit 24a is a two-man powered NAND gate 2.
41. It is comprised of an inverter 242 and two NAND gates 243 and 244 that are cross-connected to form a flip 70 tube. The NAND gate 241 connects the detection output of the A port address change detection circuit 22 and the B
It receives the inverted signal of the detection output of the boat address change detection circuit 23.

When the A port address changes and the B port address does not change, that is, when the A port address changes first, both the output of EX-OR gate 223 and the output of inverter 242 become high level. Therefore, a low level signal is output from the NAND gate 241. Therefore, in this case, the NAND gate 24
The output of No. 3 is determined to be high level by the low level signal from NAND gate 241. And NAN
The output of D gate 244 is the determined NAND gate 2
The output of the inverter 243 (high level) and the output of the inverter 242 (high level) determine the low level.

The output (low level) of NAND gate 244 is fed back to the input of NAND gate 243, thereby fixing the outputs of NAND gates 243 and 244 to high level and low level, respectively.

In other words, the output signal of the NAND gate 241 is
It is held at the output of gate 244.

Thereafter, if there is no change in either the A port address or the B port address, the NAND gate 241
-Receives low level and high level signals from OR gate 223 and inverter 242, respectively, and outputs a high level signal. In other words, NAND gate 241
only the output logic level of changes. As a result, NAND
The output logic level of gate 243 is
The state is determined by the output logic level of 4. On the other hand, since the high level signal is still applied to one input terminal of the NAND gate 244 from the inverter 242, the output logic level of the NAND gate 244 also changes to the NAND gate 244.
It is determined by the logic level applied to the other input terminal of ND gate 244, that is, the output logic level of NAND gate 243. Before the output of NAND gate 241 switches to high level, the output logic level of NAND gate 244 is low level. Therefore, if neither the A port address nor the B boat address changes after the A port address changes, the NAND gate 24
The output logic level of 3 remains high level, and the NAN
The logic level at the output terminal of D gate 244 is held at low level.

After that, if the A boat address does not change and only the B boat address changes, that is, if the B boat address changes first, the output of the EX-OR gate 223 and the output of the inverter 242 both become low level. Become. In other words, only the output logic level of inverter 242 changes.

As a result, the output logic level of NAND gate 243 continues to be determined by the output logic level of NAND gate 244, while the output logic level of NAND gate 244 receiving the low level signal from inverter 242 is at high level. will be confirmed. by this,
The NAND gate 243 outputs the determined output logic level (high level) of the NAND gate 244 and the NAND gate 243.
In response to the output logic level (high level) of the gate 241, a low level signal is input to the NAND gate 244. As a result, the output logic level of NAND gate 244 is determined to be high level.

After that, if there is no change in either the A port address or the B port address, the EX-OR gate 23
When the output of NAND gate 244 is switched to low level, the output logic level of inverter 242 is switched to a level at which the output logic level of NAND gate 244 cannot be determined, that is, to high level. However, in this case, the NAN
The output logic level (
low level) is applied to the NAND gate 244.

As a result, the output logic level of NAND gate 244 is held at the same high level as before.

Note that during the period when neither the A port address nor the B port address has changed, the NAND gate 24
4 output logic level is not determined and NAN
The output logic level of D gate 241 and inverter 242 is a high level that cannot determine the output logic level of NAND gates 243 and 244, respectively. Therefore, during such a period, the output logic level of both NAND gates 243 and 244 is not determined, so the data held at the output terminal of NAND gate 244 is also not determined.

As can be seen from the above, the data held at the output terminal of the NAND gate 244 is once set to either a high level or a low level when either the A port address or the B port address changes for the first time. After that, it switches every time either the A port address or the B port address changes. The logic level of the output terminal of the NAND gate 244 is given to the later arriving information latch circuit 24b as storage data of the later arriving boat storage circuit 24B.

Now, when the A boat address and the B port address change at exactly the same time, the output logic levels of NAND gate 241 and inverter 242 both switch from high level to low level.

As a result, the output logic levels of NAND gates 243 and 244 both become high level, and the data held at the output terminal of NAND gate 244 always becomes high level. As described above, the output logic level of the NAND gate 244 becomes low level when only the A port address changes, and becomes high level when only the B port address changes. Therefore, when the A boat address and the B boat address change at exactly the same time, the data stored in the latter boat memory circuit 24a will be changed when a new address designation from the B boat block 200 is changed to a new address designation from the A boat block 100. This indicates that it was done earlier. In other words, the data stored in the latter port storage circuit 24a is stored in the A port block IC.
If the access from O is earlier than the access from B port block 200, it becomes low level, and the access from B port block 200 is before the access from A port block 1.
If it is accessed from 00 at the same time or earlier, it becomes high level. Therefore, as shown in FIG. 4(f), the output of the subsequent port storage circuit 24a becomes low level every time the A port address changes and the detection output of the A port address change detection circuit 22 rises. Every time the port address changes and the detection output of the B port address change detection circuit 23 rises, it becomes 7X high level.

The latter port information latch circuit 24b includes two NOR gates 245 and 247, an inverter 246 that inverts the detection output of the address match detection circuit 21, and two NOR gates 248 and 249 forming a flip-flop.
including. NOR gate 247 is NOR gate 245
and the detection output of the address match detection circuit 21 which is inverted by the inverter 246.

When the output logic level of the address match detection circuit 21 is high level, that is, when the A port address and the B port address are different at the same time, the NOR gate 247 receives a low level signal from the inverter 246. The output logic level of -4247 is N
Determined by the output logic level of OR gate 245. N
The OR gate 245 receives the detection output of the address coincidence detection circuit 21 inverted by the inverter 246 and the data stored in the subsequent boat storage circuit 24a.

Now, the B port address changes and the shared memory cell array 11 is accessed first from the B port block 200), and after this change, the address match detection circuit 2
When the output of 1 is high level, the subsequent port storage circuit 2
NOR gate 2 is activated by the noise level signal from 4a.
The output signal of 45 becomes low level regardless of the detection output of the address match detection circuit 21. Now, NOR gate 248 receives the output of NOR gate 249 as an input. Therefore, when the output of NOR gate 245 goes low, NOR gate 248 enters a state determined by its output logic level or the output logic level of NOR gate 249. On the other hand, the output of the NOR gate 245 and the inverter 24 are determined to be low level.
6, the NOR gate 24
The output logic level of 7 is determined to be high level. As a result, the output of the NOR gate 249 receiving the output of the NOR gate 247, that is, the manual logic level of one of the NOR gates 248 is determined to be a high level. As a result, the output logic level of NOR gate 248 becomes high level.

Conversely, if the A port address changes first and the output of the address match detection circuit 21 after this change is at a high level,
The output logic level of the subsequent port latch circuit 24a changes from high level to low level. This allows NOR
The logic levels of the two input terminals of the gate 245 are both low level, and the output logic level of the NOR gate 245 is high level. Next, the high level output of NOR gate 245 determines the output logic level of NOR gate 248 to be high level. On the other hand, since NOR gate 247 receives a high level signal from NOR gate 245 and outputs a low level signal, the output logic level of NOR gate 249 is determined by the output logic level of NOR gate 248. . Therefore, in this case, the output logic level of NOR gate 249 is determined to be high level by the low level signal output from NOR gate 248. These two N
The outputs of OR gates 248 and 249 are each fed back to the other NOR gate, so that N
As long as there is no change in the output of either OR gate 245 and 247, the output logic level of NOR gates 248 and 249 will also not change.

In this way, if the B port address changes first or the A port address and B port address change simultaneously, if the output of the address match detection circuit 21 is at a high level, the output terminals of the NOR gates 248 and 249 High-level and low-level signals are latched at the respective high-level and low-level signals. If the output of address match detection circuit 21 is at a high level when the A port address changes first, low level and high level signals are latched in NOR gates 248 and 249, respectively.

In other words, if the A port address or B port address changes and the B port address and B port address after the change are different, the subsequent port information storage circuit 24b
The storage information (the logic level of the output terminals of NOR gates 248 and 249) changes in accordance with the change in the output of the subsequent port storage circuit 24a, and determines which of the A port address and B port address changed first. This will indicate the following.

However, if the output of the address match detection circuit 21 is low level, that is, if the A port address and the B boat address match, the subsequent port information latch circuit 24
At b, both NOR gates 245 and 247 receive a high level signal from inverter 246. As a result, the output logic levels of NOR gates 245 and 247 are respectively changed to the later port storage circuit 24a.
is fixed at a low level regardless of the output of the NOR gate 245 and the output of the NOR gate 245. This means that the output logic level of NOR gate 248 is determined by the output logic level of NOR gate 249, and the output logic level of NOR gate 248 is determined by the output logic level of NOR gate 249. Therefore, in this case,
If the logic level of the output ends of the NOR gates 1248 and 249 has already been determined, the subsequent port information latch circuit responds to the detection output of the address match detection circuit 21 becoming a low level indicating "match". 24b is applied with a strobe, and the storage information update operation of the subsequent port information latch circuit 24b in response to the output of the subsequent port storage circuit 24H is stopped.

For example, referring to FIG. 4(g), in the later arriving boat information latch circuit 24b, the NAND gate 245 controls the later arriving boat information during a period when the detection output of the address match detection circuit 21 is at a high level indicating "mismatch". In response to the output of the port storage circuit 24B, the output of the subsequent port storage circuit 24a is inverted and output, and during the period when the detection output of the address match detection circuit 21 is at a low level indicating "match", the output of the subsequent port storage circuit 24B is inverted and output. Regardless of the output of the port storage circuit 24a, a signal of the same logic level as before is output.

On the other hand, as shown in FIG. 4(h), during the period when the detection output of the address match detection circuit 21 is at a high level indicating "mismatch", the NAND gate 247 inputs the output of the subsequent port storage circuit 24a. In response, the subsequent port storage circuit 2
4a is output without being inverted and the detection output of the address match detection circuit 21 is at a low level indicating "match", regardless of the output of the subsequent port storage circuit 24a.
Outputs a signal with the same logic level as before.

In response to the outputs of NAND gates 245 and 247, NAND gates 248 and 24
The outputs of 9 vary as shown in FIGS. 4(i) and (j), respectively. In other words, during the period when the output of the address match detection circuit 21 indicates "mismatch", the NAND gate 248
The output of NOR gate 249 falls each time the output of NOR gate 245 rises in response to a change in the A port address, and the output of NOR gate 249 falls in response to a fall of NOR gate 245 in response to a change in the B port address. Rise up every time you fall. Conversely, the output of NOR gate 249 falls each time the output of NOR gate 245 falls in response to a change in the B port address, and falls in response to a rise in the output of NOR gate 245 in response to a change in the A port address. It rises every time the output of NOR gate 248 falls.

Then, the detection output of the address match detection circuit 21 is match 0.
During the period shown, the outputs of NOR gates 248 and 249 do not change.

NO which is the memory information of the subsequent port information latch circuit 24b
The outputs of R gates 248 and 249 are provided to NOR gates 250 and 251, respectively. NOR gate 25
0 and 251 are also input with the detection output of the address match detection circuit 21.

Therefore, when the detection output of the address match detection circuit 21 is at a low level and the output of the NOR gate 248 is at a high level, that is, when the B port address changes or the A port address and the B
When the port addresses change simultaneously and the A port address and B boat address match,
NOR game) 250 outputs a low level. and,
When the detection output of the address match detection circuit 21 is low level and the output of the NOR gate 248 is low level, that is, when the A boat address and the B port address match due to a change in the A boat address, NOR gate 250 outputs a high level.

On the other hand, NOR gate 251 is supplied with a signal from NOR gate 249 that has a logic level opposite to the output logic level of NOR gate 248 . Therefore, NOR gate 2
51 operates in the opposite way to NOR gate 250. That is, the output of the NOR gate 250 becomes high level when the B port address changes and the A port address and B port address match, and goes high when the A port address changes and the A port address and B port address match. becomes low level.

When the detection output of the address match detection circuit 21 is at a high level, that is, when the A port address and the B port address are different, the outputs of the NOR gates 250 and 251 are Both are at low level.

The outputs of NOR gates 250 and 251 are inverted by inverters 252 and 253, respectively, and then output to the instruction signals Not Ready A and Not ea.
MPU^62 and M in Figure 5 as dy B
It is output to PU666. Therefore, the instruction signal Not Ready-τ finally obtained is as shown in FIG. 4(k).
As shown in FIG. 3, it is at a high level during the address match period and address mismatch interval caused by a change in the B port address, and is at a low level only during an address match period caused by a change in the A port address. Conversely, the instruction signal Not Ready B is
As shown in FIG. 4, by changing the B photo address and the A port address and B
It is at a low level during an address match period caused by simultaneous changes in the port address, and becomes a high level only during an address match period caused by a change in the A port address.

As can be seen from the above, the A boat address and the B port address are different/sometimes the instruction signal Not
Rea y and Not ei1]=-
1- becomes a high level which causes the MPUA 62 and MPUa 66 to perform an access operation. Here, the fact that the A port address changes and matches the B port address means that while the B port address is writing or reading data to or from a memory cell in the shared memory cell array 11 in FIG. This means that the same memory cell was also accessed from block 100. Conversely, the fact that the B port address changes and matches the A boat address means that while the A port block is writing or reading data to or from a memory cell in the shared memory cell 11, the B port address changes to match the A boat address. also means that the same memory cell was accessed. Also, if the A port address and the B boat address change at the same time and match, the A port block 10
This means that the same memory cell in the shared memory cell 11 was accessed from the 0 and B boat blocks 200 at the same time.

Therefore, in this embodiment, for the same memory cell, the A port block 100 and the B port block 20
0 is accessed first, two instruction signals Not Ready A and Not Ready
Only one of Ready B becomes high level. Specifically, a high-level instruction signal instructing "access approval" is given to the MPU connected to the port block that previously accessed a given memory cell, and the MPU that accesses the memory cell earlier A low level signal instructing "access pending" is given to the MPU connected to the port block.

In other words, priority is given to access from the port block that outputs the first address signal. In addition, in this example, A
If the same memory cell is accessed from the port block 100 and the B port block 200 at the same time, the access from the A port block is unconditionally given priority.

1 to 5, if any memory cell in the shared memory cell array 11 in FIG. 1 is accessed first from the MPUA 62 in FIG. 5 via the A port block 100 in FIG. After that, MPUa
When there is an access from 66 through the B port block 200 and the A boat address and B port address overlap in time (address conflict condition @), that is, at time T1 in FIG. Not Re
ady B becomes low level, access from MPo 66 is suspended, and access from MPUA 62 is accepted preferentially. After that, when the access from MPUA62 ends and the A port address changes, A
The boat address and the B port address no longer match, and the instruction signal Noteay returns to high level again.

Conversely, after MPUB 66 is accessed first,
When there is an access from the MPUA 62 and an address conflict occurs, that is, at time T2 in FIG.
The instruction signal Not ReadyA becomes low level, access from MPUA 62 is suspended, and MPUa 6
Access from 6 is preferentially accepted. After that, M
When the access from PUB 66 ends and the B port address changes, the B port address and the A port address no longer match, so the instruction signal NotRea
dy A returns to high level again. Also, for the same memory cell, MPUA 62 and MPU[166
If there are simultaneous accesses from , that is, at time T3 in FIG.
B becomes low level and access from the MPUA 62 is accepted first.

Therefore, in the two-port RAM shown in FIG. 1, if the addresses selected by the A port block 100 and the B port block 200 overlap in time, the port block accessed first ( However, A boat block 100 and B port block 20
If there are simultaneous accesses from port block 0, data is written/read only from one predetermined port block, and then data is written/read from the other port block. As a result, the above-mentioned problem that occurs when the same memory cell is simultaneously accessed from different access ports does not occur.

In the above embodiment, if addresses are selected from both access ports A and B at the same time, priority is given to processing from access port A (instruction signal Not
Although the address conflict: A direction path is configured such that Ready B is set to low level, it is easy to give priority to processing from access port B. That is, in this case, in FIG.
4a shows the output of the A port address change detection circuit 22 and the output of the B port address change detection circuit 22.
This can be done manually by reversing the output of the port address detection circuit 23.

Further, in this embodiment, the present invention is applied to a two-point RAM, but it is of course possible to apply the present invention to a multi-port memory having two or more access ports.

[Effects of the Invention] As described above, according to the present invention, the same address can be reliably specified from each access port using a circuit with a relatively simple configuration using an address coincidence detection means and an address change detection means. When selecting an address conflict, priority is given to access from the access port that specified the address first, and if the same address is selected from multiple access ports at the same time, access from one of the access ports is given priority. It can be processed first. Therefore, even if the same address is selected by address signals from different access ports, read/write operations from each access port are performed correctly. Therefore, it becomes possible for a plurality of control units such as MPUs to independently use the shared memory cell array in the multiport memory. As a result, the multiport memory is efficiently used by a plurality of control units such as MPUs, and the operating rate of a multiprocessor system using the multiport memory is improved.

Furthermore, since access to the multi-port memory can be controlled by a circuit with a relatively simple configuration, it is also possible to provide a circuit section for this control on the same chip as the multi-port memory.

In addition, since the detection of a change in the address signal manually input to each access port is determined only by the timing difference in addressing from each access port with equal weighting for each access port, external circuits (for example, MPU ) side also eliminates the trouble of providing a time difference (priority set-up time) in advance for access operations.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a two-point RAM equipped with a multiport memory control device according to the present invention, which is an embodiment of the present invention, and FIG. 2 shows the configuration of the address conflict adjustment circuit in FIG. 3 is a circuit diagram showing a specific configuration example of the address conflict adjustment circuit shown in FIG. 2, and FIG. 4 is a timing chart diagram for explaining the operation of the circuit shown in FIG. 3. , FIG. 5 is a block diagram of a multiprocessor system using a multiport system, and FIG. 6 is a schematic block diagram of a conventional two-bottom RAM. In the figure, 11 is a shared memory cell array, 20 is an address conflict adjustment circuit, 21 is an A and B boat address match detection circuit, 22 is an A boat address change detection circuit, 23 is a B port address change detection circuit, and 24 is a priority port determination circuit. In the circuit, 100 is an A boat block and 200 is a B boat block. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

Claims: A multiport that controls access to a multiport memory including at least first and second access ports and a shared memory cell array that is accessed from both the first and second access ports. A memory control device, comprising: address coincidence detection means for detecting coincidence between a first address signal input to the first access port and a second address signal input to the second access port; , a first address change detection means for detecting a change in the first address signal, a second address change detection means for detecting a change in the second address signal, and a "coincidence" from the address coincidence detection means. ”, one of the first and second address signals is detected based on the detection output of the first address change detection means and the detection output of the second address change detection means. and means for deriving a signal for interrupting access to the shared memory cell from an access port that receives one of the address signals that has changed.