JPH03184149A - Transfer system for memory data - Google Patents

Abstract

PURPOSE:To rewrite picture memory at a high speed by applying the addition or the subtraction to those address data exceeding 1 set previously to update the addresses. CONSTITUTION:The address of a main memory 1 of the transferer side which stores the data corresponding to a symbole (+) and the address of a picture memory of the transferee side are stored in the corresponding transferer and transferee address generating parts 3 and 4 respectively. At the same time, the number of transferred data is stored in a transfer counter part 5. Then the data are fetched from an area of the memory 1 corresponding to the address given from the part 3 and written into an area of the memory 2 corresponding to the address given from the part 4 under the control of a control part 6. When the first transfer of data is through, 1 is subtracted from the number of transferred data stored in the part 5 and furthermore the data stored in the part 3 are updated. Meanwhile the data stored in the part 4 are updated with addition of an offset address (128) of an offset address latch circuit 7. Then the data on an area of the memory 1 corresponding to the updated address of the part 3 are written into an area of a memory 2 corresponding to the updated address of the part 4.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a memory data transfer method using a direct memory access controller (DMAC) that performs high-speed transfer of memory data without the intervention of a CPU in a computer system.

<Prior Art> FIG. 2 is a block diagram showing a schematic configuration of a conventional DMAC.

In the conventional DMAC, when data is to be transferred, the address of the main memory 1, which is the transfer source, and the address of the image memory 2, which is the transfer destination, are stored in the corresponding address generation units 3.4, and The transfer counter unit 5 stores the number of data transfers.

Next, under the control of the control unit 6, data is fetched from the area of the main memory l corresponding to the address from the address generation unit 3 of the transfer source, and
The captured data is written in the area of the image memory 2 corresponding to the address from. When one transfer is completed in this way, 1 is subtracted from the transfer number in the transfer counter section 5, and for the next transfer, the address data of each address generation section 3.4 is increased by, for example, +1. Update.

When the address update is completed, the data is transferred in the same manner as described above, and is repeated until the number of transfers in the transfer counter unit 5 becomes zero.

<Problems to be Solved by the Invention> However, in such a conventional DMAC, updating of address data in the address generation unit 3.4 is limited to 1°0, and therefore, for example, updating of address data for one screen is limited. For example, when copying display data from main memory I to image memory 2 as is, only data in memory areas with consecutive addresses can be transferred; for example, data such as characters can be transferred to any area in image memory. In such cases,
It was necessary for the CPU to calculate the address of the image memory 2, which is the transfer destination.

For example, consider the image memory 2 shown in FIG. Each address of the image memory 2 can store 1 byte of data, and each byte has 8 display dots, so in the X direction, 8x128=1024
It is a display dot. That is, each X in the figure
corresponds to each display dot.

The address change of the image memory 2 is as follows: 10, +1. +2...+127
+128. +127+128...+255+2
56. +257. +258...+383+384
．． +385. +386...+511+512. +
513. +514...+639X direction (horizontal direction)
For example, the address is 10.

+1. +2. ...+127, but the address in the Y direction (vertical direction) is, for example, +127.
0. +128. +256. +384. +512°...
The address is obtained by sequentially adding 128 bytes in the X direction.

Therefore, for example, in order to display the 10 symbol in area A in the upper left corner as shown in FIG. 4, enter oootooo at address 10.

It is necessary to write the following data: 00010000 at address +128, 11111110 at address +256, 00010000 at address +384, oo+383+3, and 00010000 at address +512.If the transfer destination addresses are not consecutive in this way, the above-mentioned DMAC cannot be used. Therefore, it is necessary to calculate the transfer destination address by the CPU. Therefore, when the number of image data to be transferred increases, there is a problem that high-speed rewriting of the image memory 2 becomes difficult.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to enable high-speed rewriting of the image memory by making it possible to transfer data to any area of the image memory using a DMAC. .

<Means for Solving the Problems> In order to achieve the above-mentioned object, the present invention provides a memory data transfer method using a direct memory access controller that transfers data by sequentially updating the address of the memory to be accessed. , the address is updated by adding or subtracting address data exceeding a preset l.

According to the above configuration, when updating the address, address data that exceeds the preset l is added or subtracted, so that the update of the address data can be performed within ±! , 0, and this makes it possible to transfer data in memory areas where addresses are not consecutive.

<Examples> Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a DMAC to which the transfer method of the present invention is applied, and parts corresponding to the conventional example in FIG. 2 are given the same reference numerals.

Furthermore, in this embodiment, the main memory! We will explain the case of transferring data from . Note that the main memory I stores data of the child symbols and characters at predetermined addresses.

In this image memory 2, the address in the Y direction (vertical direction) is an address obtained by sequentially adding 128, which is the number of bytes in the X direction, as described above.

Therefore, in this embodiment, when updating the address of the image memory 2 which is the transfer destination, the address data (offset address) exceeding the preset l latched in the offset address latch circuit 7, that is, 12
This is done by adding 8.

Next, the operation of the DMAC having the above configuration will be explained.

First, the address of the main memory 1, which is the transfer source, where data corresponding to the tens symbol is stored, and the address of the image memory 2, which is the transfer destination (in this example, address 1000)
are respectively stored in the corresponding address generation units 3.4, and the number of data transfers (5 in this embodiment) is stored in the transfer counter unit 5.

Next, under the control of the control unit 6, data (in this embodiment, 0001.0000
) and writes the fetched data (00010000) into the area of the image memory 2 corresponding to the address (address 10) from the address generator 4 as the transfer destination. When the first transfer is completed in this way, l is subtracted from the transfer number in the transfer counter section 5, and for the next transfer, the address data in the transfer source address generation section 3 is updated by 1 as before. do.

On the other hand, the address data of the transfer destination address generation section 4 is updated by adding the offset address (128) of the offset address latch circuit 7.

When the update of the address is completed, data (00010000 in this embodiment) is fetched from the area of the main memory l corresponding to the updated address from the address generation unit 3 of the transfer source, and the data of the transfer destination is The captured data (
00010000). When the second transfer is completed in this way, the number of transfers in the transfer counter section 5 is 1
Furthermore, for the next transfer, the address data of the transfer source address generator 3 is updated by l as in the conventional case.

On the other hand, the address data of the transfer destination address generator 4 is updated by adding the offset address (128) of the offset address latch circuit 7, and the updated address becomes address +256.

When the update of the address is completed, the main memory l corresponding to the updated address from the address generation unit 3 of the transfer source is
data from the area (in this example, 11111110
) is imported into the image memory 2 corresponding to the updated address (address +256) from the transfer destination address generation unit 4.
The imported data (11111110) is in the area of
Write. When the third transfer is completed in this way, 1 is subtracted from the transfer number in the transfer counter section 5, and the address data in the transfer source address generation section 3 is updated as before for the next transfer. do.

On the other hand, the address data of the transfer destination address generator 4 is updated by adding the offset address (+28) of the offset address latch circuit 7, and the updated address becomes address +384.

Thereafter, by performing data transfer up to the fifth time in the same manner, ootooo is stored in image memory 2 at address 10.

+128 ooootooo.

Data 11111110 at address +256, 00010000 at address +384, and 00010000 at address +5I2 are respectively written, and a ten symbol is displayed in area A at the upper left corner of image memory 2.

In this way, data can be transferred to any area of the image memory 2 by the DMAC without going through the CPU, so that the image memory 2 can be rewritten at high speed.

If the offset address preset in the offset address latch circuit 7 is set to +1° or 0, the same operation as in the conventional example is possible.

Further, in the above embodiment, the offset address is 12
8, if the display dots in the horizontal direction of the display screen change, the offset address will of course be changed accordingly.Furthermore, in the above embodiment, the offset address is added. Although I did it,
As another embodiment of the present invention, subtraction may be performed.

<Effects of the Invention> As described above, according to the present invention, the address to be accessed is updated by adding or subtracting address data that exceeds a preset value of l, so that it is possible to update the address to be accessed by adding or subtracting address data exceeding a preset l. In addition, updating of address data is not limited, and this makes it possible to transfer data from memory areas where addresses are not consecutive, thereby making it possible to transfer data to any area in the image memory. D
This can be done using the MAC, making it possible to rewrite the image memory at high speed.

[Brief explanation of drawings]

FIG. 1 shows a DM to which the transfer method of an embodiment of the present invention is applied.
FIG. 2 is a block diagram showing a schematic configuration of AC, FIG. 2 is a block diagram of a conventional example, FIG. 3 is a diagram showing addresses of an image memory, and FIG. 4 is a diagram showing writing of data to the image memory. ! ...Main memory, 2...Image memory, 7...
Offset address latch circuit.

Claims (1)

[Claims] (1) A memory data transfer method using a direct memory access controller that sequentially updates the address of the memory to be accessed and transfers data, and updates the address by adding address data exceeding 1 preset. Alternatively, a memory data transfer method is characterized in that it is performed by subtraction.