JPH03183231A - Pseudo-synchronization prevention circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a frame synchronization circuit that can prevent pseudo synchronization in digital wireless communication, the present invention aims to provide a pseudo synchronization prevention circuit that does not cause false synchronization even when input data is abnormal. , a timing generating section, and a frame synchronization section, in which the frame synchronization circuit includes a monitoring bit extracting means for extracting monitoring bits periodically inserted into input data, and a majority decision of the n monitoring bits extracted by the monitoring bit extracting means. Take l/n
A protection means is provided that detects and outputs an out-of-synchronization when the outputs of the majority circuit and the l/n majority circuit are erroneous for a predetermined number of consecutive frames, and when the protection means detects an out-of-synchronization, the By controlling the timing of the timing generator using the output, it is configured to prevent erroneous synchronization.

[Industrial application field]

TECHNICAL FIELD The present invention relates to a frame synchronization circuit that can prevent pseudo-intervals in digital wireless communications.

BACKGROUND ART In signal processing for digital wireless communication, a method is widely adopted in which a clock pulse is extracted from input data and a frame synchronization signal is generated.

However, in such a system, if "rOJ" or "rOJ" continues, the clock pulse cannot be reproduced, so "0
'' or rN, the data is scrambled and transmitted, and on the receiving side, the data is descrambled and returned to the original data.

There is a need to reliably prevent false frame synchronization even when there is an abnormality in human data in digital wireless communications, and scramble patterns and frame patterns for this purpose are becoming more complex.

Therefore, there is a need for a pseudo-synchronization prevention circuit that does not rely on such complicated scramble patterns and frame patterns.

[Conventional technology]

FIG. 7 is a block diagram illustrating a conventional example.

The conventional example shown in FIG. 7 includes a frame synchronization bit extraction circuit 60 that extracts frame synchronization bits from input data, and a frame pattern that confirms that the pattern of frame synchronization bits extracted from human data is a predetermined pattern. Confirmation circuit 70 and frame pattern confirmation circuit 7
0, a protection circuit 80 detects out-of-synchronization and determines that out-of-synchronization occurs when this state continues for a preset number of frames; a timing generator 10 that generates various timing signals; It consists of a frame synchronization section 20 that changes the timing and synchronizes frames based on the signal generated by the generation section IO.

In the above configuration, the frame synchronization bit extraction circuit 60 extracts the frame synchronization bit from the input data,
When the pattern of the extracted frame synchronization bits matches a predetermined pattern, it is determined that the frame synchronization bits are synchronized.

Furthermore, if the pattern of the extracted frame synchronization bits does not match the predetermined pattern, synchronization is out of synchronization. control and achieve frame synchronization.

For example, set the frame sync bit pattern to 0, ■,
When a simple pattern such as 0.1 is set, when there is an abnormality in the input data, it may appear that there is pseudo synchronization even though there is actually no synchronization.

In order to prevent such pseudo-synchronization, it is necessary to set a complex frame pattern, and the scrambling generator polynomial and frame pattern are determined through computer simulation to prevent pseudo-synchronization.

[Problem to be solved by the invention]

To prevent pseudo-synchronization in the conventional example shown in FIG. 7, a generator polynomial and a frame pattern of a scrambling pattern that will not cause pseudo-synchronization are determined by simulation using a personal computer or the like.

Creating a program to perform this simulation requires long hours of work by skilled engineers, and even if the scrambling pattern generating polynomial and frame pattern determined in this way are used, false synchronization may occur due to system malfunction Sometimes it caused.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pseudo-synchronization prevention circuit that does not cause erroneous synchronization even when input data is abnormal.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

1 in the block diagram of the principle of the present invention shown in FIG. 1 is a frame synchronization circuit consisting of a timing generator IO and a frame synchronization section 20, and 30 is a frame synchronization circuit provided in the frame synchronization circuit l, which is periodically inserted into input data. 40 is an I/N majority voting means provided in the frame synchronization circuit 1 for taking a majority vote of the n bits of monitoring bits extracted by the monitoring bit extraction means 30; Reference numeral 50 denotes a protection means provided in the frame synchronization circuit l, which detects and outputs an out-of-synchronization when the output of the l/n majority decision means 40 is erroneous for a predetermined number of consecutive frames, and is equipped with such a means. This is a means to solve this problem.

[For production]

FIG. 2 is a diagram illustrating an example of a multi-frame configuration of the present invention, in which a frame synchronization bit is placed at the beginning of an l-frame signal, and monitoring bits are inserted at specified intervals.

On the transmitting side, the inserted monitoring bit is extracted by the monitoring bit extracting means 30 on the receiving side, a majority vote is taken of the n monitoring bits, and if the majority vote is correct, it is assumed that synchronization has been performed correctly, and the specified number of frames is When the majority vote is incorrect consecutively, it is assumed that pseudo synchronization has occurred, and the timing is controlled by the timing generating section 10, and the frame synchronization bit with the correct timing is generated by the frame synchronization section 20,
Pseudo-synchronization can be prevented [Embodiment] The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 3 to 6.

FIG. 3 is a diagram explaining the monitoring bit extraction circuit according to the embodiment of the present invention, FIG. 4 is a diagram explaining the majority decision circuit according to the embodiment of the present invention, and FIG. 5 is a diagram explaining the protection circuit according to the embodiment of the present invention. figure to do,
FIG. 6 shows time charts explaining the operation of the embodiment of the present invention.

Note that the same reference numerals indicate the same objects throughout the figures.

The monitoring bits in the embodiment of the present invention are assumed to be 3 bits.

Monitoring bit extraction means 30 according to the embodiment of the present invention shown in Fig.
consists of three monitoring bit extraction circuits 30A, 30B, and 30C, and 30A is a two-person AND circuit (hereinafter referred to as AN).
(referred to as D circuit) 31, 32, and an inverter (hereinafter referred to as IN
V) 33 and a negative OR circuit (hereinafter referred to as NOR circuit) 3 whose inputs are the outputs of the AND circuits 31 and 32.
4 and a flip-flop circuit (hereinafter referred to as FF circuit)
35 and extracts the monitoring bit-1.

The configurations of the monitoring bit extraction circuits 30B and 30C are the same as the configuration of the monitoring bit extraction circuit 30A, but monitoring bits at different timings are input, and the monitoring bit extraction circuits 30B and 30C have the same configuration as the monitoring bit extraction circuit 30A.
Extract 3.

The majority voting means 40 in FIG.
Human-powered exclusive OR circuits (hereinafter referred to as EX-OR circuits) 421 to 423 and two-powered AND circuits 431 to 43
3 and a 3-person NOR circuit 44.

The protection means 50 in FIG. 5 includes three FF circuits 51 to 53,
It is composed of an AND circuit 54 powered by three people.

Pseudo-synchronization detection with the above-described configuration will be explained with reference to the time chart of FIG. 6.

■ This is the frame format of the input data, and the monitoring bits are 3 bits Pl-P3, which are set to "low" level (hereinafter referred to as "H"), "high" level (hereinafter referred to as "H"), and L, respectively. Assume that there is.

■ Pseudo synchronization occurs on the receiving side, and the frame pulse that was originally detected at the position of the broken line is mistaken for the position of the solid line.

■■■ The extraction timing of Pi-P3 is shifted by the same timing as the frame pulse error, and the monitoring bit timing occurs.

Here, it is assumed that H, L, and L are extracted as the monitoring bits because the timing of the monitoring bits is shifted as shown in the figure.

The monitoring bit extracting circuit 30A in FIG. 3 extracts the monitoring bit Pl at the monitoring bit timing -1■, and then
It holds that value until you enter it. Similarly, the monitoring bit extraction circuits 30B and 30C extract the monitoring bits P2 and P3 and hold their values until the next monitoring bit is manually input.

■ It is a multi-frame pulse, and the timing is shifted by the same timing as the incorrect frame pulse.

■■■ This is the output from the monitoring bit extraction circuits 30A, 30B, and 30C, and as described above, the values are held until H, L, and L are extracted and the next monitoring bit is extracted.

[Phase] It is assumed that the majority decision means 40 of this embodiment generates H when synchronization is abnormal.

Setting terminals tl, t2, and t3 of the majority voting means 40 in FIG. 4 are inputted with L and HIL, which are set as monitor bits.

The EX-OR circuits 421 to 423 match the extracted monitoring bits with the set value bits, and output H when they match.

Three EX-OR circuits 4 with AND circuits 431 to 433
AND with two outputs of outputs 21 to 423 as input
Take.

That is, when the outputs of the three EX-OR circuits are all H, the outputs of the AND circuits 431 to 433 are all Hl. When the two outputs of the three EX-OR circuits are H,
The outputs of the AND circuits 431 to 433 are only the l output is Hl, and the outputs of the three EX-OR circuits are Hl and 3.
When both outputs are L, only all of the outputs of the AND circuits 431 to 433 are L, and the majority decision result is output.

The outputs of the three AND circuits 431 to 433 are N.

By using the R circuit 44, its output outputs H when two or more L values do not match, that is, two or more monitoring bits do not match.

In the example, since L, H, and L are H, L, and L, Pi and P2 are wrong, and P3 is normal, so ■
When input, the output of the NOR circuit 44 becomes H,
Detect false synchronization.

This is the same multi-frame pulse as 0 ■.

■The following is written by shortening the time axis of ■~[phase].

■ Same majority output as [phase].

0 This is an output from the protection circuit 50. Using the multi-frame pulse ■ as a clock pulse, the majority output @ is input to the FF circuit 51, and the majority output is shifted by one stage each time the multi-frame pulse 0 is input.

By inputting the outputs of the FF circuits 51 to 53 to the three-person AND circuit 54, when the outputs of the three FF circuits 51 to 53 all become H, H is output.

In this embodiment, when the majority output is 0 for three or more consecutive multi-frame pulses, it is detected as out of synchronization.

The number of stages of the protection circuit 50 is set to the number of stages required by the system.

In the principle block diagram, the timing generator lO and the frame synchronizer 20 are based on known techniques, and the frame synchronizer is also provided with a protection circuit.

The protection output 0 is ORed with the protection output of the frame synchronization unit 20.
is used as a control signal to the timing generator IO, and the timing is changed from the pseudo-synchronized position to achieve correct synchronization.

As described above, false synchronization can be prevented by inserting a monitoring bit and transmitting it, and extracting and monitoring the monitoring bit on the receiving side.

Also, in the embodiment, the monitoring bits are 3 bits, but
Of course, by increasing the number of monitoring bits, the probability of preventing false synchronization can be increased.

〔Effect of the invention〕

According to the present invention as described above, by using the monitoring bit, it is possible to provide a pseudo-synchronization prevention circuit that can prevent pseudo-synchronization of digital wireless communication.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a diagram explaining a multi-frame configuration example of the present invention, FIG. 3 is a diagram explaining a monitoring bit extraction circuit according to an embodiment of the present invention, Figure 4 is a diagram explaining the majority circuit of the embodiment of the present invention, Figure 5 is a diagram explaining the protection circuit of the embodiment of the present invention, and Figure 6 is a diagram explaining the protection circuit of the embodiment of the present invention.
The figure shows a time chart explaining the operation of the embodiment of the present invention, and FIG. 7 shows a block diagram explaining the conventional example. In the figure, 1 is a frame synchronization circuit, IO is a timing generation section, 20 is a frame synchronization section, 30 is monitoring bit extraction means, 30A, 30B, 30C are monitoring bit extraction circuits, 31.
32.431 to 433.54 are AND circuits, 3.411
~413 is INV, 4.44 is NOR circuit, 5.51~53 is FF circuit, 0 is I/N majority voting means, 21~423 is EX-OR circuit, 70 is frame pattern confirmation circuit, 80 is protection circuit, are shown respectively. 8. (,1) A detailed block diagram of the present invention. Figure 1. A block diagram explaining an example of a multi-frame configuration of the present invention. Figure 2. A block diagram explaining a monitoring bit extraction circuit of an embodiment of the present invention.
Figure r, 40 Figure 4 for explaining the majority circuit of the embodiment of the present invention Figure 4 for explaining the protection circuit of the embodiment of the present invention Block diagram for explaining the conventional example

Claims (1)

[Claims] A frame synchronization circuit (1) capable of preventing pseudo-synchronization in digital wireless communication, the frame synchronization circuit consisting of a timing generation section (10) and a frame synchronization section (20), in which input data is periodically a monitoring bit extracting means (30) for extracting the monitoring bits inserted in the monitoring bit; a 1/n majority voting circuit (40) for taking a majority vote of the n monitoring bits extracted by the monitoring bit extracting means (30); A protection means (50) is provided for detecting and outputting an out-of-synchronization when the output of the 1/n majority circuit (40) is incorrect for a predetermined number of consecutive frames, and the protection means (50) detects an out-of-synchronization. 1. A pseudo-synchronization prevention circuit characterized in that when detecting this, the timing of the timing generator (10) is controlled by the output thereof, thereby preventing false synchronization.