JPH03177931A - Optimal object selection execution processing device - Google Patents

Abstract

PURPOSE:To perform the optimum processing in response to various device types with a single program by multiplying an object and at the same time selecting an execution route in accordance with the called type. CONSTITUTION:A load module 4 is loaded in a higher rank hardware 1, for example, and executed. Thus a type take-out instruction part 10 is first executed and a type setting library 6 is called out. The library 6 takes out the type A of the hardware 1 and sets it to an object interface 8. Then a multiplex object 11 is executed and the reference is given to the interface 8. Thus an optimized instruction train, e.g., an instruction train for A 12 is selected in accordance with the type A out of those instruction trains 12 - 14. Then the selected train 12 is carried out. Thus the instructions suited to plural types of hardware can be executed with a single program.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to an optimal object selection execution processing method corresponding to the hardware model at the time of execution.

One program can teach multiple types of hardware,
an object ink face for setting a type, and a multiple object containing a plurality of instruction sequences with the same contents optimized according to each of the types.

A load module is provided with a type setting library for setting the type in the object interface and a type retrieval instruction section for calling the type setting library, and the load module is executed on any of a plurality of computer hardware. , the type setting library called by the type retrieval instruction section sets the type to the object interface, refers to the type to which the multiple object is set, and selects the setting among the multiple instruction sequences of the multiple object. The configuration is configured to select and execute a sequence of instructions according to the type of command.

[Industrial application field]

The present invention relates to an optimal object selection execution processing method,
For more details, see the optimal object selection execution processing method corresponding to the hardware model at runtime.Normally, there are several types of computer hardware, from low to high, and compatibility is maintained between them. . Therefore, for example, a program that can be executed on a general-purpose large-sized computer can also be executed on a supercomputer located above it.

However, in this case, it may not necessarily be said that the execution format is optimal for the higher-end model.

[Conventional technology]

Lower-level and upper-level computer models usually have the same architecture and are compatible at the instruction level to protect program assets. However, since there are differences in the quantity of each hardware, the relative execution performance between the two will differ even if the same instruction sequence (or object) is executed. That is, there is a sequence of instructions (or an execution format) that is passed through each piece of hardware.

This tendency is particularly noticeable in pipeline-type supercomputers.

By the way, it is assumed that two supercomputer hardware units (CI'U: central processing unit) are installed at the center, a lower level and an upper level. In this case, the user's library and application program are prepared as a data set common to both. That is, the dexenode of the instruction string passed through each am is not prepared separately for upper and lower orders.

This common data set is prepared in the form of a load module rather than as a source program, but its instruction sequence is made to consist only of instructions for lower-level models for the following reason. In other words, in a supercomputer, a higher-order model is compatible with all of the instructions of a lower-order model, but a lower-order model is not necessarily compatible with all of the instructions of a higher-order model. This makes one data center common to both.

/Pk nRJ, z hQ book+ l-Q J-nas ill Uf+ 1 In the above-mentioned conventional technology, in order to enable one data set to operate without distinguishing between models.

Koibira, a high-level language such as FORTRAN, outputs a sequence of instructions that can be run on all models. Therefore, from the perspective of each individual model, there is a problem in that the instruction sequence is often not optimal for expressing a program.

Furthermore, since supercomputers have the above-mentioned characteristics regarding compatibility, the instruction sequence is determined according to the lowest model. For this reason, when a library or the like is executed on a higher-end model, there is a problem with its execution performance. That is, there was a problem in that the performance of higher-end models could not be fully utilized.

Note that some compilers for supercomputers output an optimal instruction sequence according to the characteristics of the hardware (CPU) that executes the instruction sequence. However, in this case, the program (object) output from the compiler can only be executed on the only machine specified by the user.
4M--pu J-yh I-41 umbrella 4t
all) m If there is a JBeka, compile it for each model even though the basic parts are compatible.
Since it is necessary to have a load module, it is a burden on the user.

There is a problem in terms of effective use of resources.

SUMMARY OF THE INVENTION An object of the present invention is to provide an optimal object selection and execution processing method that allows one program to execute instructions suitable for multiple types of hardware.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle structure of the present invention, and shows a data processing system according to the present invention.

In FIG. 1, numeral 3 is computer hardware, 4 is a load module, 5 is an object, 6 is a type setting library, 7 is a data section of object 5, and 8
is an object interface; 9 is a command section of the object 5; 10 is a type fetch command section; 11 is a multiple object; and 12 to 14 are optimized command sequences.

For example, a plurality of computer hardware 1 to 3 of three different types (models) are provided in a computer center, and a common load module 4 is provided for these.

The load module 4 is a program in a format executable by the computer hardware 1 to 3, and includes an object 5 of the current program and a type setting library 6.

The object 5 includes an object interface 81, a type retrieval instruction section 10, and a multiple object 11. Object interface 8.

This is an area for setting the type of computer hardware 1 to 3. This setting has two types of settings library 6
carried out by For this purpose, the 1-type extraction instruction section 10 calls the 1-type setting library 6. On the other hand, the multiple object 11 includes a plurality of instruction sequences 12 to 4 having the same content, which are optimized according to nine types.

[For production]

The load module 4 is connected to any one of the computer hardware 1 to 3, for example, the upper hardware 1.
Suppose it is executed with

When the load module 4 is loaded into the higher-level hardware 1 and execution is started, the 9-type fetch instruction unit 1O is executed and the 1-type setting library 6 is called.

The type setting library 6 takes out the type "A" of the upper hardware l, sets it in the object interface 8, and returns it to the object 5.

After this, the multiple object 11 is executed and the object interface 8 is referenced. As a result, the multiple object 11 knows that the type of hardware being executed is r A J.

Therefore, among the instruction sequences 12 to 14, one instruction sequence (A instruction sequence) 12 optimized according to one type "A" is selected and executed.

According to the above, it is possible to check the type of computer hardware A to 3 on which the load module 4 is executed, and select and execute a dynamically optimized instruction sequence 12 to 14 according to this. Therefore, programs can be executed in an optimally expressed form according to the eight types, and the performance of the relevant machine can be fully utilized. Also.

One load module for one program,
It can be common to multiple types of computer hardware 1 to 3.

〔Example〕

FIG. 1 will be further explained.

Computer hardware 3 is, for example, a supercomputer CPU, or a processing device consisting of a CPU and a main memory (hereinafter simply referred to as CPU). C.P.
U1.2 and 3 are each.

These are high-level, middle-level, and low-level models, have the same architecture, and are compatible at the instruction level. A higher-order model is compatible with all the instructions of a lower-order model, but a lower-order model is not compatible with all of the instructions of a higher-order model.

CPUI, 2 and 3 models each have one type "A" and "B1"
``CI and L7 man's type of IPO ``A''
The instruction sequence 12 corresponding to ``1 type rB'' can be executed only by the CPU, and the instruction sequence 13 (all B instruction sequences) corresponding to ``1 type rB'' is C
The instruction sequence 14 which is executable by PUI and CPU 2 and corresponds to one type "Cj" is executable in common by CPUs 1 to 3 (therefore.

(referred to as a common instruction sequence). The type is each CPUI to 3
5, for example, is stored in a predetermined register.

The object 5 is obtained as an output from the compiler and includes a decoder section 7 and an instruction section 9.

The object ink face 8 is provided at a predetermined position in the data section 7 so that the compiler (or object) and the library can commonly cite it. Therefore 1
The type (hereinafter referred to as CP [JID: identifier) is set at a predetermined position of the object 5 or load module 4.

The type extraction instruction section 10 is provided at the beginning of the instruction section 9.

Therefore, at the time of execution, the nine type setting library 6 is executed as an initialization routine prior to execution of all other instructions, and the CPU 1D is set.

As a result, for all subsequent instruction sequences, CPUTD
You can make a selection according to your needs. Note that the "instruction string" refers to the type retrieval instruction section 10, including one consisting of only one instruction.
1, for example, rCALI, type setting library, and is automatically generated by a compiler.

Multiple objects 11 are for A, B, and common (for C).
It consists of instruction sequences 12, 13 and 14, and is automatically generated by a compiler, for example. The multiple object 11 is
In addition to having three instruction sequences (ie, execution routes) corresponding to one instruction sequence of a source program, it also includes means for selecting a unique execution route among the three execution routes according to the CPU ID (type). That is, rIF type -
A.J.

By rELsE lli = 13. , rELSE Select a common execution route for A, B, and ]4 by type-ANYJ, respectively. Each instruction sequence 12.13 and ]4 have the same content (for example, the same number (product calculation) using the same calculation formula). ) is generated from the same instruction sequence of the source progera jz, but it is optimized according to the CPU1D.n(Jchi.

Depending on the hardware, Biblical scheduling, register allocation, etc. are optimized.

The type setting library 6 includes means for accessing and extracting the CPUID from a predetermined register of each CPU 1 to 3, and means for setting the extracted CPUID in the object interface 8.

In addition to the type setting library 6, there are other libraries for input/output, for example, and the load module 4 is configured by linking these and the object 5.

FIG. 2 is an explanatory diagram of the compiler.

In FIG. 2, 16 is a source program, 18 is a processing device, 19 is a compiler, 20 is a program input section, 2
1 is a vectorization processing unit, 22 is an optimization processing unit, and 23 is C
PUID extraction unit, 24, multiple object generation unit, 25
26 is the raw bottom of the object.

Object module, program
9. When the program human resources section 20 receives the source program 1, the literization processing section 21 generates the source program 1.
6('f) Vectorize the predetermined portion.

For example, the Do statement in FORTRAN is vectorized to make it suitable for high-speed processing.

The optimization processing unit 22 performs processing to enable selection and execution of optimal objects during execution. , that is, CPU[
The D retrieval section 23 performs a process of providing the object interface 8 at a predetermined position in the data section 7 and also performs a process of providing a two-type retrieval instruction section 10 at the beginning of the instruction section 9. Therefore, the PUID extraction unit 23 uses the CPU I at the time of execution.
This causes the process to retrieve the variable set as D. The multiple object generation unit 24 is a CPU
1-4↓+-X to perform processing to multiplex develop a predetermined part of the source program 16 and generate multiple object E1 so that the optimal execution route can be selected according to D.
I/8J= Noah 1 lma FFi! Width n l
! - machine rl/~c) - machine 11) middle 4w +17-
A process for adding a means for selecting a command part (instruction part) to the multiple object 11 is performed. The hardware-dependent optimization unit 25 performs hardware-dependent optimization. This ri J
12.13 of multiple instruction sequences of multiple objects 11
and 14 separately. Therefore, for each instruction sequence 12, 13 and 14, 1 different barb line scheduling, 1/register allocation, etc. are performed,
Optimization is performed according to the execution hardware.

The object generation unit 26 generates the object 5 based on the source program 16 which is then subjected to hectorization processing and optimization processing.

At this time, the object generation section 2G generates the object 5 into the data section 7 and the instruction section 92. At the same time, an object interface 8 is provided at a predetermined position determined with the library (6), and various information referenced by the library is set therein.

Therefore, even if no instruction regarding iiM conversion is given in the source program 6, the object 5 suitable for optimization is automatically generated by the compiler 19 or its optimization processing unit 22.

Once the execution hardware is determined, the optimal object is selected and executed accordingly. That is, parts of the source program 16 that should be expanded in multiple ways are automatically recognized, automatically expanded in multiple ways, and each of the multiple expansions is further optimized. Further, means for not extracting C P LJ ID that did not exist in the source program 16 and means for selecting an optimal execution route at the time of execution are added.

FIG. 3 is an explanatory diagram of the object interface.

Between the object 5 generated by the compiler 19 and the library, there is a
There are specific interfaces such as ``r-interrupt top element position'', ``r-mode conversion data'', and ``hardware type (CPU1D)''. The compiler 19 arranges these as object interfaces or library interfaces.
74-Create as a source list in an area that can be referenced by the library in object 5.

In the object 5, various information about the current object 5 is stored.2. There is information about the library infrastructure arrangement at the 48th Hyde G in the entry code. As a result, the effective indicator and g1.1st instruction address of the static area of the data section 7 is pointed to.

The valid indicator indicates whether each element in the library interface list is valid or not. When compiled by the compiler 19, the least significant bit of the valid indicator is always turned ON.

The list designation address points to the address of each element in the library interface list. these are.

It is stored in a portion of the static area of the data section 7 that is referenced by the instruction section (procedure section) 9, and is pointed to by a relative address in the list. CPU ID exists in the 16th byte of the list. The address of CPUTD is compiler 19
and the library.

Ina Pu Ninoini +l +1 Koto? - P type 911 is always deaf, and ifte 116 is called, the entrance code is 4.
Refer to the 8th byte and check the validity with the validity indicator,
Refer to the list specified address and place the CP at the 16th byte of the list.
Set the UID.

FIG. 4 is a reference explanatory diagram of CP UID.

Compilation by the compiler 19 creates a translation unit list for the six objects 5. This set of translation units includes the native variable base index for the native interface between the object 5 and the library. As described above, the unique ink face is allocated as a continuous area to the static area of the data section 7. Therefore, by knowing the base point, the CPU ID can be referenced during execution.

FIG. 5 is a diagram showing an example of optimization.

The source program 16 is written in FORTRAN2.
It includes one 00 sentence as shown.

After this 00 sentence is vectorized, it is recognized by the multiple object generation unit 24 and the multiple object; -h L
+ 1'L-White! hi+, = DiF-'I 6h
A plurality of instruction sequences 12', 13' and I4' of contents are generated. Also, rlF (CPUI
D, EQ, VI'2400) THEN, an execution route selection means which was not present in the source program E6 is added. In addition, in Figure 2, rVP2400J and rVr'
2600" is the CPU ID.

Next, each of the plurality of instruction sequences 12', 13', and 14' is converted into instruction sequences 12, 13, and 14 suitable for the CPU ID by the hardware dependent optimization unit 25.

On the other hand, during execution, MF (CPUID + EQ.

)TIIEN, the only execution route is selectively executed.

In the above embodiments, an example has been described in which the compiler 19 automatically generates an object 5 suitable for optimization, as shown in FIG.

The object 5 may be obtained by adopting a configuration suitable for optimization in the source program 16'.

That is, three means are provided in the source program 16'.

First, the service routine GET that retrieves the CPU ID
Means of calling CPUID rCALLCETCPUID
(CPUID)J is provided.

As a result, the one type setting library 6 is directly or indirectly called. The variable CPUID is an integer type variable, and the type setting library 6 is
PUID + Existence Second, there is a method for specifying the optimization range and performing hardware-dependent optimization within that range.
A CPU (CPUID)J is provided. The specified range is ``rTOTAL'', which specifies the entire program.
"LooPJ" to specify a small loop, rsT to specify a statement
MTJ can be used and the range can be as desired. Also, r(CPUID)J
Specify UrD.

Third, 7 DO statements and the like are multiplexed in advance in the source program 16'.

By compiling the source program 16' as described above, it is possible to obtain substantially the same object as the object 5. The compiler for this purpose is
Among the optimization processing units 22, the hardware-dependent optimization unit 25
It is good if you have the following.

CPUID extraction unit 23 and multiple object generation unit 25
is not necessary. That is, by the first means, CP is
The UID can be retrieved and by a third means, the DO
A means of multiplexing statements and selecting a unique execution route is provided. Further, by using the second means, the hardware-dependent optimization unit 25 only needs to perform the instructed optimization for each multiplexed DO statement.

Although the present invention has been described above with reference to embodiments, the present invention can be modified in various ways according to its gist.

〔Effect of the invention〕

As explained above, according to the present invention, in the optimal object selection execution processing method, objects are multiplexed and the called CPU ID +, f-, L-7''1
;°<+u, tL double bow ζ (low?-IMbrwhh4r
1 depending on the type of hardware running Duram.

Since the optimal object can be selected and executed, one program can perform optimal processing for each model, and the load module can be made common to each model.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention. FIG. 2 is an explanatory diagram of the compiler. FIG. 3 is an explanatory diagram of the object interface. FIG. 4 is a CPUID reference explanatory diagram. FIG. 5 is a diagram showing an example of optimization. FIG. 6 is an explanatory diagram of another embodiment. 3 is a computer hardware, 4 is a load module, 5 is an object, 6 is a type setting library, 7 is a data section 8 of the object 5, is an object interface, 9 is an instruction section of the object 5, 10 is a type extraction instruction section, 11 It is a sequence of instructions.

Claims (1)

[Claims] A plurality of computer hardware of different types (1, 2
, 3) and a load module (4) common to the plurality of computer hardware (1, 2, 3), an object interface (8) for setting the type.
), a multiple object (11) including a plurality of instruction sequences with the same contents optimized according to each of the types, and a type setting library (6) for setting the type to the object interface (8); Type fetch command section (10) for calling the type setting library (6)
is provided in the load module (4), and when the load module (4) is executed by any of the plurality of computer hardware (1, 2, 3), it is called by the type retrieval instruction unit (10). The type setting library (6) sets the type in the object interface (8), and the multiple object (11) refers to the set type and executes multiple instruction sequences of the multiple object (11). An optimal object selection execution processing method characterized by selecting and executing a sequence of instructions according to the set type.