JPH03177072A - Semiconductor device and its manufacture - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Summary) Regarding a semiconductor device and its manufacturing method, patterning of parts that will eventually become transistor regions, such as source, drain, and gate for MOS transistors, and emitter, collector, and base formation for bipolar transistors. This process is performed before the bonding process to provide a sufficient stopper surface when thinning the element substrate, to make the thickness of the thin film uniform, and to obtain uniform and stable transistor characteristics. A semiconductor device in which an insulating film is formed on the back side of a substrate, and an element substrate is thinned from the front side with the insulating film adhered to a support substrate, the semiconductor device being formed by etching from the back side of the element substrate. A trench with a constant depth and a channel region with a constant film thickness formed between adjacent trenches, which are made up of a sidewall portion closed by the insulating film and a bottom wall portion closed by the insulating film, and a groove with a constant depth that is open on the front side of the element substrate. The width of the channel region in the direction adjacent to the political situation is configured to be smaller than the film thickness of the channel region, or the back side of the element substrate is etched along the outer periphery of a predetermined channel region to form the element substrate. a step of forming a groove with a constant depth on the back side of the element substrate, a step of embedding a buried layer to serve as a stopper when thinning the element substrate due to political circumstances, and a step of covering the buried layer and the back side of the element substrate. A step of forming an insulating film, a step of adhering the insulating film to a support substrate and laminating the element substrate to the support substrate, and using the buried layer as a bar on the surface side of the element substrate. A step of thinning the element substrate while leaving a predetermined channel region with a constant film thickness, and a step of removing the buried layer of the element substrate by etching to form a groove having a bottom wall portion and side wall portions made of an insulating film. or,
The method is configured to include a step of doping impurity ions into a predetermined transistor region adjacent to the channel region prior to the step of bonding the substrate and the support substrate together.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a method for manufacturing the same that can make the film thickness uniform when thinning an element substrate of a bonded wafer.

In recent years, there has been an increase in the integration, functionality, and speed of ICs and other products due to miniaturization, and with regard to microfabrication, it is now possible to draw minute patterns by increasing the speed and clarity of electron beam exposure equipment. Since it is becoming 0
．． A high-speed device structure with active elements of 1 μm or less is required. On the other hand, if only the pattern is miniaturized, there is a problem that signal delay occurs due to an increase in capacitance and resistance with the semiconductor substrate.For example, a 5OI (silicon on insulator) structure using a thin film of semiconductor crystal is effective for this problem. It is known to thin the element substrate (element forming layer) of a bonded wafer.

[Conventional technology]

A conventional semiconductor device of this type and its manufacturing method will be explained based on the drawings.

FIGS. 6(a) to 6(c) show a conventional method for manufacturing a semiconductor device.
It is a figure explaining an example of.

In the figure, 31 is an element substrate made of Si, for example;
2 is a support substrate made of Si, for example, and 33 is an element substrate 31.
34 is an oxide film that covers the back surface 31a of the element substrate Fi 31, and is provided in an empty area or dicing line where a transistor is not formed, and is spaced at intervals of several μm or more and serves as a stopper during etching or polishing; 35 is a stopper layer 34; This is a groove to embed.

Next, the manufacturing method will be explained.

First, as shown in FIG. 6(a), after forming a groove 35 of a predetermined depth in the vacant area or dicing line from the back surface 31a side of the element substrate 31 by etching, for example,
A stopper layer 34 for thinning the element substrate 31 made of an oxide film or other insulating material is embedded in the VD method and RIE in the 135, and an oxide film 33 is further formed on the element substrate 31.
form. Next, as shown in FIG. 6(b), the element substrate 31 and the support substrate 32 are overlapped and bonded together, for example, by thermal bonding. Next, as shown in FIG. 6(C), the element substrate 31 is thinned by etching or polishing from the back surface 31b side, and when the back surface 31b reaches the stopper layer 34, due to the difference in selectivity, etc., the element substrate 31 is thinned by etching or polishing. The polishing is stopped, and the element substrate 31 is thinned to a thickness corresponding to the thickness of the stopper layer 34.

[Problem to be solved by the invention]

However, in such conventional semiconductor devices and their manufacturing methods, the manufacturing of bonded wafers consists of the steps of oxidation, bonding, and polishing, and the wafer process (device fabrication process) comes after that. Based on this fixed idea, the stopper layer 34 has been provided in the empty area or on the dicing line so as not to hinder the patterning of various elements. Therefore, the stopper layer 34
can only be formed at intervals of several μm or more in the lateral direction (for example, in a square lattice), and because the stopper area is insufficient, it is difficult to make the thin film uniform to 0.1 μm or less when thinning. It was difficult to obtain uniform and stable transistor characteristics.

Therefore, in the present invention, the patterning process of the parts that will eventually become the transistor region (ie, the source, drain, and gate for a MOS) transistor, and the emitter, collector, and base for a bipolar transistor is performed before the bonding process. The purpose is to provide a sufficient stopper during the process, to make the thickness of the thin film uniform, and to obtain uniform and stable transistor characteristics.

[Means to solve the problem]

In order to achieve the above object, the semiconductor device according to the first invention has the following features:
A semiconductor device in which an insulating film is formed on the back side of an element substrate, and the element substrate is thinned from the front side with the insulating film adhered to a support substrate, and the element substrate is etched from the back side. a groove with a constant depth that is open on the front surface side of the element substrate, and a channel region with a constant film thickness formed between adjacent grooves; , and is characterized in that the width of the channel region in the direction adjacent to the political situation is smaller than the film thickness of the channel region.

In order to achieve the above object, a method for manufacturing a semiconductor device according to a second aspect of the present invention includes etching the back side of a substrate along the outer periphery of a predetermined channel region to form a groove of a constant depth having a side wall on the back side of the element substrate. a step of embedding a buried layer that will serve as a stopper when thinning the element substrate due to political circumstances; a step of forming an insulating film that covers the buried layer and the back side of the element substrate; and a step of forming the insulating film on a support substrate. a step of attaching the element substrate to a support substrate by adhering it to the supporting substrate; and a step of thinning the element substrate by leaving the predetermined channel region at a constant film thickness by using the buried layer as a stone bar on the front side of the element substrate. and a step of removing the buried layer of the element substrate by etching to form a trench having a bottom wall portion and side wall portions made of an insulating film.

Further, the second aspect of the present invention is characterized by including a step of doping impurity ions into a predetermined transistor region adjacent to the channel region, prior to the step of bonding the element substrate and the support substrate together.

In the present invention, it is preferable that the channel region 5 of the transistor has a constricted shape such that the width is minimum at the center in the direction in which the groove 4 extends. Furthermore, methods for thinning the film include selective etching, polishing, or a combination of these methods.

[Effect]

In the first invention, the channel region 5 is formed between the grooves 4 formed in the element substrate 1, and the width of the channel region 5 in the direction adjacent to the grooves 4 is formed to be smaller than the film thickness of the channel region 5. . Therefore, it is possible to embed a stopper during thinning into the wide groove 4, and it is possible to ensure a sufficient area of the best sover compared to the conventional method and to make the thickness of the thin film uniform. Further, by forming an active element on the element substrate l using a layer in the narrow channel region 5 as an electron channel, it is possible to obtain uniform and stable transistor characteristics.

In the second invention, a groove 11 is formed along the outer periphery of the channel region 5 prior to bonding the element substrate l and the support substrate 3, and a buried layer 12 is embedded in the substrate 11 to serve as a stopper when thinning the film. After bonding the element substrate 1 and the support base vi3, the channel region 5 is thinned to a constant thickness using the buried layer 12, and then the buried layer 12 is removed. Therefore, by performing patterning using a mask pattern for each type before the bonding process, a sufficient area of the buried layer 12 can be ensured and the film thickness can be made uniform. Moreover, the semiconductor layer remaining in the channel region 5 can be controlled by thermal oxidation from the left and right sides of the channel region 5 due to the trench 4 from which the buried layer 12 has been removed.

Furthermore, in the second invention, the element substrate l and the support base +ffl
3, doping impurity ions into the transistor region 6 adjacent to the channel region 5,
Thin film ICs can be formed laterally.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 5 are diagrams showing an embodiment of a semiconductor device and its manufacturing method according to the present invention, FIG. 1(a) is a cross-sectional view showing the structure of the semiconductor device, and FIG. 1(b) is a A perspective view of the main part of the element substrate, FIGS. 2(a) to 2(c) are diagrams explaining the manufacturing method, and FIGS. 3 to 5 show the mode when an MO3 type element is formed on the element substrate. 3 is a perspective view of essential parts of the element substrate, FIG. 4 is a plan view thereof, and FIG. 5 is a plan view showing a modified form thereof.

In FIGS. 1 to 4, 1 is an element substrate made of, for example, Si (silicon), 2 is an insulating film made of, for example, Stow, formed on the back side la of the element substrate 1, and 3 is bonded to the back side 1a of the element substrate 1. 4 is a plurality of grooves formed in the element substrate 1; 5 is a channel region formed between adjacent grooves 4; 6. are transistor regions forming a source 6S and a drain 6D adjacent to both sides of the channel region 5; 7 is a gate electrode made of, for example, polysilicon or tungsten; and 8 is a gate oxide film made of, for example, 5iQz. The element substrate 1 is selectively thinned from the surface 1b side by notching or polishing while being adhered to the support substrate 3, and the film thickness T is, for example, 0.
．． It is 2 μm. The groove 4 is open on the surface lb of the element substrate 1, and the groove 4 has a side wall 4a formed by etching from the back surface 1a of the element substrate 1 and a bottom wall 4b closed by the insulating film 2. have. Further, the width W of the channel region 5 in the direction in which the grooves 4 are adjacent to each other is, for example, 500 mm.
The thickness is from 1,000 to 1,000, which is smaller than the film thickness T of the channel region 5.

Next, the manufacturing method will be explained.

First, as shown in Figure 2(a), the thickness is, for example, 500 μm.
Processing by photolithography is performed on the rear surface la side of the element substrate 1 having a diameter of about m. That is, the resist is patterned using a stencil pattern reduction transfer method using an electron beam,
Leaving the channel region 5 that forms the gate and channel of the transistor, etching is performed around it.
A groove 11 having a constant depth of, for example, 0.2 μm is formed. Next, a thin protective oxide film (not shown) is formed in this groove 11, and an oxide film or 5OG (
A buried layer 12 made of spin-on glass (alcohol compound of silicon) is buried, and impurity ions such as As are doped to form a source 6S and a drain 6D in the transistor region 6 adjacent to the channel region 5. An insulating film 2 covering the back side la of the substrate 1 is formed.

Next, as shown in FIG. 2(b), the Si of the supporting substrate 3 is
The surface (or oxide film) and the insulating film 2 side of the element substrate 1 are overlapped, and a pulse voltage of about IKV is applied between both substrates 1.3 under an appropriate atmospheric pressure and heated to about 800°C to form the insulating film 2. The element substrate 1 and support substrate 3 on which are formed are bonded together. Next, as shown in FIG. 2(C), the surface lb side of the element substrate 1 is etched or polished to make the element substrate 1 thin. At this time, the buried layer 12 acts as a stopper due to the difference in selectivity between the Si of the element substrate 1 and the buried layer 12 in the trench 11, and a constant film thickness corresponding to the thickness of the buried layer 12 (
For example, a channel region 5 and a transistor region 6 having a thickness of 0.2 μm are formed. Next, when the buried layer 12 is removed by etching, for example, RIE, the state shown in FIG. 1(a) is obtained. - At this time, the groove 4 opens on the surface lb of the element substrate 1, but? Since an oxide film is formed on the side wall portion 4a of s4, this is removed next, and a gate oxide film 8 is formed again.
Grow about 0 people. Next, when the gate electrode 7 is formed as shown in Fig. 3.4, MO3 made of thin Si crystal is formed.
Mold elements are created laterally. In addition, groove 4 has a CV
A semiconductor device is completed by embedding an insulating film such as Sin using the D method or the like, and further forming an insulating film, a contact hole, a wiring layer, a cover film, etc.

As described above, in this embodiment, the thinning process, which was conventionally performed before patterning of various elements, is performed after patterning of a predetermined element, and the stopper embedding space, which was conventionally available only in empty areas such as dicing lines, is now performed. is the majority of the area around the channel region 5 excluding the silicon of 1,000 to 500 people, and the buried layer 12 made of oxide film or SOG is buried in this space, in addition to the advantages of conventional SOI. Therefore, when thinning the element substrate l, a sufficient stopper area can be ensured, and uniformity of the film thickness within 300 mm can be achieved. A thin St layer 5a having a width of at least 100 layers can be formed with a very narrow lateral width, and a sor active element using this Si layer 5a as a lateral two-dimensional electron channel can be formed to produce LSI circuits, etc. that have uniform and stable transistor characteristics. can be realized.

Furthermore, in the three-dimensional state, the energy ranks of the electrons in the Si crystal were distributed almost continuously, whereas in the two-dimensional crystal (
500 Å to 300 Å) state, the quantum order becomes discrete, so there are fewer opportunities for electrons flowing through the electron channel 5c of the channel region 5 to be scattered, and an increase in electron velocity can be expected. Furthermore, as shown in FIG. 4, since the electric field has equipotential lines perpendicular to the electron channel 5c from the Si conductive portion of the channel region 5 to the gate, hot electrons accelerated by the electric field reach the gate oxide film 8. This prevents the gate oxide film 8 from being implanted and deteriorating it, and also prevents the life from being shortened.

Note that if the Sin island consisting of the channel region 5 and the transistor region 6 is thin and low impedance cannot be obtained when the gate voltage is positive, it is appropriate to connect multiple islands in parallel as shown in FIG. Therefore, Si
Even when the width of the n-island is widened, the stoppers for thinning can be provided sufficiently densely, which is effective. Furthermore, if alignment marks for patterning of the second layer and subsequent layers are formed at the same time when forming the dug pattern of the first layer of the element substrate 1, pattern overlay accuracy can be improved. can.

〔Effect of the invention〕

According to the present invention, the stoppers in the thinning process can be provided densely and with a sufficient area, so that the thickness of the element substrate to be thinned can be made uniform, and uniform and stable transistor characteristics can be obtained. can. Furthermore, a channel region having a very narrow width can be formed on the element substrate, and a high-speed and highly reliable semiconductor device can be manufactured.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining an embodiment of a semiconductor device and a method for manufacturing the same according to the present invention, FIG. 1(a) is a cross-sectional view of the semiconductor device of one embodiment, and FIG. 1(b) is a perspective view of the main part of the element substrate, Figures 2(a) to (C) are diagrams explaining the manufacturing method of one embodiment, and Figures 3 to 5 are diagrams of the case where an MO3 type element is formed on the element substrate. FIG. 3 is a perspective view of the main part of the element substrate, FIG. 4 is a plan view of the main part, and FIG. 5 is a plan view showing a modification thereof. FIGS. 6A to 6C are diagrams illustrating an example of a conventional method for manufacturing a semiconductor device. ■...Element substrate, 1a...Back surface, 1b...Front surface, 2...Insulating film, 3...Support substrate, 4. ... Groove, 5 ... Channel region, 6 ... Transistor region, 7 ... Gate electrode, 11 ... Groove, 12 ... ...buried layer, T...film thickness, W...width. 6: A perspective view of the main parts of the element substrate of an embodiment of the transistor region (Fig. (1)) Fig. 3 A perspective view of the main parts showing the mode when an MO3 type element is formed

Claims (3)

[Claims] (1) Insulating film (2) on the back side (1a) of the element substrate (1)
is formed, and the element substrate (1) is thinned from the front surface (1b) side with the insulating film (2) adhered to the support substrate (3), the element substrate (1) The side wall portion (4a) and the insulating film (2) formed by etching from the back surface (1a) side of the
It consists of a bottom wall portion (4b) closed by an element substrate (
1) has a groove (4) with a constant depth that is open on the surface side, and a channel region (5) with a constant thickness formed between adjacent grooves (4), A semiconductor device characterized in that a width of a channel region (5) in an adjacent direction is smaller than a film thickness of the channel region (5). (2) Etching the back surface (1a) side of the element substrate (1) along the outer periphery of a predetermined channel region (5) to
) forming a groove (11) with a constant depth having a side wall (4a) on the back surface (1a) of the substrate, and embedding the groove (11) to serve as a stopper when thinning the element substrate (1). a step of embedding the layer (12); and the embedding layer (12) and the back surface (1a) of the element substrate (1).
A step of forming an insulating film (2) covering the side, and adhering the insulating film (2) to a supporting substrate (3) to form an element substrate (
1) on the support substrate (3), and the step of laminating the buried layer (1) on the surface (1b) side of the element substrate (1).
2) as a stopper to reduce the thickness of the device substrate (1) by leaving the predetermined channel region (5) at a constant thickness; and
) by etching to form a groove (4) having a bottom wall (4b) and a side wall (4a) made of an insulating film (2). . (3) Prior to the step of bonding the substrate (1) and the supporting substrate (3), the method includes a step of doping impurity ions into a predetermined transistor region (6) adjacent to the channel region (5). A method for manufacturing a semiconductor device according to claim 2.