JPH03177055A - Substrate for mounting semiconductor element - Google Patents
Substrate for mounting semiconductor elementInfo
- Publication number
- JPH03177055A JPH03177055A JP1316076A JP31607689A JPH03177055A JP H03177055 A JPH03177055 A JP H03177055A JP 1316076 A JP1316076 A JP 1316076A JP 31607689 A JP31607689 A JP 31607689A JP H03177055 A JPH03177055 A JP H03177055A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- base
- mounting
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 40
- 239000000758 substrate Substances 0.000 title description 13
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85385—Shape, e.g. interlocking features
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子搭載用基体に関し、特に詳細には、
搭載すべき半導体素子と電気的接続を図るための電極部
に特徴のある半導体素子搭載用基体に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a substrate for mounting semiconductor elements, and in particular,
The present invention relates to a substrate for mounting a semiconductor element, which is characterized by an electrode part for electrically connecting the semiconductor element to be mounted.
半導体素子搭載用基体の一例として、特開昭64−28
830号公報に示されるものがある。As an example of a substrate for mounting semiconductor elements, JP-A-64-28
There is one shown in Publication No. 830.
この文献に示される基体で、その基体上に半導体素子を
搭載するための凹部を備え、凹部の半導体素子に隣接す
る部分が面取されている。このような面取りを行うこと
により、半導体素子と基体との間の電気的接続の断線等
を防止している。そして、半導体素子と電気的接続を行
うための電極パッドは、基体の上面に設けられている。The base body disclosed in this document includes a recessed portion for mounting a semiconductor element on the base body, and a portion of the recessed portion adjacent to the semiconductor element is chamfered. By performing such chamfering, disconnection of the electrical connection between the semiconductor element and the base body is prevented. Electrode pads for making electrical connections with the semiconductor element are provided on the upper surface of the base.
しかし、上記文献の半導体素子搭載用基体では、先に説
明したように、基体の上面に電極用のポンディングパッ
ドが設けられているため、電気的接続を行うにはワイヤ
を垂直上方に引き上げなければならない。そのため接続
したワイヤが上方に突出し、その形状が凸状となり、半
導体素子搭載用基体の上面へワイヤが突出し、この半導
体素子搭載用基板を使用する半導体装置では、この基体
に蓋等をするとき、このワイヤに触れないように余裕を
もって取り付けたりしなければならず、このような半導
体素子搭載用基体を有する半導体装置では、その高さ、
厚さを薄くすることが難しかつく、また、ワイヤの突出
した部分が他の部材等に接触し、ワイヤが切断され、製
造歩留を高くすることが難しかった。However, in the substrate for mounting semiconductor elements in the above-mentioned document, as explained earlier, a bonding pad for electrodes is provided on the top surface of the substrate, so the wire must be pulled vertically upward to make an electrical connection. Must be. Therefore, the connected wires protrude upward and have a convex shape, and the wires protrude to the upper surface of the semiconductor element mounting substrate.In a semiconductor device using this semiconductor element mounting substrate, when a lid or the like is placed on the substrate, It is necessary to attach the wire with enough allowance to avoid touching it, and in a semiconductor device having such a base for mounting a semiconductor element, its height,
It was difficult to reduce the thickness, and the protruding portion of the wire came into contact with other members, causing the wire to be cut, making it difficult to increase the manufacturing yield.
本発明は上記課題を解決することができる半導体素子搭
載用基板を提供することを目的とする。An object of the present invention is to provide a substrate for mounting a semiconductor element that can solve the above problems.
本発明の半導体素子搭載用基体は、上面と、上面に設け
られ半導体素子をその中に搭載するための凹部と、この
凹部の側壁部に設けられ、上面に対して傾斜した傾斜面
と、傾斜面に形成され、搭載すべき半導体素子と電気的
接続するための電極パッドとを備えたことを特徴とする
。The substrate for mounting a semiconductor element of the present invention has an upper surface, a recess provided on the upper surface for mounting a semiconductor element therein, an inclined surface provided on a side wall of the recess and inclined with respect to the upper surface, and It is characterized by comprising electrode pads formed on the surface for electrical connection with the semiconductor element to be mounted.
上記のように構成したことにより、本発明の半導体素子
搭載用基板では、電気接続用の電極領域がその上面に対
して傾斜している。このため、この電極パッドに接続さ
れるワイヤは、上面に対して斜め方向に立ち上がり、接
続したワイヤの最頂部の高さを低くすることができる。With the above configuration, in the semiconductor element mounting substrate of the present invention, the electrode region for electrical connection is inclined with respect to the upper surface thereof. Therefore, the wire connected to this electrode pad rises obliquely with respect to the upper surface, and the height of the top of the connected wire can be reduced.
以下図面を参照しつつ本発明に従う実施例について説明
する。Embodiments according to the present invention will be described below with reference to the drawings.
同一符号を付した要素は同一機能を有するため重複する
説明は省略する。Elements with the same reference numerals have the same functions, so duplicate explanations will be omitted.
第1図は本発明に従う一実施例である半導体素子搭載用
基体1(以下、基体という)の斜視外観を示す。この第
1図では、半導体素子搭載用基体内に半導体素子を搭載
した状態を示している。また、第2図は第1図に示す半
導体素子搭載用基体の断面図を示す。FIG. 1 shows a perspective external appearance of a semiconductor element mounting base 1 (hereinafter referred to as the base) which is an embodiment according to the present invention. FIG. 1 shows a state in which a semiconductor element is mounted within a semiconductor element mounting base. Further, FIG. 2 shows a cross-sectional view of the semiconductor element mounting base shown in FIG. 1.
第1図に示すように、基体1は略直方体形状をしており
、その上面2には、半導体素子3を内部に搭載するため
の凹部4が設けられている。凹部4の側壁5は上面2に
対して傾斜しており、この傾斜面5上には電極パッド6
が形成されている。As shown in FIG. 1, a base 1 has a substantially rectangular parallelepiped shape, and a recess 4 for mounting a semiconductor element 3 therein is provided on its upper surface 2. As shown in FIG. A side wall 5 of the recess 4 is inclined with respect to the upper surface 2, and an electrode pad 6 is disposed on this inclined surface 5.
is formed.
この電極パッド6は、上面2に形成された配線パターン
7に電気的に接続されている。一方電極パッド6は凹部
4内にダイボンディングされた半導体素子3の電極パッ
ド8にワイヤボンディング10にて電気的に接続されて
いる。また、第2図に示すように、基体1内には貫通穴
9が形成されており、この貫通穴9には導電ピン11が
挿入されている。この貫通穴9の内面9aには、金属面
9bが形成されており、導電ピン11の外面と電気的に
接続されている。この金属面9bは、基体1の上面2に
形成された配線パターン7に第1図及び第2図に示すよ
うに電気的に接続されている。This electrode pad 6 is electrically connected to a wiring pattern 7 formed on the upper surface 2. On the other hand, the electrode pad 6 is electrically connected to the electrode pad 8 of the semiconductor element 3 die-bonded in the recess 4 by wire bonding 10 . Further, as shown in FIG. 2, a through hole 9 is formed in the base body 1, and a conductive pin 11 is inserted into this through hole 9. A metal surface 9b is formed on the inner surface 9a of the through hole 9, and is electrically connected to the outer surface of the conductive pin 11. This metal surface 9b is electrically connected to the wiring pattern 7 formed on the upper surface 2 of the base 1, as shown in FIGS. 1 and 2.
シタがって、半導体素子チップ3の電極パッド8は、ボ
ンディングワイヤ10、電極パッド6、配線パターン7
、金属面9b及び導電ピン11を介して、外部の装置と
電気的に接続可能となっている。このような基体1は、
セラミックの場合には型に入れ焼き固めたり、またプラ
スチック等の場合には、所定の型に材料を注入すること
により簡単に製作することができる。電極パッド、電気
配線パターン等は従来より知られている製造方法により
容易に形成することができる。又、この基体の製造方法
はこれに限定されず、従来の垂直な側壁を有する凹部を
備えた基体の側壁部を斜めに削除し、傾斜した側壁部を
形成してもよい。Turning to the side, the electrode pad 8 of the semiconductor element chip 3 includes the bonding wire 10, the electrode pad 6, and the wiring pattern 7.
, can be electrically connected to an external device via the metal surface 9b and the conductive pin 11. Such a base 1 is
In the case of ceramic, it can be easily manufactured by putting it in a mold and baking it, and in the case of plastic, it can be easily manufactured by pouring the material into a predetermined mold. Electrode pads, electrical wiring patterns, etc. can be easily formed by conventionally known manufacturing methods. Further, the manufacturing method of this base body is not limited to this, and a side wall portion of a conventional base body having a recessed portion having a vertical side wall may be obliquely removed to form an inclined side wall portion.
上記のような基体1の凹部4内に半導体素子3を凹部4
内にグイボンディングし、この半導体素子3の電極パッ
ド8と基体1の電極パッド6とをボンディングワイヤ1
0にて接続する。ここで、第1図及び第2図に示すよう
に、ワイヤを基体1の電極パッド8に対して垂直に立ち
上げたとしても、電極パッド8が上面2に対して傾斜し
ているため、ボンディングワイヤ10は基体1の上面2
の上に突出しない。したがって、この基体1の凹部を覆
うように蓋(図示せず)をかぶせても、ボンディングワ
イヤ10は蓋の下面に接触せず、従来必要であったワイ
ヤ突出分の余裕空間を設ける必要がない。そのため、こ
のような基体を備えた半導体装置では、その厚さを薄く
することが可能になる。The semiconductor element 3 is placed in the recess 4 of the base 1 as described above.
The electrode pads 8 of the semiconductor element 3 and the electrode pads 6 of the base 1 are connected with the bonding wire 1.
Connect at 0. Here, as shown in FIGS. 1 and 2, even if the wire is raised perpendicularly to the electrode pad 8 of the base 1, since the electrode pad 8 is inclined with respect to the upper surface 2, the bonding The wire 10 is connected to the upper surface 2 of the base 1
Do not protrude above. Therefore, even if a lid (not shown) is placed over the concave portion of the base 1, the bonding wire 10 does not come into contact with the bottom surface of the lid, and there is no need to provide an extra space for the wire protrusion, which was required in the past. . Therefore, it is possible to reduce the thickness of a semiconductor device including such a base.
また、第3図に示すように、ワイヤボンディングの密度
を高くするため、凹部の傾斜した側壁上に電極パッドを
多段構造に形成することもできる。Further, as shown in FIG. 3, in order to increase the density of wire bonding, electrode pads can be formed in a multi-stage structure on the inclined sidewalls of the recess.
このような場合にも、先に説明したように、ボンディン
グされたワイヤは基板の接続部よりも上部に出ないため
、その上の段のワイヤボンディング作業において下側の
ボンディングワイヤが邪魔にならず作業効率を高くする
ことができる。Even in this case, as explained earlier, the bonded wire does not protrude above the connection part of the board, so the lower bonding wire does not get in the way of the wire bonding work on the upper stage. Work efficiency can be increased.
本発明は上記実施例に限定されず種々の変形例が考えら
れ得る。The present invention is not limited to the above embodiments, and various modifications may be made.
例えば、上記実施例では、凹部内の傾斜した側壁部が凹
部の両側のみに設けられているが、側壁部会てが傾斜し
ていてもよく、また、側壁の一部のみが傾斜し、そこに
電極パッドを設けるようにしてもよい。For example, in the above embodiment, the inclined side wall portions in the recess are provided only on both sides of the recess, but all the side wall portions may be sloped, or only a part of the side wall is sloped, and there An electrode pad may also be provided.
又、上記実施例では側壁部が直線状に傾斜しているが、
湾曲状に傾斜していてもよい。Further, in the above embodiment, the side wall portion is sloped linearly, but
It may be inclined in a curved manner.
本発明の半導体素子搭載用基体では、先に説明したよう
に、その電極パッドが傾斜しているため、そこに搭載す
る半導体素子との電気的接続を行うワイヤの最頂部の高
さを低くすることができる。As explained above, in the substrate for mounting a semiconductor element of the present invention, since the electrode pad is inclined, the height of the top of the wire that makes an electrical connection with the semiconductor element mounted there is reduced. be able to.
したがって、この半導体素子搭載用基体を使用した半導
体装置では、その厚さを薄くすることができ、かつその
製造歩留まりを高く保つことができる。Therefore, a semiconductor device using this semiconductor element mounting base can be made thinner, and its manufacturing yield can be kept high.
第1図は本発明に従う一実施例の半導体素子搭載用基体
の斜視外観図、第2図は第1図に示す半導体素子搭載用
基体の断面図、及び第3図は本発明に従う別の実施例の
断面図である。
1・・・基体、2・・・上面、3・・・半導体素子、4
・・・凹部、5・・・側壁、6.8・・・電極パッド、
7・・・配線パターン。FIG. 1 is a perspective external view of a semiconductor element mounting base according to an embodiment of the present invention, FIG. 2 is a sectional view of the semiconductor element mounting base shown in FIG. 1, and FIG. 3 is another embodiment according to the present invention. FIG. 3 is an example cross-sectional view. DESCRIPTION OF SYMBOLS 1... Base body, 2... Upper surface, 3... Semiconductor element, 4
... recess, 5... side wall, 6.8... electrode pad,
7...Wiring pattern.
Claims (1)
るための凹部と、 前記凹部の側壁部に設けられ、前記上面に対して傾斜し
た傾斜面と、 この傾斜面に形成され、搭載すべき半導体素子と電気的
接続するための電極とを備えた半導体素子搭載用基体。[Scope of Claims] An upper surface; a recess provided on the upper surface for mounting a semiconductor element therein; an inclined surface provided on a side wall of the recess and inclined with respect to the upper surface; A base for mounting a semiconductor element, which is formed and includes a semiconductor element to be mounted and an electrode for electrical connection.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1316076A JPH03177055A (en) | 1989-12-05 | 1989-12-05 | Substrate for mounting semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1316076A JPH03177055A (en) | 1989-12-05 | 1989-12-05 | Substrate for mounting semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03177055A true JPH03177055A (en) | 1991-08-01 |
Family
ID=18072989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1316076A Pending JPH03177055A (en) | 1989-12-05 | 1989-12-05 | Substrate for mounting semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03177055A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996003020A1 (en) * | 1994-07-19 | 1996-02-01 | Olin Corporation | Integrally bumped electronic package components |
WO1998049726A1 (en) * | 1997-04-30 | 1998-11-05 | Hitachi Chemical Company, Ltd. | Board for mounting semiconductor element, method for manufacturing the same, and semiconductor device |
US6340842B1 (en) * | 1998-04-02 | 2002-01-22 | Oki Electric Industry Co., Ltd. | Semiconductor device in a recess of a semiconductor plate |
US6492203B1 (en) | 1997-04-30 | 2002-12-10 | Hitachi Chemical Company, Ltd. | Semiconductor device and method of fabrication thereof |
US6617193B1 (en) | 1997-04-30 | 2003-09-09 | Hitachi Chemical Company, Ltd. | Semiconductor device, semiconductor device substrate, and methods of fabricating the same |
KR100848609B1 (en) * | 2007-04-10 | 2008-07-28 | 조현귀 | Receiving space hot plate printed circuit board and its manufacturing method |
JP6024759B2 (en) * | 2012-11-19 | 2016-11-16 | 富士電機株式会社 | Semiconductor device |
-
1989
- 1989-12-05 JP JP1316076A patent/JPH03177055A/en active Pending
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5629835A (en) * | 1994-07-19 | 1997-05-13 | Olin Corporation | Metal ball grid array package with improved thermal conductivity |
WO1996003020A1 (en) * | 1994-07-19 | 1996-02-01 | Olin Corporation | Integrally bumped electronic package components |
KR100553281B1 (en) * | 1997-04-30 | 2006-02-22 | 히다치 가세고교 가부시끼가이샤 | Substrate for semiconductor device and semiconductor element mounting and manufacturing method thereof |
WO1998049726A1 (en) * | 1997-04-30 | 1998-11-05 | Hitachi Chemical Company, Ltd. | Board for mounting semiconductor element, method for manufacturing the same, and semiconductor device |
US6268648B1 (en) | 1997-04-30 | 2001-07-31 | Hitachi Chemical Co., Ltd. | Board for mounting semiconductor element, method for manufacturing the same, and semiconductor device |
CN100370602C (en) * | 1997-04-30 | 2008-02-20 | 日立化成工业株式会社 | Substrate for mounting semiconductor element, manufacturing method thereof, and semiconductor device |
US6492203B1 (en) | 1997-04-30 | 2002-12-10 | Hitachi Chemical Company, Ltd. | Semiconductor device and method of fabrication thereof |
US6617193B1 (en) | 1997-04-30 | 2003-09-09 | Hitachi Chemical Company, Ltd. | Semiconductor device, semiconductor device substrate, and methods of fabricating the same |
US6538322B2 (en) * | 1998-04-02 | 2003-03-25 | Oki Electric Industry Co., Ltd. | Semiconductor device in a recess of a semiconductor plate |
US7183132B2 (en) | 1998-04-02 | 2007-02-27 | Oki Electric Industry Co., Ltd. | Semiconductor device in a recess of a semiconductor plate |
US6340842B1 (en) * | 1998-04-02 | 2002-01-22 | Oki Electric Industry Co., Ltd. | Semiconductor device in a recess of a semiconductor plate |
KR100848609B1 (en) * | 2007-04-10 | 2008-07-28 | 조현귀 | Receiving space hot plate printed circuit board and its manufacturing method |
JP6024759B2 (en) * | 2012-11-19 | 2016-11-16 | 富士電機株式会社 | Semiconductor device |
US9728475B2 (en) | 2012-11-19 | 2017-08-08 | Fuji Electric Co., Ltd. | Lead portion of semiconductor device |
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