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JPH03171745A - Mount structure of hybrid integrated circuit - Google Patents

Mount structure of hybrid integrated circuit

Info

Publication number
JPH03171745A
JPH03171745A JP1308955A JP30895589A JPH03171745A JP H03171745 A JPH03171745 A JP H03171745A JP 1308955 A JP1308955 A JP 1308955A JP 30895589 A JP30895589 A JP 30895589A JP H03171745 A JPH03171745 A JP H03171745A
Authority
JP
Japan
Prior art keywords
conductor
gold
solder
hybrid integrated
barrier layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1308955A
Other languages
Japanese (ja)
Other versions
JP2830221B2 (en
Inventor
Hayami Sugiyama
早実 杉山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Priority to JP1308955A priority Critical patent/JP2830221B2/en
Publication of JPH03171745A publication Critical patent/JPH03171745A/en
Application granted granted Critical
Publication of JP2830221B2 publication Critical patent/JP2830221B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To improve electrical connection between a gold conductor and chip parts without causing the gold of the gold conductor to be absorbed into solder by forming a conductor pad which can be soldered onto the gold conductor without directly forming solder on the gold conductor. CONSTITUTION:A conductor pad 10 consisting of gold which can be soldered is formed on a gold conductor 5 through a barrier layer 11. Then, a lead frame 2 is fixed onto this conductor pad 10 by a solder 9. The material of the barrier layer 11 may be or may not be equal to that of a barrier layer 4, namely chrome, titanium, nickel, etc. In this manner, presence of the barrier layer 11 prevents gold of the gold conductor 5 from being absorbed into the solder 9, thus achieving a mount structure of a hybrid integrated circuit where adhesion of the chip parts to the substrate is large and electrical connection to the gold conductor is also stable.

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は、ハイブリッド集積回路（以下、ハイブリｙ
ドＩＣと称する。）の基板上に形成された金導体にチッ
プ部品をマウントする構造に関する。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to hybrid integrated circuits (hereinafter referred to as hybrid integrated circuits).
It is called a de-IC. ) relates to a structure in which chip components are mounted on a gold conductor formed on a substrate.

［従来の技術］ 前記のようなマウント構造として、次に示すような３つ
の構造のいずれかが従来用いられていた。[Prior Art] As the above-mentioned mount structure, one of the following three structures has been conventionally used.

（１）第２図（イ）に示すように、チップ部品１の下部
に形戊されたリードフレーム２と、基板３上にバリア金
属４を介して形成された金導体５とが導電性接着剤６で
接着されているマウント構造で、導電性接着剤６がチッ
プ部品Ｊの基板３への固定と同時に金導体５への電気的
接続の役目を成している。(1) As shown in FIG. 2(A), the lead frame 2 formed at the bottom of the chip component 1 and the gold conductor 5 formed on the substrate 3 via the barrier metal 4 are electrically bonded together. In the mounting structure, the conductive adhesive 6 serves to fix the chip component J to the substrate 3 and to electrically connect it to the gold conductor 5 at the same time.

（２）第２図（口）に示すように、チップ部品１と基板
３が絶縁性接着剤７で直接接着され、チ・ｙプ部品１の
上部に形成されたリードフレーム２に金ワイヤー８の一
端のそれぞれがワイヤボンディングされ、他端のそれぞ
れが基板３」二にバリア金属４を介して形成された金導
体５にワイヤボンデイングされているマウント構造で、
絶縁性接着剤７がチップ部品１の基板３への固定の役目
を成し、金ワイヤー８がチップ部品１−の金導体５への
電気的接続の役目を成している。(2) As shown in FIG. 2 (opening), the chip component 1 and the substrate 3 are directly bonded with an insulating adhesive 7, and the gold wire 8 is attached to the lead frame 2 formed on the top of the chip component 1. Each of one end is wire-bonded, and each of the other ends is wire-bonded to a gold conductor 5 formed on a substrate 3 through a barrier metal 4.
The insulating adhesive 7 serves to fix the chip component 1 to the substrate 3, and the gold wire 8 serves to electrically connect the chip component 1- to the gold conductor 5.

（３）第２図（ハ）に示すように、チップ部品１の下部
に形成されたリードフレーム２と、基板３上にバリア金
属４を介して形或された金導体５とがハンダ９で接続さ
れているマウント構造で、ハンダ９がチップ部品１の基
板３への固定と同時に金導体５への電気的接続の役目を
成している。(3) As shown in FIG. 2(c), the lead frame 2 formed at the bottom of the chip component 1 and the gold conductor 5 formed on the substrate 3 via the barrier metal 4 are bonded with solder 9. In the connected mounting structure, the solder 9 serves to fix the chip component 1 to the substrate 3 and at the same time to electrically connect it to the gold conductor 5.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、前記した従来の構造はそれぞれ次に示すような
欠点を有していた。However, each of the conventional structures described above has the following drawbacks.

■前記（１）の構造では、導電性接着剤６にフィラーと
呼ばれる銀などの導電性物質が添加されているため、接
着力が一般の接着剤に比べ著しく劣り、衝撃に弱くチッ
プ部品がμ板からはがれやすい。■ In the structure of (1) above, since a conductive substance such as silver called a filler is added to the conductive adhesive 6, the adhesive strength is significantly inferior to that of general adhesives, and the chip parts are weak against shock. Easy to peel off from the board.

■前記（２）の構造では、チップ部品へワイヤボンディ
ングできるリードフレームの゜材質が金などに限定され
ている。また、リードフレーム面と導体パターンに１１
以上の段差があるチ・ｙブ部品のリードフレームへのワ
イヤポンデイングモ困難で、汎用的でない。(2) In the structure (2) above, the material of the lead frame that can be wire-bonded to the chip component is limited to gold or the like. Also, the lead frame surface and conductor pattern have 11
Wire bonding to the lead frame of a chip/ybeam component with such a step difference is difficult and not universally applicable.

■前記（３〉の構造では、ハンダ付け時に金がハング中
に吸収される、いわゆるハンダ食われ現象が起こり、金
導体５の一部が消失してしまい、電気的接続が極めて不
安定になる。■In the structure described in (3) above, during soldering, gold is absorbed into the hanger, a so-called solder-eating phenomenon occurs, and a part of the gold conductor 5 disappears, making the electrical connection extremely unstable. .

そこで、この発明は、チップ部品の基板への接着強度が
弾ク、汎用的で、金導体との電気的接続も安定している
ハイブリッド集積回路のマウント構造を堤供することを
目的とする。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a mounting structure for a hybrid integrated circuit that has flexible adhesive strength to a substrate of a chip component, is versatile, and has a stable electrical connection with a gold conductor.

〔課題を解決するための手段〕[Means to solve the problem]

前記目的を達成するために、この発明のハイブリッド集
積回路のマウント構造は、前記ハイブリッド集積回路の
基板上に所定の間隔を保ち対向して配置された金導体の
上にハンダ付け司能な導体パッドが形成され、この導体
パッドとチップ部品の問にハンダ層が設けられ、このハ
ンダ局により前記導体パッドの上にチップ部品がマウン
トされているものである。In order to achieve the above object, the hybrid integrated circuit mounting structure of the present invention includes conductor pads that can be soldered onto gold conductors that are arranged facing each other at a predetermined distance on the substrate of the hybrid integrated circuit. A solder layer is provided between the conductor pad and the chip component, and the chip component is mounted on the conductor pad by the solder pad.

また、前記導体パッドの材料に金を用いたときは、この
導体パッドと前記金導体の間にバリア金属を形成すると
好適である。Further, when gold is used as the material of the conductor pad, it is preferable to form a barrier metal between the conductor pad and the gold conductor.

［実施例］ 第１図はこの考案の一実施例を示す断面図で、この図中
、第２図（ハ）と同一の符号を付したものは第２図（ハ
）と同様の構成を示す。[Example] Fig. 1 is a sectional view showing an embodiment of this invention. In this figure, the same reference numerals as in Fig. 2 (c) indicate the same configuration as in Fig. 2 (c). show.

１０はハンダ付け可能な金を材料とした導体パ・ｙドで
、バリア層１１を介して金導体５上に形成されている。Reference numeral 10 denotes a solderable conductor pad made of gold, which is formed on the gold conductor 5 with a barrier layer 11 in between.

そして、この導体バ・ｙド１０の上にＪ−ドフレーム２
がハンダって固定されている。Then, on top of this conductor bar y-board 10, a J-board frame 2 is placed.
is fixed by soldering.

なお、バリア層１１の材質はバリア層４の材質と同一で
も異なってもよく、具体的にはクロム、チタン、ニッケ
ル等が適用できる。Note that the material of the barrier layer 11 may be the same as or different from the material of the barrier layer 4, and specifically, chromium, titanium, nickel, etc. can be used.

［作用］ 以上の構成において、金導体５にパリア金［１１を介し
て形成され電気的にも接続されている導体ハッド１０の
上に、ハンダ９によりリードフレーム２を介してチップ
部品１が固定されて電気的にも接続されているので、結
果的に、チップ部品１は基板３に固定されて金導体５と
電気的に接続されている。ところで、ハンダ付け時に導
体パッド１０の金はハンダ９中に吸収されることがあっ
ても、バリア層１１の存在により金導体５の金がハンダ
９中に吸収されることはない。[Function] In the above configuration, the chip component 1 is fixed via the lead frame 2 by the solder 9 on the conductor had 10 which is formed on the gold conductor 5 via the pariah gold 11 and is also electrically connected. As a result, the chip component 1 is fixed to the substrate 3 and electrically connected to the gold conductor 5. Incidentally, even though the gold of the conductor pad 10 may be absorbed into the solder 9 during soldering, the presence of the barrier layer 11 prevents the gold of the gold conductor 5 from being absorbed into the solder 9.

なお、導体バッド１０が金の場合、使用するハングはＩ
ｎＳｎ＋　！ｎＳｂなどのハンダを用いるのが好ましい
。In addition, when the conductor pad 10 is made of gold, the hang used is I.
nSn+! It is preferable to use solder such as nSb.

また、金導体５を複数層形成させる多層ノ＼イブリッド
ＩＣの場合には、前記実施例のように導体バ，ド１０の
材料に金を用いると、この導体パッド１０と上層の導体
とを同時に形戊できるので便利であるが、この発明では
導体パ，２ド１０の材料に金を用いる必要はなく、その
材料としてはハンダ付け可能な導体であればよく、具体
的にはニッケル、銅などが適用できる。そして、導体パ
ッド１０に金を用いない場合には、この導体パッド１０
がハンダ９と金導体５の間のバリア層の役目を兼ねる場
合もあるので、この場合はバリア層】１は必要ない。Furthermore, in the case of a multilayer/hybrid IC in which multiple layers of gold conductors 5 are formed, if gold is used as the material for the conductor pads 10 as in the above embodiment, the conductor pads 10 and the upper layer conductor can be simultaneously formed. Although it is convenient because it can be shaped, it is not necessary to use gold as the material for the conductor pads 2 and 10 in this invention, and the material may be any conductor that can be soldered, specifically nickel, copper, etc. is applicable. When gold is not used for the conductor pad 10, this conductor pad 10
In some cases, the barrier layer 1 may also serve as a barrier layer between the solder 9 and the gold conductor 5, so the barrier layer 1 is not necessary in this case.

［発明の効果］ 以上説明したようにこの発明では、金導体の上に直Ｉ＆
ハンダを形戊せずに、金導体の」二にバンダイ・１け可
能な導体パッドを形成し、この導体パッドの１−にハン
ダを形或するようにし，たので、金導体の金がハング中
に吸収されることがなくなり、金導体とチップ部品との
電気的接続が１フ好になる。[Effect of the invention] As explained above, in this invention, direct I&
Without shaping the solder, I formed a conductor pad on the second side of the gold conductor, and formed solder on the first side of this conductor pad, so that the gold of the gold conductor could hang. The electrical connection between the gold conductor and the chip component becomes good.

ハンダ付けはチップ部品の１＆板への接符強度が強く、
汎用的であるため、チップ部晶の７１への接ｊク怖度が
強く、汎用的で、全導体との電気的接統も安定している
ハイブリッド集積回路のマウント構氾が得られるという
優れた効果が得られる。When soldering, the strength of the joint of the chip parts to the 1 & board is strong,
Because it is general-purpose, there is a strong fear of contact with the chip crystal 71, and it is versatile and has the advantage of being able to provide a mounting structure for hybrid integrated circuits that has stable electrical connections with all conductors. You can get the same effect.

また、導体パッドの材料に金を用いれば、多居ハイブリ
・ノドＩＣの場合、導体パッドと−１二層の導体とを同
時に形成できる。この鴫合、この導体バ，ドと金導体の
間にバリア金属を形成させておけば、ハング付けＩ１｝
に金導体がハンダ中に吸収されることはないという優れ
た効果が得られる。Furthermore, if gold is used as the material for the conductor pads, the conductor pads and the -1 two-layer conductor can be formed at the same time in the case of a multi-layer hybrid node IC. If a barrier metal is formed between the conductors B, D and the gold conductor during this bonding, hanging I1}
An excellent effect is obtained in that the gold conductor is not absorbed into the solder.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例を示す側而断而図、第２図
（イ），（ロ），（ハ）は、従来のそれぞれ異なったハ
イブリッド集積回路のマウント構造を示す側面断面図で
ある。 ．チップ部品 ・ノλ板 ・金専体 ．ハンダ居 ・導体パッド ，バリア金属Figure 1 is a side view showing one embodiment of the present invention, and Figures 2 (a), (b), and (c) are side sectional views showing different conventional mounting structures for hybrid integrated circuits. It is. ．． Specializes in chip parts, lambda plates, and gold. Soldering/conductor pad, barrier metal

Claims (2)

【特許請求の範囲】[Claims] １．ハイブリッド集積回路の基板上に所定の間隔を保ち
対向して配置された金導体の上にハンダ付け可能な導体
パッドが形成され、この導体パッドとチップ部品の間に
ハンダ層が設けられ、このハンダ層により前記導体パッ
ドの上に前記チップ部品がマウントされていることを特
徴とするハイブリッド集積回路のマウント構造。1. Solderable conductor pads are formed on gold conductors placed oppositely at a predetermined distance on the substrate of the hybrid integrated circuit, a solder layer is provided between the conductor pads and the chip component, and the solder A mounting structure for a hybrid integrated circuit, wherein the chip component is mounted on the conductor pad by a layer. ２．導体パッドの材料が金であり、この導体パッドと金
導体の間にバリア金属が形成されている請求項１記載の
ハイブリッド集積回路のマウント構造。2. 2. The mounting structure for a hybrid integrated circuit according to claim 1, wherein the conductor pad is made of gold, and a barrier metal is formed between the conductor pad and the gold conductor.
JP1308955A 1989-11-30 1989-11-30 Mounting structure of hybrid integrated circuit Expired - Fee Related JP2830221B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1308955A JP2830221B2 (en) 1989-11-30 1989-11-30 Mounting structure of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1308955A JP2830221B2 (en) 1989-11-30 1989-11-30 Mounting structure of hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPH03171745A true JPH03171745A (en) 1991-07-25
JP2830221B2 JP2830221B2 (en) 1998-12-02

Family

ID=17987259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1308955A Expired - Fee Related JP2830221B2 (en) 1989-11-30 1989-11-30 Mounting structure of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JP2830221B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1564803A4 (en) * 2002-04-30 2008-09-03 Sumitomo Electric Industries EMBASE AND SEMICONDUCTOR DEVICE
US7993506B2 (en) 2007-01-16 2011-08-09 Ngk Spark Plug Co., Ltd. Gas sensor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1564803A4 (en) * 2002-04-30 2008-09-03 Sumitomo Electric Industries EMBASE AND SEMICONDUCTOR DEVICE
US7993506B2 (en) 2007-01-16 2011-08-09 Ngk Spark Plug Co., Ltd. Gas sensor

Also Published As

Publication number Publication date
JP2830221B2 (en) 1998-12-02

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