JPH03171492A - Dynamic type semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain the reduction of the interference noise between bit lines by crossing a pair of bit lines among the 2 pairs of bit lines at the center of a memory array, and simultaneously inserting a bit line of the other party between a pair of bit side pair. CONSTITUTION:Plural pairs of bit lines BL (BL0, the inverse of BL0, BL1, the inverse of BL1, BL2, the inverse of BL2, BL3, the inverse of BL 3...), constitute their bit line unit with 2 pairs, and are repeatedly disposed in the state where a bit line of the other side pair is arranged between the pair on one side. One side among the 2 pairs of bit lines BL, the inverse of BL constituting the bit line unit, is crossed at the center part of a longitudinal direction. In such a manner, the influence depending on the combined capacity between the adjacent bit lines can be decreased without increasing the chip area, and the interference noise is reduced.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a dynamic semiconductor memory device (DRAM), and particularly relates to a dynamic semiconductor memory device in which interference noise between bit lines is reduced. .

(Prior Art) DRAMs having a memory cell structure of one transistor/capacitor are becoming highly integrated due to improvements in the memory cell structure and advances in microfabrication technology. Data in a DRAM memory cell array is amplified by a sense amplifier and read out via a bit line pair. With the increasing density of DRAM, the bit line spacing has become extremely fine.
Interference noise between bit lines due to increased coupling capacitance between bit lines has become a serious problem in accurately reading data.

Conventionally, as a method to solve this serious problem, a method has been proposed in which the bit lines are crossed to reduce interference noise. For example, ■Japanese Unexamined Patent Publication No. 63-148489, ■ISSCC88D igest of Tec
hnical Papers pp239-239 building. However, although these methods achieve a certain level of noise reduction effect, they are still insufficient and also pose problems such as complicating the structure of the memory cell array.

(Problems to be Solved by the Invention) As described above, in conventional high-density DRAMs, large interference noise occurs due to the coupling capacitance between bit lines, and when attempting to solve this problem, the memory cell array becomes complicated. there were.

An object of the present invention is to provide a DRAM in which interference noise between bit lines is effectively reduced.

[Structure of the Invention + ffl] (Means for Solving the Problems) A dynamic semiconductor memory device of the present invention for achieving the above object has a bit line unit configured by two pairs of bit lines, and a bit line unit of the bit line unit. A plurality of bit lines having a folded bit line structure, in which one bit line pair is arranged between one bit line pair of the other bit line pair, and one bit line pair is arranged to intersect with each other at the center in the longitudinal direction. a plurality of word lines arranged to intersect with this bit line; two dummy word lines arranged parallel to this word line on each side of the intersection of the bit line pair; The bit lines are arranged every two consecutive bit lines in the word line direction at the intersections of the bit lines and the plurality of word lines, and are sequentially shifted by 1/2 pitch in the bit line direction. a plurality of dummy cells arranged at the intersection of the bit line and the dummy word line at a ratio of one dummy cell to at least one bit line; and a plurality of dummy cells arranged for each pair of bit lines. The present invention is characterized by comprising a bit line sense amplifier and a bit line sense amplifier.

(Function) In the dynamic type 1i conductor memory device of the present invention, one of two pairs of bit lines constituting a 9 bit line unit is arranged between the bit lines of the other pair, and one pair of bit lines is arranged between the other pair of bit lines. Since they are crossed (twisted), the influence of coupling capacitance between adjacent bit lines can be reduced without increasing the chip area, and interference noise can be reduced. Further, the interval between the paired bit lines is increased because another bit line is arranged between them, and therefore the layout of the bit line sense amplifiers provided for each bit line pair is easy.

In addition, in a memory cell array, memory cells are arranged diagonally in two columns every two columns with respect to the intersection position arrangement of bit lines and word lines, so the cell plate has loose lines/spaces and is easy to process. The cell plate can be arranged in a band shape with a constant width in the diagonal direction between the memory cell arrays.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

] 0 FIG. 1 shows the main part configuration of a DRAM according to a first embodiment of the present invention. This DRAM has a folded bit line structure. Multiple pairs of bit lines BL (BLO, BLO, BL
I. ,BLI. , BL2 , BL2 , BL3 , BL
3...) constitute a two-pair bit 1/line unit, and are repeatedly arranged with one wire of the other pair being placed between one pair.

One of the two pairs of bit lines BL, BL constituting a bit line unit intersects at the center in the longitudinal direction, as shown in the figure. In this embodiment, the bit line sense amplifier that amplifies memory cell data is a PMOS sense amplifier PSA (PSAO, PSA
I. , ...) and NMOS sense amplifiers NSA (NSAO, NSAI
,...). For such a plurality of bit 1/line pairs BL, BL, a plurality of word lines WL (WLO, WLI, WL21
] WL3,...) are arranged. Although only four word lines are shown in the figure, in reality many more word lines are arranged in parallel. And these bit lines BL
, BL and the word line WL, a memory cell M is arranged at the intersection of the word line WL. As shown in FIG. 2, this memory cell M is composed of one switching MOS transistor QM and a memory capacitor CM.

In this embodiment, the memory cell array has two memory cells M arranged on four word lines. These memory cells are successively arranged two by two every two bit lines along the word line direction, and sequentially shifted by 1/2 pitch in the bit line direction.

In other words, this memory cell array has bit lines BL, B
With respect to the lattice array formed by the intersections of L and word line WL, there are two rows every two rows in the diagonal direction.

This memory cell array also has two spare word lines SWL (S
WLO, SWLI, SWL2, ]2 SWL3) are prepared. In addition, there are two dummy word lines DWL on each side of the intersection of the bit lines BL■.
(DWLOI, DWLO3, DWL12, DW
L23) is provided. Two dummy words II
DWLOi and DWLO3 are connected to two other dummy word lines DWL12 and DWLO3 at both ends of the right cell array area.
W L 23 are arranged at both ends of the left cell array area. Along these dummy word lines DWL, dummy cells DC are arranged at a ratio of one for every two pairs of bit lines. Like the memory cell M, the dummy cell is composed of one MOS transistor QD and one memory capacitor CD, as shown in FIG.

The dummy cell may also have a structure including a write transistor QDw as shown in FIG.

In this embodiment, four dummy word lines DWL are at "H" level during precharging, and one word line WL
When a dummy cell is selected, the data of the selected memory cell is read out from the bit line.
So-called anti-phase driving is performed in which the dummy word line to be driven is set to the "L" 13 level. In this case, further
In this embodiment, two dummy word lines are set to “L” at the same time.
Driving is performed to achieve the level.

For example, in FIG. 1, when word line WLO is selected and becomes "H" level, dummy word line DWLO
I. , DWLO3 are selected and become "L" level. Similarly, when word line WLI is selected, dummy word line D
W L 01 and D W L 12 are selected and “L
” level. When the word line WL2 is selected and becomes the “H” level, the dummy word line D W L 12,
DWL 23 is selected and becomes "L" level. When word line WL3 is selected, dummy word line DW
L23 and DWLO3 are selected and become "L" level.

FIG. 5 schematically shows the layout of the main parts of the memory cell array. Element formation regions surrounded by an element isolation insulating film on a silicon substrate] are arranged and formed as shown in the figure.
A cell plate 2, which is a common electrode for a capacitor of a memory cell, is formed of a lower polycrystalline silicon film having a strip pattern running diagonally. Then, the switching MOS of the memory cell which becomes the word line W is formed by the upper polycrystalline silicon film.
A gate electrode 3 of the transistor is provided, and a MOS transistor is formed in the nodal region sandwiched between the cell plates 2.

The shaded region in the figure is the gate region of each MOS transistor. Although the bit lines BL and BL are simply shown as straight lines in the figure, they are formed by Aβ wiring or the like so as to contact the common drain regions of adjacent MOS transistors.

As shown in Fig. 1, the bit line pairs are crossed in the PMOS sense amplifier PSA section, but this is achieved in a special way by using the gate 1 electrode of the MOS transistor that constitutes the sense amplifier PSA. This can be realized without using cross wiring.

The principle configuration is shown in FIG. Gate electrode 51.5 in the figure
2 is that of a sense amplifier MOS transistor connected to the bit line pair BLI, BLI; for example, the gate electrodes 51 and 52 are made of first layer polycrystalline silicon film wiring;
Bit lines BL and BL are formed using a second layer polycrystalline silicon film. That is, the bit line BLO is disposed across the gate electrode 51 using the gate electrode 51 to which the bit line BLI is connected as part of the wiring.

Similarly, bit lines BLO and BLI are disposed across gate electrode 52, using gate electrode 52 to which bit line BLI is connected as part of the wiring.

FIG. 7 more specifically shows the configuration of the bit line intersection and the PMOS sense amplifier PSA disposed there as an equivalent circuit. FIG. 8 shows its layout. Two pairs of bit lines BLO forming a bit line unit shown in FIG.
The PMOS sense amplifier PSAO provided in BLO, BLI, BLI is actually a sense amplifier PSAO connected to the bit line pair BLO, BLO, as shown in FIG.
I, and a sense amplifier PSAO2 connected to the bit line pair BLI, BLI.

The sense amplifier PSA old is a dynamic 16-type sense amplifier composed of p-channel MOS+- transistors Trl and Tr2, and the sense amplifier PSAO2 is a dynamic-type sense amplifier composed of p-channel MOS+-transistors Tr3 and Tr4.

Four MOS transistors constituting these sense amplifiers are arranged in four stages with their elongated gate electrodes aligned in the bit line direction. Sense amplifiers PSAII and PSA that constitute the PMOS sense amplifier PSAI in Fig. 1
The same applies to I2.

In the word line direction, MOSI transistors constituting the sense amplifier are arranged at a ratio of one for every four bit lines. Sense amplifier PSAIIP S A 12
,... MOS transistors Tr3, Tr
In the regions Tr4, Tr5, Tr6, . . . , bit line crossings are performed on their gate electrodes according to the construction method shown in FIG.

Although the specific configuration of the NMOS sense amplifier NSA is not shown, the configuration principle is the same as that of the PMOS sense amplifier, and it is a dynamic 2 (resense amplifier) using an n-channel MOS transistor.

According to this example, interference noise between the bit lines is reduced by having one of the two pairs of bit lines intersecting each other at the center. For example, if we look at the bit line pairs BLI and BLI that intersect, these are the bit line pairs LO, BLO and BL.
Adjacent to 2. The bit line pairs BLI, BLI are not adjacent to each other. Therefore, bit line pair BLI, BLI
Interference noise between the two is greatly reduced. Bit 49 B
The interference effect on the bit lines BLI and BLI of L2 is:
Since BLI and BLI intersect at a point of approximately ]/2 of the wiring length, they are approximately equal. That is, the interference caused by the bit line BL2 does not appear as a potential difference between BLI and BLI, and does not lead to a decrease in the sense margin of the sense amplifier. Similarly, the interference effect of bit lines BLO, BLO on bit lines BLI, BLI does not appear as a potential difference between BLI, BLI.

Next, attention will be paid to the bit line pair BL2, BL2.

Bit line pair BL2, the bit line adjacent to BL2 is BLI
, BLI and BL3, BL3. Now, word line WLO is selected in FIG. Rabbit: breath, 1, 7' upper kuni memory: ``H'' level from 2, B:; l'
Consider the worst pattern in which "L" level is read from the memory cell on 5tBL3. At this time, bit line BL2 receives interference noise from bit line BLI, but
Since BLI and BL2 are adjacent to each other for half the wiring length, their size is the normal size ]/2. Bit line BL3
The interference noise received from the left half of BL3 is canceled out because it is equally capacitively coupled to BL2 and BL2. The right half of the bit line BL3 gives interference noise to the bit line BL2 due to the coupling capacitance of half the wiring length.

Further, since the bit lines BL2 and BL2 are not adjacent to each other, there is no interference noise between them. Since there is no memory cell at the intersection of the word line WLO with the bit lines BLI and BL3, the bit lines BLI and BL3 are at a precharge potential, for example (1/2) Vcc, and do not change. As described above, even in the sense amplifier of the bit line pair BL2, BL2, the interference noise is reduced to ]/2 of the conventional value even in the worst case.

Also, in this embodiment, when selecting one word line, it is necessary to select two dummy word lines, but two dummy word lines are prepared and one of them is selected. Compared to the selected method, the load on each dummy word line becomes lighter. Furthermore, when one of the four dummy word lines is selected and set to "L" level, the remaining three dummy word lines are set to "H" level, and the bit line capacitance increases by the dummy cell capacitance. However, in this embodiment, only one dummy cell is connected to one bit line, so there is no increase in bit line capacitance. Therefore, high sense sensitivity can be obtained.

Further, according to the memory cell arrangement method according to this embodiment, as shown in FIG. 5, the cell plate 2 is arranged in a band shape with a constant width without being constricted, and the lines/spaces are loose, making it easy to process. Also stable in memory cell array! A quasi-potential can be given.

FIG. 9 shows the main structure of a DRAM according to a second embodiment of the present invention. Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 120, and detailed description thereof will be omitted. This embodiment differs from the embodiment shown in FIG. 1 in that the dummy word line DWL is driven in normal phase. That is, the four dummy word lines DWL are kept at the "L" level during the precharge time, and when one word line is selected and becomes the 'H' level, two of the four dummy word lines DWL are kept at the "L" level. A book is selected and becomes "H" level.For example, when word line WLO is selected, dummy word lines DWLOI and DWLO3 are selected and become "H" level.Similarly, word line WL
When I is selected, the dummy word line D W L 01,
DWLI2 is selected. When word line WL2 is selected, dummy word lines DWLI2 and DWL23 are selected. When word line WL3 is selected, dummy word line D
W L 23 and D W L 03 are selected.

This embodiment also provides the same effects as the previous embodiment.

FIG. 10 shows the main part configuration of a DRAM of the third embodiment of the present invention, which is shaped like the figure 9. In the failed example of the ninth country, a 2] PMOS sense amplifier PSA was placed in the center of the memory cell array, but in this example, it is divided for each bit line and NMOS sense amplifiers and NMOS sense amplifiers are placed at both ends of the memory cell array. It is placed. In other words, bit line sense amplifier SA (SAO, SAI
, SA2, . . . ) each include an NMOS sense amplifier and a PMOS sense amplifier. Like this PMOS
If sense amplifiers are also placed at both ends of the memory cell array,
As previously explained in FIGS. 6 to 8, the gate 1 electrode of the sense amplifier cannot be used as is for bit line cross wiring, but cross wiring can be performed in the same manner as shown in FIG. .

Although not shown in the figure, the arrangement of the sense amplifiers in the embodiment shown in FIG. 1 can be changed in the same way as in FIG. 10.

This embodiment also provides the same effects as the previous embodiment.

FIG. 11 shows a DRAM according to a fourth embodiment of the present invention. The difference from the embodiment shown in FIG. 1 is that there are two
22 dummy cells DC are provided. That is, bit line pair BLO, BLO
One BLO has dummy cells DC selected by dummy word lines DWLO and DWL3 at both ends thereof, respectively.
On the other hand, in the center of BLO, dummy cells DC selected by dummy word lines DWLI and DWL2 are arranged. In other words, the dummy word lines DWL (DWLO, DWLI, DWL2
, DWL3), two dummy cells DC are arranged for each two pairs of bit lines.

In this embodiment, the dummy word line DWL is driven in reverse phase to be at the "H" level during precharging, or one of the four lines is selected and set to the "L" level. For example, when word line WLO is selected and goes to "H" level, I. i
At J time, dummy word line DWLO is selected and goes to "L" level. Similarly, when word line WLI is selected, dummy word line DWLI is selected, and word line WL
When word line 2 is selected, dummy word line DWL2 is selected, and when word line WL3 is selected, dummy word line DWL3 is selected.

Therefore, in this embodiment, one dummy cell is connected to the bit line connected to the selected memory cell, and two dummy cells are connected to the paired bit line. Also, twice the number of dummy cells is required compared to the embodiment shown in FIG. However, since it is only necessary to select one dummy word line, the selection means becomes easy.

FIG. 12 shows a DRAM of the fifth cusp embodiment of the present invention. This is a modification of the embodiment shown in FIG. 11, and the dummy word line DW
L is driven in normal phase.

The dummy word lines DWL are at "L" level during precharging, and one selectively becomes "H" level.

For example, when word line WLO is selected, dummy word line DWLO is selected; when word line WLI is selected, dummy word line DWLI is selected; when word line WL2 is selected, dummy word line DWL2 is selected; When line WL3 is selected, dummy word line DWL3 is selected.

24 FIG. 13 shows a DRAM according to a sixth embodiment of the present invention.

This embodiment is based on the PMP of the DRAM of the embodiment shown in FIG.
S sense amplifiers PSA are arranged together with NMOS sense amplifiers at both ends of the memory cell array as in FIG. 10.

Similar changes in the sense amplifier arrangement can also be made to the embodiment of FIG.

By the way, in large-scale DRAMs, a memory cell array is divided into a plurality of (for example, 4 or 8) subcell arrays in the bit line direction, and a shared sense amplifier method is adopted in which adjacent subcell arrays share a bit line sense amplifier. Ru. The memory cell array in the embodiments described so far is a large-scale DR using such a shared sense amplifier method.
In AM, this corresponds to one subcell array. The bit line sense amplifiers arranged at both ends of the memory cell array are connected to adjacent subcell arrays.

Further, in such a shared sense amplifier type DRAM, not only the bit line sense amplifier but also dummy cells and dummy word lines can be shared by adjacent subcell 25 arrays to improve the degree of integration.

Such embodiments are described below.

FIG. 14 shows the main structure of a DRAM of such an embodiment. This is based on the memory cell array configuration shown in FIG. NMO arranged at both ends of subcell array 11
S sense amplifier NSA is connected to bit line BL in subcell array 11 via selection gates SGQ and SGI. The NMOS sense amplifier NSA on the right side of the subcell array 11 is also connected to the bit line BL in the adjacent subcell array 12 via the selection gate SG2.
It is shared by two subcell arrays] 1 and 12. Although omitted in the figure, the NM on the left side of the subcell array 11
Similarly, the OS sense amplifier NSA is shared with the adjacent subcell array. In this example, dummy cell D
C is also arranged near the NMOS sense amplifier NSA and connected to the bit line in the subcell array via the selection gate SG. That is, the dummy cell DC and the dummy word line DWL that drives it are converted to J':(-i) by the adjacent sub cell array, similar to the NMOS sense amplifier.

According to this embodiment, the number of dummy cells and dummy word lines is halved, and the DRAM can be highly integrated.

Figure 15 shows another example of the DR of the military sense amplifier system.
This is the main structure of AM. This embodiment is based on the memory cell array configuration of the embodiment shown in FIG. 9 in which the dummy word lines are driven in the normal phase, and the dummy cells and dummy word lines are shared as in FIG. 14.

FIG. 16 shows the main part configuration of a DRAM of still another embodiment of the shared sense amplifier type. This embodiment is based on the structure of the embodiment shown in FIG. 10, in which PMOS sense amplifiers and NMOS sense amplifiers are arranged at both ends of the memory cell array, and dummy cells and dummy word lines are shared.

The PMOS sense amplifier PSA is located at both ends of each knob cell array, or unlike the NMOS sense amplifier, it is not shared.

27 Even with the embodiments shown in FIGS. 15 and 16,
Does it have the same effect as the example shown? It will be stolen.

[Effects of the Invention] According to the present invention, one pair of bit lines out of two pairs of bit lines is crossed at the center of the memory array, and the other bit line is crossed between one pair of bit sides. By inserting one bit line in a pair, the influence of capacitive coupling between adjacent bit lines can be reduced, and interference noise can be reduced. In addition, by appropriately arranging dummy word lines and dummy cells, DRA
M can be operated properly. Furthermore, according to the memory cell arrangement of the present invention, the layout of cell plate electrodes is facilitated. Furthermore, in a shared sense amplifier type DRAM, high integration can be achieved by sharing dummy cells and dummy word lines.

[Brief explanation of the drawing]

28. FIG. 1 is a circuit diagram of a DRAM according to the first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram showing its memory cell configuration, and FIG. 3 is an equivalent circuit diagram showing its dummy cell configuration. Figure 4 is an equivalent circuit diagram showing another dummy cell configuration, Figure 5 is a schematic layout diagram of the memory cell array, Figure 6 is a diagram showing the bit line crossing method, and Figure 7 is the same <PMOS sense amplifier section. FIG. 8 is a layout diagram thereof, FIG. 9 is a circuit diagram of a DRAM according to a second embodiment of the present invention, and FIG. 10 is a third embodiment of the present invention. 11 is a circuit diagram of a DRAM according to a fourth embodiment of the present invention, FIG. 12 is a circuit diagram of a DRAM according to a fifth embodiment of the present invention, and FIG. 13 is a circuit diagram of a DRAM according to a fifth embodiment of the present invention. 29 FIG. 14 is a circuit diagram of a DRAM according to a shared sense amplifier system based on the configuration of the first embodiment, and FIG. 15 is a circuit diagram of a DRAM according to the second embodiment.
FIG. 16 is a circuit diagram of a DRAM using a shared sense amplifier system based on the configuration of the third embodiment. FIG. 16 is a circuit diagram of a DRAM using a shared sense amplifier system based on the configuration of the third embodiment. . BL BL...Bit line, WL...Word line, D
WL, DWL...dummy word line, SWL...spare word line, M...memory cell, DC...dummy cell, PSA...PMOS sense amplifier, NSA...
NMO'S sense amplifier, 1... element formation region,
2... Cell plate, 3... Gate 1 electrode (word line), 11. , 12... sub cell array, SG...
Choice game!・.

Claims (14)

[Claims] (1) Two pairs of bit lines constitute a bit line unit, one bit line pair is arranged between one bit line pair of this bit line unit, and one bit line pair is arranged in the longitudinal direction. A plurality of bit lines of a folded bit line structure are arranged to intersect with each other in the center, a plurality of word lines are arranged to intersect with the bit lines, and the bit lines are arranged in parallel with the word lines. Two dummy word lines are arranged on both sides of the pair of intersections, and two dummy word lines are arranged at the intersections of the plurality of bit lines and the plurality of word lines, and two dummy word lines are arranged for every two consecutive bit lines in the word line direction. a plurality of memory cells arranged every other bit line and sequentially shifted by 1/2 pitch in the bit line direction; 1. A dynamic semiconductor memory device comprising: a plurality of dummy cells arranged at a ratio of 1 to 1; and a bit line sense amplifier provided for each bit line pair. (2) The bit line sense amplifier is composed of a PMOS sense amplifier and an NMOS sense amplifier.
A sense amplifier is placed in the longitudinal center of the bit line,
2. The dynamic semiconductor memory device according to claim 1, wherein the NMOS sense amplifier is arranged at an end of the bit line. (3) The dynamic semiconductor memory device according to claim 2, wherein the bit line pair crosses each other using a gate electrode of a MOS transistor constituting the PMOS sense amplifier. (4) The dynamic semiconductor memory device according to claim 1, wherein the bit line sense amplifier is arranged at an end of the bit line. (5) The dynamic semiconductor memory device according to claim 1, wherein two dummy cells are arranged on each bit line. (6) The plurality of dummy word lines are “H” during precharging.
A dummy cell that drives a dummy cell connected to a bit line that is held at "H" level and from which data of the selected memory cell is read when one of the plurality of word lines is selected and becomes "H" level when activated. 2. The dynamic semiconductor memory device according to claim 1, wherein the word line is at an "L" level. (7) The plurality of dummy word lines are “L” during precharging.
When one of the plurality of word lines is selected and becomes the "H" level while active, the word line is connected to the bit line paired with the bit line from which the data of the selected memory cell is read. 2. The dynamic semiconductor memory device according to claim 1, wherein a dummy word line for driving a dummy cell is at an "H" level. (8) A dynamic semiconductor memory device in which a memory cell array is divided into a plurality of subcell arrays and adjacent subcell arrays share a bit line sense amplifier, in which a pair of bit lines constitutes a bit line unit, and the bit line A plurality of folded bit line structures in which one bit line pair of a unit is arranged between one bit line pair of the other bit line pair, and one bit line pair is arranged to intersect with each other at the center in the longitudinal direction. a bit line, a plurality of word lines arranged to intersect with the bit line, and dummy word lines arranged parallel to the word line on each side of the intersection of the bit line pair; At the intersection positions of the plurality of bit lines and the plurality of word lines, two bit lines are arranged every two consecutive bit lines in the word line direction, and a 1/2 pitch is sequentially arranged in the bit line direction. a plurality of memory cells arranged at different intervals; a plurality of dummy cells arranged at the intersection of the bit line and the dummy word line at a rate of one per at least one bit line; and for each pair of bit lines. A dynamic semiconductor memory device comprising: a bit line sense amplifier provided and shared by adjacent subcell arrays. (9) The dynamic semiconductor memory device according to claim 8, wherein the bit line sense amplifier is composed of a PMOS sense amplifier and an NMOS sense amplifier, and is arranged at an end of each subcell array. (10) The bit line sense amplifier is composed of a PMOS sense amplifier and an NMOS sense amplifier, and is composed of a PMOS sense amplifier and an NMOS sense amplifier.
S sense amplifier is arranged for each subcell array, and NM
9. The dynamic semiconductor memory device according to claim 8, wherein the OS sense amplifier is arranged at an end of the subcell array, connected to the bit line via a selection gate, and shared by adjacent subcell arrays. (11) The dynamic semiconductor memory device according to claim 8, wherein two dummy cells are arranged for each bit line at an end of the subcell array. (12) The plurality of dummy word lines are “
When one of the plurality of word lines is selected and becomes the "H" level when active, it drives a dummy cell connected to the bit line from which the data of the selected memory cell is read. 9. The dynamic semiconductor memory device according to claim 8, wherein the dummy word line is at "L" level. (13) The plurality of dummy word lines are “
When one of the plurality of word lines is selected during activation and becomes the "H" level, the bit line paired with the bit line from which the data of the selected memory cell is read. 9. The dynamic semiconductor memory device according to claim 8, wherein a dummy word line that drives connected dummy cells is at an "H" level. (14) The dynamic semiconductor memory device according to claim 2, wherein the dummy cell is arranged at an end of the subcell array, connected to a bit line via a selection gate, and shared by adjacent subcell arrays.