JPH03169287A - Controller of rotary element - Google Patents

Abstract

PURPOSE:To eliminate a steady-state phase deviation by a method wherein a phase control system is constituted by a loop composed of a position detecting means, a phase comparator, a reference signal generating means, a digital filter and so forth. CONSTITUTION:The position signal of a motor 1 is picked up by a position detecting means 7 and the position signal (PG signal) is inputted to a phase comparator 8. A reference phase signal outputted by a reference phase signal generating means 9 is inputted to the phase comparator 8. The output of the phase comparator 8 is inputted to a digital filter 10 for low-frequency range compensation. The digital filter 10 transmits the filtered output to an output correcting means 11. The output correcting means 11 corrects the output data of the digital filter 10 in accordance with the overflow detecting signal of the digital filter 10. A phase control system is constituted by the above mentioned loop and eliminates the steady-state phase deviation of the phase control system. Further, a steady-state speed deviation can also be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a rotating body control device for controlling the speed and phase of a rotating body used in a magnetic recording/reproducing device or the like.

Conventional technology A control device for a rotating body has two functions: speed control to control the period of the output signal (hereinafter referred to as FG signal) of a frequency generator attached to the rotating body to a desired period; Phase control is performed to control the phase difference between a signal representing a position (hereinafter referred to as a PG signal) and a reference phase signal to a desired value.

For example, in a cylinder motor of a magnetic recording/reproducing device, a frequency generator attached to the motor generates six pulses of the FC signal per rotation, and a PC signal generates one pulse per rotation. Since the cylinder motor rotates at 30Hz, F(
? , the signal frequency is 180Hz, and the reference period is 1
/180 sec. Therefore, speed control is performed so that the period of the FC signal becomes 1/180 sec. Also, P.C. The frequency of the signal is 30Hz,
Phase control is performed so that there is a predetermined phase difference from the reference phase signal.

The speed control error output and the phase control error output are combined at their respective synthesis ratios and output to the cylinder motor drive circuit, and the cylinder motor is driven by the output of the drive circuit to perform rotation control.

However, the speed control output. A steady speed deviation and a steady phase deviation occur due to the offset 1 and the load generated between the combined output of the phase control output and the drive circuit. Steady-state speed deviation hardly occurs because the phase control operates as an integral term in the speed control system, but since the phase control system operates to correct the steady-state speed deviation of the speed control, the error output of the phase control includes the correction amount. appears, and the center value of the phase error output shifts. In particular, since the gain of the phase control system is larger than the gain of the speed control system, even if the steady-state speed deviation is small, it appears as a large steady-state phase deviation, which causes a large steady-state phase deviation.

Is steady phase deviation a phase system? Since there is no integral term for the ffl system, only one part of the phase control gain remains.

Therefore, the phase difference between the PC signal and the reference phase signal cannot be adjusted to the set value. Therefore, a low frequency compensation filter is inserted into the phase error output so as to compensate for the error output in the low frequency range. This filter eliminates steady phase deviation.

If this low-pass compensation filter is constructed with a digital filter, the result will be as shown in FIG. The reason why this filter is constructed digitally is that the speed control and phase control are processed digitally, and if the filter operation can be processed digitally, all controls including the filter operation can be converted into digital ICs. Because you can. Furthermore, by digitizing the filter, it is possible to eliminate changes in characteristics caused by variations in components, temperature changes, and the like.

Here, the operation of the digital filter shown in FIG. 9 will be explained. First, input data is input from the terminal 1101,
The multiplier 102 multiplies it by a constant. In block 1103 that performs cumulative addition, multiplier 1 1. The output data of 0 and 2 are cumulatively added and the cumulative result is stored in the memory.

Here, ZI is a symbol representing one sample delay. Multiplier 1104 multiplies the cumulative result of block 1103 by a constant, adder 1105 adds the output data of multiplier 1104 and the output data of multiplier +102, and outputs the result from output terminal 1106 as output data of the digital filter.

In block 1103, which performs cumulative addition, the cumulative data stored in the memory is data for compensating for steady speed deviation and steady phase deviation, so it increases or decreases depending on the values of steady speed deviation and steady phase deviation. It happens. Therefore, when a large load is applied or when the speed deviation is large, the cumulative data stored in the memory becomes a large value.

Problem to be Solved by the Invention However, in the above structure, when the speed deviation and phase deviation are large, the accumulated data of the low-pass compensation filter that compensates for them becomes a large value, and the memory storing the accumulated data becomes large. The maximum value that can be stored may be exceeded. Therefore, the value stored in the memory is fixed at the upper or lower limit value, and as a result, compensation by the cumulative term is no longer possible, and a deviation remains. The fact that a steady phase deviation remains means that the performance of phase control has deteriorated.
In extreme cases, there is a problem that phase lock is not achieved and phase control does not operate normally.

Means for Solving the Problems In order to solve the above-mentioned problems, a control device for a rotating body according to the present invention includes frequency discriminating means for frequency discriminating a signal that changes the speed information of the rotating body, and a phase comparison means for performing a phase comparison between a signal having information and a reference phase signal outputted from the reference phase signal generation means; a digital filter for compensating the output of the phase comparison means; and a digital filter for detecting an overflow of the digital filter. overflow detection means; output correction means for correcting the output of the digital filter using the output signal of the overflow detection means; synthesis means for synthesizing the output of the output correction means and the output of the frequency discrimination means; A driving means for driving the rotating body by an output is provided.

The present invention uses the above-described structure to detect the overflow of the cumulative term of the digital filter that compensates for the steady speed deviation 2 steady phase deviation caused by offset, load, etc.
By correcting the output signal of the digital filter using the detection output, the cumulative term of the digital filter will not overflow, so the steady speed deviation of the speed system and the steady phase deviation of the phase control system can be corrected using the digital filter (low-pass compensation filter). can be removed.

Embodiment Hereinafter, a control device for a rotating body according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a rotating body control device showing an embodiment of the present invention. 1 is a rotating body (motor), and 2 is a frequency generator that extracts rotation information of the motor 1. F
C signal is output. 3 is a frequency discrimination means for frequency discrimination of the FC signal.

Reference numeral 4 denotes a synthesizing means for combining the output of the frequency discriminator 3 with the output of the output correcting means 11 (described later).

5 is a digital-to-analog converter to which the digital data output of the synthesizing means 4 is manually input; 6 is a power amplifier for amplifying the analog signal; the motor 1 is driven by the output thereof. The speed control system is configured by the above loop.

Next, 7 is a position detecting means for extracting a position signal of the motor 1, and the position signal (PC signal) is inputted to a phase comparator 8. Further, the reference phase signal outputted from the reference phase signal generating means 9 is inputted to the phase comparator 8 . The output of the phase comparator 8 is input to a digital filter IO, where low-frequency compensation is performed. The digital filter 10 sends the filtered output to the output correction stage 11 and the overflow detection signal to the output correction means 11. The output correction means 11 corrects the output data of the digital filter IO based on the overflow detection signal of the digital filter 10. The above loop constitutes a phase # control system.

FIG. 2 is a time chart for explaining the operation of the frequency discrimination stage 3, where a is the FG signal, b is a trapezoidal wave for frequency discrimination, and at the time when the FG signal a is input. A speed error output C is obtained by sampling the value of the trapezoidal wave b. After the trapezoidal wave b is sampled by the FC signal, a new reference period is set to create the next trapezoidal wave of the FC signal. Speed error output C
For example, when the period of the FG signal a is shorter than the reference period, a positive error output is output, and when it is longer, a negative error output is output.

FIG. 3 is a flowchart when the above-described operation of the frequency discrimination means 3 is realized by software, and the process 301
In step 302, it is determined whether the FC signal was input manually or not, and if the FC signal was input, the process moves to process 302 and the F
If the G signal is not input, the process moves to process 307.

In process 302, the period of the FG signal is calculated. Previous F
If the count value of the base counter when the C signal is input is NSB, and the count value of the base counter when the current FC signal is input is NSA, the period PER S of the FC signal can be obtained from equation (1). .

PER S=NSI3-NSA -=・(
+) Here, the Haese counter is treated as operating as a cyclic counter that counts down the reference clock signal.

Next, in process 303, the speed error ERR S is determined by equation (2) using the period PER S of the FC signal determined in process 302 and the reference period REF S.

E R R S = R E F S - P E
R S −・− =− (2) And processing 30
In step 4, limit processing is performed so that the speed error ERR S falls within a specified range, and in step 305, the speed error ERR S is output to the Isen stage 4. after that,
In process 306 in preparation for processing the next FC signal,
The count value NSA of the Haese counter when the current FG signal is input is stored in NSB again, and the operation of the frequency discrimination means 3 is ended.

If the FC signal has not been manually input in process 301, it is determined in process 307 whether or not the allowable time for inputting the next FG signal has exceeded since the previous FC signal was input manually. If so, process 30
At step 8, the speed error output for accelerating the motor 1 to the maximum is outputted to the synthesizing means 4, and the process ends at step 11. If the speed error is not exceeded, the process ends without doing anything.

As mentioned above, the speed error ERR S is the period of the measured FC signal; tl + P E R S is the reference period REF
If it is shorter than S, a positive value is output, and if it is longer, a negative value is output.

FIG. 4 is a time chart for explaining the phase comparison means 8, where a is a reference phase signal, b is a trapezoidal wave for performing phase comparison generated from the reference phase signal a, and the PC A phase error output d is obtained by sampling the trapezoidal wave b at the time when the signal C is input. The phase error output C outputs a positive error output when the phase difference between the reference phase signal a and the PC signal C is shorter than a predetermined phase difference, and outputs a negative error output when it is longer.

FIG. 5 is a flowchart when the operation of the 1,000-stage phase comparison 8 is realized by software. In process 501, the reference phase signal (REF P
) is manually input, and if the reference phase signal has been input, the process moves to process 502, and if the reference phase signal has not been input, the process moves to process 503. In process 502, the count 1 of the Haeskaunk at the time when the reference phase signal was manually input is calculated.
- The value CNI is stored in the memory N REF. In process 503, it is determined whether a PG signal has been input, and if a PG signal has been input, the process moves to process 504,
The count value CN2 of the Hayes counter at the time when the PG signal was input is stored in the memory NPA. In process 505, the phase error ERRI) is obtained using equation (3).

ERR P shit N REF P (N REF - NPA) ...... (3) Here, N REF P does not represent the reference phase difference and is the counter 1.
・It is a value.

Next, in process 506, a reduction process is performed so that the phase error ERR P falls within a specified range, and in process 507
The digital filter 10 has a phase error ERR at
Output P. This completes the operation of the phase comparison means 8.

If the PG signal is not input in process 503, the process ends without doing anything.

Next, FIG. 6 shows a bronch diagram of the digital filter 10. Input data is input from an input terminal 601 and multiplied by a constant in block 602 .

Block 603 performs cumulative addition of input data input from input terminal 601, and stores the cumulative result in memory. In block 604, the cumulative result of block 603 is multiplied by a constant, and in block 603, the output data of block 604 and the output data of block 602 are added,
Output terminal 606 as output data of the digital filter
The output is shifted by more.

Further, when the memory storing the accumulated results overflows in block 603, an overflow detection signal is output from overflow output terminal 607.

The overflow detection signal includes data indicating the polarity of overflow [-7-].

FIG. 7 is a flowchart when the operation of the digital filter 10 is realized by software. In process 701, data DI input to the input terminal 601 shown in FIG. 6 is stored in the memory M1. In process 702, the data in the memory MI is multiplied by a constant 01, and the multiplication result is stored in the memory M2. In process 703, the data in the memory MI in which the accumulated results up to now are stored is added to the manual data Di, and the addition result is stored again in the memory Ml. In process 704, it is determined whether the addition result stored in the memory M1 exceeds the maximum or minimum value that the memory M1 can store, that is, whether there is an overflow. If the memory M1 has not overflowed, the process moves to step 705, where the cumulative result of the data in the memory M1 is multiplied by a constant C2, and the multiplication result is stored in the memory M3. Then, in process 706, the data in the memory M2 and the memory M3 are added, and the addition result is output as the output data of the digital filter 10.

In process 104, if the memory MT has overflowed, the process moves to process 707, where it is determined whether the overflow has exceeded the maximum or minimum value. In other words, the polarity of the overflow is determined. When the overflow of the memory Ml is the maximum value, the process moves to process 708, sets the value of the memory Ml to the maximum value of 6, further outputs a positive overflow signal from the output J terminal 607 (not shown in FIG. 6), and processes. 705.

When the overflow of the memory Ml is the minimum value, the process moves to step 709, where the value of the memory Ml is set to the minimum value, and a negative overflow signal is output from the output terminal 607. Thereafter, the process moves to process 705. As described above, digital filter processing is performed by software.

Next, the output correction means l1 for correcting the output of the digital filter 10 based on the output of the overflow detection signal will be explained. FIG. 8 is a flowchart when the output correction means 11 is realized by software. In process 801, the overflow signal output from the digital filter 10 is taken in, it is determined whether the memory M1 of the digital filter 10 has overflowed, and the overflow signal is outputted from the digital filter 10. If there is no flow from 1 to 1, the process ends. If the digital filter 10 has overflowed, the process moves to step 802. In process 802, it is determined whether the polarity of the overflow signal is positive, and if it is positive, the process moves to process 803. In process 803, the following process is performed.

Although the polarity of the overflow signal is positive, even though the output of the digital filter 10 should output a larger positive value, it is limited by the cumulative memory Ml and cannot be larger than the limit value. It shows that Therefore, the output of the digital filter 10 is corrected using the correction value, and the cumulative memory M1
prevent overflow.

That is, as shown in equation (4), the digital filter 1
It is sufficient to correct the output data F I L of 0.

FIL C=FIL+ΔC ・・・・・・
(4) Here, FILC is the output of the output correction means 11 that corrected the output data of the digital filter 10, and Δ
C is a correction value. If the steady speed deviation or steady phase deviation is large and the overflow of the digital filter 10 cannot be improved by performing the correction using equation (4) once, the correction using equation (4) is repeatedly performed and the memory storing the cumulative value is If the adjustment is carried out until the value of MI becomes approximately "0", that is, until it reaches the center of operation, the pull-in range by the phase control system will be greatly improved.

When the polarity of the overflow signal in process 802 is negative, the same process as that performed in process 803 is performed in process 804. That is, the correction value ΔC used in equation (4) is converted to the output data FI of the idicle filter 10.
If subtracted from L, it is expressed as Equation (5).

FIL C=FTL-ΔC ・・・・・・
(5) As shown in (2) below, the low-pass compensation filter (digital filter 10) of the phase control system caused by steady speed deviation
By correcting the output signal of the digital filter 10, the digital filter IO can be prevented from overflowing, and the operating point of the digital filter 10 can be brought close to the center. A wide range of low frequency compensation operations can be performed.

In this embodiment, a case has been described in which each process is implemented using software, but there is no harm in implementing similar operations using hardware.

Effects of the Invention As described in ``2'', the present invention includes a frequency discrimination means for frequency discriminating a signal having speed information of a rotating body, and a signal having position information of the rotating body and a reference phase signal outputted from a reference phase signal generating means. a phase comparison means for performing a phase comparison with a reference phase signal; a digital filter for compensating the output of the phase comparison means; an overflow detection means for detecting an overflow of the digital filter; It comprises an output correction means for correcting the output of the filter, a synthesis means for synthesizing the output of the output correction means and the output of the frequency discrimination means, and a drive means for driving the rotating body by the output of the synthesis means. Therefore, the overflow of the low-pass compensation filter (digital filter) of the phase control system caused by the steady speed deviation and steady phase deviation is corrected by using the correction value for the output of the digital filter. By preventing overflow, the operating point of the digital filter can be set near the center, allowing low-frequency compensation operation with a wide operating range, which is very effective. be.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a control device for a rotating body according to an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of the frequency discriminator, and Fig. 3 is a diagram showing the frequency discriminator configured by software. FIG. 4 is a time chart for explaining the operation of the phase comparison means, FIG. 5 is a flowchart when the phase comparison means is configured by software, FIG. 6 is a block diagram of the digital filter, and FIG. 7 8 is a flowchart when the digital filter is configured by software, and FIG. 8 is a flowchart for explaining the operation of the output 20 correction means.
The figure is a block diagram of a conventional digital filter. 1...Moke, 2...Speed generator, 3
...Frequency discrimination means, 4...Synthesizing means, 5...Digital-to-analog converter, 6...
...Power amplifier, 7. Group position detection means, 8.
. . . Phase comparison means, 9 . . . Reference phase signal generation means, 10 . . . Digital filter, 11.
...Output correction means.

Claims (4)

[Claims] (1) A frequency discrimination means for frequency discriminating a signal having speed information of a rotating body, and a phase comparison for performing a phase comparison between a signal having position information of the rotary body and a reference phase signal output from a reference phase signal generation means. means, a digital filter for low-frequency compensation of the output of the phase comparison means, overflow detection means for detecting overflow of the digital filter, and output correction means for correcting the output of the digital filter based on the output signal of the overflow detection means. A control device for a rotating body, comprising: a synthesizing means for synthesizing the output of the output correcting means and the output of the frequency discriminating means; and a driving means for driving the rotating body by the output of the synthesizing means. . (2) A digital filter has a proportional term obtained by multiplying input data by a coefficient, an accumulation term obtained by accumulating the input data, and an integral term obtained by multiplying the accumulation term by a coefficient. and an addition term that adds the proportional term and the integral term, and an output of the addition term is used as an output signal. (3) The control device for a rotating body according to claim (2), wherein the overflow detection means detects that the integral term of the digital filter exceeds a predetermined upper limit value or lower limit value. (4) The output correction means adds or subtracts a correction value to the output of the digital filter according to the polarity of an output signal of an overflow detection means for detecting an overflow of the digital filter. body control device.