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JPH03167825A - Etching device and etching method - Google Patents

Etching device and etching method

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Publication number
JPH03167825A
JPH03167825A JP30869489A JP30869489A JPH03167825A JP H03167825 A JPH03167825 A JP H03167825A JP 30869489 A JP30869489 A JP 30869489A JP 30869489 A JP30869489 A JP 30869489A JP H03167825 A JPH03167825 A JP H03167825A
Authority
JP
Japan
Prior art keywords
substrate
etching
temperature
plasma
chamber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30869489A
Other languages
Japanese (ja)
Inventor
Kenji Tateiwa
健二 立岩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP30869489A priority Critical patent/JPH03167825A/en
Publication of JPH03167825A publication Critical patent/JPH03167825A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To perform reproducible clean etching by etching a substrate or a semiconductor thin-film of mainly Si on the substrate, raising the temperature of the substrate to 100 deg.C or higher in a vacuum, and evaporating a reaction product remaining on the substrate surface. CONSTITUTION:An SiO2 film 2 and a poly-Si 3 are stacked on a Si substrate 1, resist 4 is applied, and plasma etching is performed with Br2 gas. Then SiBr4 5, a reaction product, is produced on the sides vertical to the substrate 1. When the substrate temperature is raised to 100 deg.C in the same vacuum, SiBr4 5 evaporates into the vacuum. After that, the resist is removed with O2 plasma, and the desired patterning of the poly-Si to is finished. This method makes it possible to perform high-precision etching without lowering the yield which is caused by dust, etc. Besides, when the substrate temperature is controlled with a sensor 28 while placing the substrate 21 on a stage 23 cooled with a liquid N2, and when a chamber 24 covered with a heater 25 is kept at 70 deg.C with a sensor 26 and a measuring instrument 27 and the substrate 21 is kept at -120 deg.C, anisotropic etching can be performed without the deposition of dust.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は高逮 高密度半導体装置の製造におけるエッチ
ング装置およびエッチング方法に関するものであも 従来の技術 従久 半導体基板上に形威したシリコン系の半導体薄膜
をプラズマエッチングする際に 異方性に優れた臭素系
ガスを用いることが微細加工に有利になってきていも 
またこうした異方性エッチングは反応生成物の蒸気圧が
低い範囲においてプラズマエッチングを行うことが一つ
の大きな要因となっていも 臭素系ガスで異方性エッチ
ングが容易に行えるのは常温でのシリコンの臭化物の蒸
気圧が非常に低いためイオンの入射がないサイドウオー
ルなどの場所に於で反応生成物の堆積作用が起こりサイ
ドエッチが生じないため異方性が達威されも 弗素系ガ
スを用いた場合にわいても基板温度を十分に下げること
によって異方性が達戊される。例えばSF6ガスを用い
た場合、基板温度を一120度以下の温度でエッチング
を行うことにより異方性エッチングが達或される(7゜
ロシーシ′ンク′オ7’  10回 ドライ ブ゜ロセ
ス シンホ゜シゝウム;  Proc,  of  1
0thDry process Symposium.
42(1989)参照)。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an etching apparatus and an etching method for manufacturing high-density semiconductor devices. Although the use of bromine-based gases with excellent anisotropy when plasma etching thin films has become advantageous for microfabrication,
Furthermore, one of the major factors in this type of anisotropic etching is that plasma etching is performed in a range where the vapor pressure of the reaction product is low. Because the vapor pressure of bromide is very low, the reaction product accumulates in places such as side walls where ions do not enter, and side etching does not occur, so anisotropy is achieved. In some cases, anisotropy can be achieved by sufficiently lowering the substrate temperature. For example, when SF6 gas is used, anisotropic etching is achieved by etching at a substrate temperature of -120 degrees Celsius or less (7 degrees Celsius 10 times). Um; Proc, of 1
0thDry process Symposium.
42 (1989)).

発明が解決しようとする課題 臭素系ガスを主体に用いるプラズマエッチングに於いて
はその反応生底物である例えばSiBraなどの蒸気圧
の非常に低い生底物が形戒されも こうした蒸気圧の非
常に低い生戊物は反応室のあらゆるところに再付着すも
 すなわち反応室にある半導体基板上にも付着を起こす
。基板の平坦部分にはイオン衝撃があるためにこの部分
には再付着が起こらないものの基板に対して垂直方向の
部分、例えばレジストの側面には再付着がおこも こう
して再付着した反応生或物SiBrsは空気中に基板を
解放した際に空気中の酸素と反応してSi02を形威す
ん またレジスト除去で酸素プラズマ処理を行うことで
さらにSi02に変化すも こうして形威されたSi0
2は通常の硫醜 過酸化水素の洗浄では除去することが
不可能であリバターン形戊に不用な余分なものが基板に
形戒されることになん基板を冷却してエッチングを行う
低温プラズマエッチングの際はチャンバー内の表面に反
応生戊物が堆積しエッチングの再現性の劣化 ダストの
増加等の問題点を有していf,  又 一般的に基板以
外のチャンバー温度は温度制御をしていないためチャン
バー温度の時間変化にともないプラズマ状態が変化して
しまうという欠点を有していf,本発明(よ 上述の課
題に鑑みてなされたもので、エッチング時に形或される
蒸気圧の低い反応生戊物が基板表面に残留することがな
く高精度なエッチングを実現することができ、あるいは
チャンバーに付着する反応生戊物を除去し 常にクリー
ンで再現性のよいエッチングを実現するエッチング装置
およびエッチング方法を提供することを目的とすも 課題を解決するための手段 本発明(1)は上記課題を解決するために 半導体基板
もしくは半導体基板上に形或したシリコンを中心元素と
する半導体薄膜をプラズマ中でエッチングした後、大気
に基板をさらす前に真空中で基板温度を100度以上に
上昇させて基板表面に残留する反応生底物を蒸発させる
ことを特徴とするものであも また 本発明(2)は基板温度を摂氏零度以下の一定温
度に保持し 基板が接触する以外のチャンバー温度を摂
氏70度以上の一定温度に保ちながらプラズマ中でエッ
チングを施すことを特徴とするものであも 作用 本発明は上記構戒(1)により、エッチング終了比大気
中に解放する事なく基板温度を高温に上昇させるた取 
エッチング時に形威される蒸気圧の低い反応生戊物が基
板表面に残留することがなく高精度なエッチングを実現
することができも また上記構或(2)により、チャン
バー表面を高温に保持することでプラズマの再現性良く
表面にダストの原因となる物質を付着させる事なく異方
性エッチングを実現する゛ことができも 実施例 第1図に本発明の第1の実施例における工程断面図を示
す。図において、シリコン基板1上にシリコン酸化膜2
を堆積し その上にポリシリコン3を形或すも 次にレ
ジスト4で所定の領域をパターニングする(第1図a)
。次にBrzガスでプラズマエッチングを行う。エッチ
ングガスはその他のガ入 例えばHBrでも同様であも
 エッチング途中での断面図が第1図bであも 基板l
と垂直な側面には反応生戊物であるSiBr4( 5 
)が形威されている。エッチング終了時には第l図Cの
ようにSiBr4 ( 5 )のサイドウオールが形或
されていもこの後同じく真空中で基板温度を100度ま
で上昇させる。これによりサイドオールに形戊されてい
るSiBr4 ( 5 )は真空中に蒸発し基板表面に
はSiBr4は残らない(第1図d)。この眞 酸素プ
ラズマによるレジスト4除去を行うことで目的とするボ
リシリコ.ンのパターニングが終了する(第1図e)。
Problems to be Solved by the Invention In plasma etching that mainly uses bromine-based gas, the use of reactive biobottoms such as SiBra, which has a very low vapor pressure, is prohibited. The raw materials with a low temperature re-deposit everywhere in the reaction chamber, including on the semiconductor substrate in the reaction chamber. Because there is ion bombardment on the flat parts of the substrate, re-deposition does not occur in this part, but re-deposition occurs in parts perpendicular to the substrate, such as the sides of the resist. When the substrate is exposed to the air, SiBrs reacts with oxygen in the air to form Si02.Also, when the resist is removed and oxygen plasma treatment is performed, it further changes to Si02.
2. Normal sulfur filth cannot be removed by hydrogen peroxide cleaning, and in the reversal process, unnecessary excess material is deposited on the substrate.Low-temperature plasma etching involves cooling and etching the substrate. In this case, reaction products accumulate on the surface inside the chamber, resulting in problems such as deterioration of etching reproducibility and increase in dust.In addition, the temperature of the chamber other than the substrate is generally not controlled. Therefore, the plasma state changes as the chamber temperature changes over time.The present invention, which was developed in view of the above-mentioned problems, has the disadvantage that the plasma state changes as the chamber temperature changes over time. Etching equipment and etching method that can achieve high-precision etching without leaving any debris on the substrate surface, or remove reaction product debris that adheres to the chamber to always achieve clean etching with good reproducibility. Means for Solving the Problems The present invention (1) solves the above problems by subjecting a semiconductor substrate or a semiconductor thin film formed on a semiconductor substrate to a semiconductor thin film containing silicon as a central element in plasma. After etching, the temperature of the substrate is raised to 100 degrees or more in vacuum to evaporate the reactive biomass remaining on the substrate surface before exposing the substrate to the atmosphere. 2) is characterized by etching in plasma while maintaining the substrate temperature at a constant temperature below zero degrees Celsius, and maintaining the chamber temperature other than that in contact with the substrate at a constant temperature above 70 degrees Celsius. Based on the above-mentioned principle (1), the present invention provides an approach to raise the substrate temperature to a high temperature without releasing the etching end ratio into the atmosphere.
High-precision etching can be achieved without the reaction product with low vapor pressure remaining on the substrate surface during etching. Also, with the above structure (2), the chamber surface is maintained at a high temperature. This makes it possible to realize anisotropic etching with good plasma reproducibility without depositing substances that cause dust on the surface. shows. In the figure, a silicon oxide film 2 is placed on a silicon substrate 1.
After depositing polysilicon 3 and forming polysilicon 3 on it, a predetermined area is patterned with resist 4 (Fig. 1a).
. Next, plasma etching is performed using Brz gas. The etching gas may be used with other gases, such as HBr, or even if the cross-sectional view in the middle of etching is as shown in Figure 1b.Substrate l
SiBr4 (5
) is clearly expressed. When the etching is completed, a side wall of SiBr4(5) is formed as shown in FIG. As a result, the SiBr4 (5) formed into sidealls is evaporated in vacuum, and no SiBr4 remains on the substrate surface (FIG. 1d). By removing the resist 4 using oxygen plasma, the target material can be removed. The patterning is completed (Fig. 1e).

第2図はSiCln、TiC1n及びSiBraにおけ
る温度に対する蒸気圧曲線を示す(シーアールシーハン
ト゛フ1フク オ7ゝ ケミストリ アントゝ 7イシ
ゝクフス;  CRC  HandBook  ofC
hemistry and Physics 1984
−1985参照)。以下、基板温度を100度まで上昇
させることによりSiBr4(5)のサイドウオールが
蒸発する理由を説明す&  SiBrnの沸点は154
cASiC14の沸点は57. 57Cであも 常温(
〜20C)のエッチングではSiClzではプラズマ中
は減圧のたべ 堆積物がほとんどない力<  SiBr
nは堆積作用が起こ’h  TiCbはチャンバーから
早く出し入れを行なうと堆積物が残ることがある力( 
 SiCl4ではこのようなことはなI,%つまり、T
iCl4における常温での蒸気圧が10mmHg (T
orr)であるたWs.  10mmHg付近以下では
堆積物残留が起こり得も これを避けるために(;L 
 S i B r sにおいて基板温度を高温にして蒸
気圧を上げる必要があも チャンバーのように常時減圧
状態のものでは70C(蒸気圧10nmHg)以上必要
玄 ウェハのようにすぐに出し入れするものはもう少し
高温が必要でIOOC以上が必要であん よって、基板
温度を100度まで上昇させることによりSiBr4 
( 5 )のサイドウオールを蒸発させることができも
第3図に本発明の第2実施例におけるエッチング装置の
概要断面図を示も 図においてシリコン基板2lは液体
窒素22で冷却したステージ23に載置されていも 基
板温度は温度センサーA(28)とコンピュータ(測定
器)20により正確に制御されていも チャンバー24
はヒーター25で覆われていて温度センサーB(26)
とコンビュータ(測定器)27によりチャンバー温度が
正確に制御されていも チャンバーは真空ポンプにより
真空に引かれていも このように温度のパラメータを正
確に制御したうえでRIEを行うことにより再現性の良
いエッチングを行う。この隊 チャンバー24自体は常
温より高い一定の高鳳 ここでは70度に保持されてい
るためプラズマ中の反応生或恢 プラズマボリマー等が
付着することが殆どなく、エッチング中にポリマーが剥
がれてシリコン基板2lヘダスト付着しなくなム しか
も基板2lを十分に冷却し摂氏零度以下の温嵐例えば−
120度に保持しているので異方性に優れたエッチング
を行うことができも 発明の効果 以上の説明から明らかなように 本発明によればダスト
等による歩留低下を起さt 高精度なエッチングを行な
うことができるたべ 超LSIの歩留を向上させること
ができも
Figure 2 shows the vapor pressure versus temperature curves for SiCln, TiCln, and SiBra (CRC HandBook ofC).
hemistry and physics 1984
-1985). Below, we will explain why the sidewall of SiBr4 (5) evaporates by increasing the substrate temperature to 100 degrees & The boiling point of SiBrn is 154 degrees.
The boiling point of cASiC14 is 57. Even at 57C, at room temperature (
In etching at ~20C), SiClz requires a reduced pressure in the plasma.
n is the force at which deposition occurs;
This is not the case with SiCl4.In other words, T
The vapor pressure of iCl4 at room temperature is 10 mmHg (T
orr) was Ws. To avoid this, deposits may remain below around 10 mmHg (;L
In SiBrS, it is necessary to increase the vapor pressure by raising the substrate temperature to a high temperature.For chambers that are constantly under reduced pressure, 70C (vapor pressure 10 nmHg) or higher is required.For items that are taken in and out quickly, such as wafers, it is a little more necessary. A high temperature is required, and it is not necessary to exceed the IOOC. Therefore, by raising the substrate temperature to 100 degrees, SiBr4
In the figure, a silicon substrate 2l is placed on a stage 23 cooled with liquid nitrogen 22. Even if the substrate temperature is accurately controlled by the temperature sensor A (28) and the computer (measuring device) 20, the chamber 24
is covered with heater 25 and temperature sensor B (26)
Even if the chamber temperature is accurately controlled by the computer (measuring device) 27, or the chamber is evacuated by a vacuum pump, performing RIE after accurately controlling the temperature parameters will result in good reproducibility. Perform etching. The chamber 24 itself is kept at a constant temperature of 70 degrees, which is higher than room temperature, so there is almost no adhesion of plasma polymers, etc. due to reactions in the plasma, and the polymer peels off during etching. This prevents dust from adhering to the substrate 2l.Moreover, the substrate 2l is sufficiently cooled to prevent temperature storms below zero degrees Celsius, e.g.
Since the temperature is maintained at 120 degrees, it is possible to perform etching with excellent anisotropy. However, as is clear from the above explanation, according to the present invention, there is no reduction in yield due to dust, etc. It is possible to perform etching and improve the yield of VLSI.

【図面の簡単な説明】[Brief explanation of the drawing]

第l図は本発明の第1の実施例における工程断面は 第
2図はSiC1n、TiC1n及びSiBr4における
温度に対する蒸気圧曲線を示す特性阻 第3図は本発明
の第2の実施例におけるエッチング装置の断面概略図で
あも 1.2 1・・・シリコン基坂 2・・・シリコン酸化
風3・・・ポリシリコン、 4・・・レジスト、 5・
・・3iBra、’IO.27・・・コンピュー久 2
2・・・液体窒魚 23・・・ステージ、24・・・チ
ャンバー、25・・・ヒー久 26.28・・・温度セ
ンサー。
Fig. 1 is a process cross section in the first embodiment of the present invention. Fig. 2 is a characteristic diagram showing vapor pressure curves with respect to temperature in SiC1n, TiC1n, and SiBr4. Fig. 3 is an etching apparatus in the second embodiment of the present invention. 1.2 1...Silicon base slope 2...Silicon oxidation wind 3...Polysilicon, 4...Resist, 5.
...3iBra,'IO. 27...computer 2
2...Liquid nitrogen fish 23...Stage, 24...Chamber, 25...Hiku 26.28...Temperature sensor.

Claims (3)

【特許請求の範囲】[Claims] (1)基板温度を摂氏零度以下の一定温度に保持し、基
板が接触する以外のチャンバー温度を摂氏70度以上の
一定温度に保持することを特徴とするエッチング装置
(1) An etching device characterized by maintaining the substrate temperature at a constant temperature of 0 degrees Celsius or lower, and maintaining the chamber temperature other than the chamber where the substrate comes into contact at a constant temperature of 70 degrees Celsius or higher.
(2)半導体基板もしくは半導体基板上に形成したシリ
コンを中心元素とする半導体薄膜をプラズマ中でエッチ
ングした後、大気に基板をさらす前に真空中で基板温度
を100度以上に上昇させて基板表面に残留する反応生
成物を蒸発させることを特徴とするエッチング方法
(2) After etching a semiconductor substrate or a semiconductor thin film with silicon as the main element formed on a semiconductor substrate in plasma, the substrate temperature is raised to 100 degrees or more in a vacuum before exposing the substrate to the atmosphere. An etching method characterized by evaporating reaction products remaining in
(3)基板温度を摂氏零度以下の一定温度に保持し、基
板が接触する以外のチャンバー温度を摂氏70度以上の
一定温度に保ちながらプラズマ中でエッチングを施すこ
とを特徴とするエッチング方法。
(3) An etching method characterized by performing etching in plasma while maintaining the substrate temperature at a constant temperature of 0 degrees Celsius or lower, and maintaining the chamber temperature other than that in contact with the substrate at a constant temperature of 70 degrees Celsius or higher.
JP30869489A 1989-11-28 1989-11-28 Etching device and etching method Pending JPH03167825A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30869489A JPH03167825A (en) 1989-11-28 1989-11-28 Etching device and etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30869489A JPH03167825A (en) 1989-11-28 1989-11-28 Etching device and etching method

Publications (1)

Publication Number Publication Date
JPH03167825A true JPH03167825A (en) 1991-07-19

Family

ID=17984159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30869489A Pending JPH03167825A (en) 1989-11-28 1989-11-28 Etching device and etching method

Country Status (1)

Country Link
JP (1) JPH03167825A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0734047A2 (en) * 1995-03-20 1996-09-25 Hitachi, Ltd. Plasma processing method and apparatus
US5685950A (en) * 1993-12-29 1997-11-11 Sony Corporation Dry etching method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5753939A (en) * 1980-09-17 1982-03-31 Matsushita Electric Ind Co Ltd Dry etching method for thin film
JPS6230329A (en) * 1985-07-31 1987-02-09 Toshiba Corp Dry etching device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5753939A (en) * 1980-09-17 1982-03-31 Matsushita Electric Ind Co Ltd Dry etching method for thin film
JPS6230329A (en) * 1985-07-31 1987-02-09 Toshiba Corp Dry etching device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5685950A (en) * 1993-12-29 1997-11-11 Sony Corporation Dry etching method
EP0734047A2 (en) * 1995-03-20 1996-09-25 Hitachi, Ltd. Plasma processing method and apparatus
EP0734047A3 (en) * 1995-03-20 1997-04-02 Hitachi Ltd Processing method and apparatus for plasma
KR100399542B1 (en) * 1995-03-20 2004-01-07 가부시끼가이샤 히다치 세이사꾸쇼 Plasma processing method and apparatus

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