JPH03165645A - Multiplex circuit - Google Patents

Abstract

PURPOSE:To select impartial selection to each node and to multiplex output data of each node by interconnecting selection circuits with a control line. CONSTITUTION:The multiplex circuit consists of a transmission enable discrimination circuit 35, a data transmission circuit 11, a storage circuit 54 storing the priority of data transmission enable, and a circuit 52 outputting a data transmission right to a succeeding node. Then the data transmission right is connected to a data transmission right input of a succeeding adjacent node to form a loop and the output of the data transmission circuit 11 in each data is subjected to bus connection to constitute the multiplex circuit of the node data. Thus, a node succeeding to the node selected precedingly reaches the uppermost stream and the data transmission right is sent to each node and a node having a selection circuit 10 receiving the data transmission right and the transmission request signal acquires the data transmission permission in the timing of discriminating the data transmission permission and sends the data to a data multiplex line and the deviation of the service is avoided for the selection with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiplex circuit that multiplexes data for selecting one of a plurality of requests onto a single transmission line.

Conventional technology Asynchronous transfer, in which information is divided into predetermined sizes (herein referred to as cells) and multimedia is multiplexed and transferred, is attracting attention. Such a transfer method requires a circuit that multiplexes cells at high speed, but conventional multiplexing circuits that select one request from multiple requests and send the output from the selected circuit to a single transmission line There are the following types of selection circuits used for:

First, there is a selection circuit that starts a search from a certain node. This is a method in which the search starts from a certain node every time a selection is made, and when a node making a transmission request is found, that node is selected and given permission to transmit data.

The problem to be solved by the invention is to use a method in which the search starts sequentially from the node following the previously selected node. However, the selection circuit described above has the following problems.

If the selection algorithm of the selection circuit always searches from a fixed position, some items may be selected as soon as a request is made, and others may not be selected for a long time even if a request is made. There is a problem that the service is biased.

Also, how to start searching sequentially from the node next to the node selected last time (table) The software takes a long time to process and cannot search many nodes.Also, it searches sequentially from the node next to the node selected last time to see if there is a request to send. Even if a node that has already been searched issues a transmission request during the period, that node will not be selected (-In this way, there is a probability that there will be a time period in which no node is selected even though there is a transmission request). There is a problem that it is expensive.There is also a problem that it is not scalable unless you know the maximum number of nodes.

The first object of the present invention is to provide a data multiplexing circuit having a simple GBS hardware configuration and a selection circuit capable of selecting services without bias. The object of the second invention is to provide a data multiplexing circuit that can finely control service ratios with a simple hardware configuration.

Means for Solving the Problems First Invention (Human) A transmission permission determination circuit which inputs data transmission rights and a data transmission request from its own node and gives permission to transmit data of its own node; The circuit consists of a data transmission circuit that transmits data from a node, a storage circuit that holds priority for data transmission permission, and a circuit that outputs data transmission rights to the next node. This is a node data multiplex circuit in which the output of the data transmission circuit in each node is connected to the power input, and the next node is connected in the same way to form a loop.The output of the data transmission circuit in each node is connected to the bus.

Second Invention (Companion) A data multiplexing circuit has a priority indicating circuit for externally instructing the priority of data transmission permission instead of the storage circuit of the first invention.

Effects The first invention has the above-described configuration, so that the next node selected last time becomes the most upstream node, transmits the data transmission right to each node, and receives and receives the data transmission right and the transmission request signal at the data transmission permission determination timing. A node with a selector circuit can obtain permission to send data and send data on the data multiplex.

According to the second invention, with the above-described configuration, the node designated by the priority designation circuit becomes the most upstream node and transmits data transmission rights to each node, and can transmit data to the data multiplex line as in the first invention. Embodiment FIG. 1 shows the overall configuration of a multiplex circuit in a first embodiment of the first invention, and FIG. 2 shows a configuration diagram of the selection circuit in FIG. 1.

In FIG. 1, 10 is a selection division, 11 is a data transmission division, 20 is a node, and 30 is a data multiplex line. In FIG. 2, 41 is a data sending right input line, 42 is a data sending right output line, 43 is a data sending request signal line 44
51 is a logic structure 52 is a logic generator
53 is a data transmission permission determination circuit; 54 is a storage circuit; and regarding the multiplex circuit of this embodiment configured as described above,
The operation will be explained below.

Data sending circuit 11 (friend) When ready to send data, first send sending request signal (RDY) to selection circuit IO.
When the data sending circuit 11 receives the sending permission signal (OE) from the selection circuit 1O, it sends the data to the data multiplex line 30. Therefore, the data sending circuit outputs of each node do not overlap on the data multiplex line 30 (~ The selection control operation by the selection circuit will be explained below. The data transmission right output line 42 is connected to the data transmission right power line 41 of the next adjacent selection circuit, and even though the selection circuit 10 as a whole is connected in a loop form, the data transmission right input (ENi) and the transmission permission signal are connected. (RD
If the two signals Y) are both active at the determined timing (judgment timing), the transmission permission determination circuit 5
3 outputs an output permission signal (OE) to the data output circuit 11 in its own node, and outputs an active signal to the memory circuit 54 (if the own node is the node that last sent data to the data multiplex line 30). If not, output an active signal. If it is the own node that sent the data, the operation is as follows: At the judgment timing, the data sending authority
If the data transmission right is input from 1, the memory circuit 54 will continue to output an active signal until the next judgment timing, and if the data transmission right is not manually input, the storage circuit 54 will not output an active signal after the judgment timing. -On the other hand, when the memory circuit 54 output is not active, the following operation is performed. At the judgment timing, both the data transmission right and the transmission request signal from the own node must be input +2
The output of the memory circuit 54 remains active until the next judgment timing, unless there is human power from both memory circuits 5
Although the 4 output continues to be inactive, the data transmission right output (ENo) i;t,, the data transmission right input (EN
The operation of each node using the sending right based on the circuit configuration which is the logical product of i), the inversion of the sending permission signal (RDY), and the output of the storage circuit 54 is as follows.

+i logical sum 5 when own node sends data last
The second output becomes active and passes data transmission rights to the next node and subsequent nodes (downstream side). Each node is
If the data transmission right is received from the data transmission right input line (from the upstream side), and the data transmission circuit in the own node is issuing a transmission request (RDY), the data transmission circuit in the own node receives the data transmission right (from the upstream side). Output sending permission (OE) a
In this case, the AND 51 output becomes non-active, and when the storage circuit 54 is non-active, +i OR 5
2 output becomes non-active, and the data transmission right is not passed to the next node. In the case (tomo), the output of AND 51 becomes active, which causes the output of OR 52 to also become active, passing the right to send data to the next node and beyond. Even though the own node has received the right to send, the Selection circuit 10 for the case where the transmission right is passed to nodes after the node
When a node inputs a sending request (RDY), the data sending right output immediately becomes non-active, and it is possible to take away the data sending right from a node downstream from the own node. Even if the highest priority data transmission right is given to a node, if there is no output request from its own node, each node will pass the acquired data transmission right to the downstream node.

If each node has data transmission rights input to itself (
Yes, there is a possibility of obtaining transmission permission by sending a transmission request. However, if a transmission request occurs to a node upstream of the own node before the decision timing to grant transmission permission, the data transmission right will be lost.4 As described above, in this embodiment, each selection circuit is connected in a loop. By transmitting the data transmission right through a single line, equal selection multiplexing can be performed for each node. FIG. 3 shows the overall configuration of a multiplex circuit in a second embodiment of the first invention.

In FIG. 3, lO is the selection same area, 11 is the data sending circuit, 20 is the note t', and 30 is the data multiplex line.The selection circuit 10 and the data sending circuit 11 are those having the same function as the first embodiment. use Differences from the first embodiment (more
One data transmission circuit 11 is connected to one or more selection circuits 10. In other words, the transmission request of the data transmission circuit 11 is connected to the plurality of selection circuits 10, and the output from the selection circuit 10 is transmitted. Even if the enable signal is connected to the data sending circuit 11 after being ORed, each selection circuit is equally selected as described in the first embodiment.
If the number of selection circuits is N, the ratio of data transmission circuits connected to M selection circuits being selected is M/N.As described above, in this embodiment, ζ is connected to data transmission circuits. By changing the number of selection circuits, it is possible to adjust the rate at which each data sending circuit is selected, that is, the rate at which data can be sent to the multiplex line 30. The force of placing multiple selection circuits adjacent to each other (actually, it is better to distribute them in a loop to achieve more even selection, but Figure 4 shows the overall configuration of the multiplex circuit in the third embodiment of the first invention). , FIG. 5 shows a configuration diagram of the selection circuit in FIG. 4. In FIG. 4, 10 is a selection section, 11 is a data sending circuit 11, 20 is a note t', and 30 is a data multiplex line. .

In Fig. 5, 41 and 45 are data transmission authority human power wind 4
2 and 46 are data transmission right input lines 43 are data transmission right input lines 44 are data transmission permission signals @ 51 are logic machines 52
53 is a logic circuit, 54 is a memory circuit, and 54 is a memory circuit.About the multiplex circuit of this embodiment configured as described above,
The operation will be described below, but the roles and operations of each block in the circuit are almost the same as in the first embodiment. The difference is that two control lines are used for connection with adjacent nodes.a One line is for transmitting data transmission rights, ENi,
ENo), and the other one transmits a signal indicating whether the own node has priority transmission rights (OEi, 0EO).

Outsourcing Authority (OEi)1. ? , is the same as the memory circuit output of the first embodiment, and is transmitted from the memory circuit output of the adjacent node.Therefore, in this configuration, information on whether or not the own node has the highest priority transmission right is transmitted from the memory circuit output of the adjacent node. Although it can be known from the input line 45, if the node inputting the transmission right (OE i) sends the transmission request signal, the transmission permission will be obtained at the next judgment timing.As described above, according to this embodiment, In the same way as in the first embodiment, it is possible to easily realize a selective multiplexing circuit that provides equal service to each node, but it is also possible to grasp whether or not the own node has priority transmission rights, and to obtain priority transmission rights. If the data transmission circuit has the following, permission to transmit the next determination timing can be obtained without fail.It is also possible to adopt a configuration similar to the second embodiment and adjust the ratio at which each data transmission circuit is selected.

FIG. 6 shows the overall configuration of the multiplex circuit in the fourth embodiment of the first invention, FIG. 7 shows the configuration of the data generation circuit in FIG. 6, and FIG. 8 shows the sub selection in FIG. 7. 1 shows a configuration diagram of a circuit.

In FIG. 6, 10 is a selection group, 12 is a data sending group, 20 is a node, and 30 is a data multiplex line. In FIG. Sub-data multiplex line 115 is a logical sum.

In FIG. 8, 41 is a data sending right input line, 43 is a data sending right input line, 44 is a data sending request signal wave, 47 is a subnode data sending right input device, 51 is a logic machine 52 is a logic line 53 The data transmission permission determination port 54 is a storage circuit.

Data sending circuit 111 in FIG. 7! i Even if the circuit has the same configuration as the first embodiment, etc. Also, the selection circuit 10 in FIG. 6 may have the same configuration as the first embodiment, etc.; Regarding multiple circuits,
The operation will be explained below, but first, the operation of the sub selection circuit 110 will be explained using FIG. Although the configuration and operation in FIG. 8 are almost the same as the selection circuit of the first embodiment (FIG. 2), the difference is that the subnode data transmission right input line 47 is connected to the transmission permission determination circuit 53. Judgment circuit 531: If the data sending right input (ENi), subnode data sending right input (ENM), and data sending request (RDY) are all active at the sending judgment timing, activate the data sending permission signal (OE) a Next Although the data sending circuit 12 will be explained using FIG. 7, the configuration and operation in FIG.
The power exchange is almost the same as in Figure 1), except that the data transmission request (RDYM) of the data transmission circuit 12 is obtained by ORing the transmission request signals from each node, and the subnode data transmission right (OEM) is input. According to the configuration of the data sending circuit 12 as described above, a sending request from a subnode becomes a data sending request (RDYM) and is output to the selection circuit IO in the overall configuration (Fig. 6). It turns out. On the other hand, the transmission permission signal output from the selection circuit IO becomes the data transmission right (OEM) of the subnode and the selection circuit 1
Finally, the overall configuration will be explained using FIG. 6.

The configuration and operation of FIG. 6 are the same as those of the overall configuration of the first embodiment (FIG. 1). The data multiplex line 130 in the data sending circuit 111 is connected to the data multiplex line 3 by bus.
0 and a In this embodiment, as already explained, there is a loop (referred to as a subloop) that conveys the L data transmission right in the data selection circuit 12, resulting in a double loop structure (hereinafter referred to as a subloop). , the transmission loop for the data transmission right in FIG. 6 will be called the main loop).The data transmission circuit 111 (the seventh
In this case, when the data sending circuit 111 issues a sending request, it is transmitted to the selecting circuit 10 (in the overall configuration in FIG. 6). If the reception is received, the data transmission circuit 11
1 can send data to the data multiplex 130, but the selection circuit (10, 1
10) On the other hand, the user must not have the right to send data1.
It is necessary to wait to send data to the data multiplex line 130 until fS data sending rights are obtained. Data sending rights on the subloop in the data sending circuit 12 of the node 20 that has received data sending rights on the main loop. (It is transmitted on the subloop and passed to the data transmission circuit 111 that has issued the transmission request.) The data transmission right is transmitted to the subloop 1 in the node that has not received the data transmission right on the 4-X main loop. The operation of the circuit is two-step, since it remains within the subnode 120 that sent out the data last in the node 20. First, it receives RDYM, which is the sum of the sending request signals from each subnode, and selects the one on the main loop. Sending permission is output from circuit 10. After that, the right to send data on the subloop within the node for which sending permission was issued is transmitted, and one subnode is selected. Through this control, the nodes on the main loop are evenly distributed. Furthermore, subnodes on subloops within one node are also selected at equal proportions within the subloop.

As described above, according to this embodiment, many nodes are
This eliminates the need for long control lines that are connected on two loops and transmits data transmission rights.This makes it possible to increase the selection speed of the entire circuit and improve overall reliability. Also, by changing the number of nodes in the subloop, one data transmission circuit 111
The selected ratio of the data transmission circuit 12 described above as a circuit having a sub-loop structure may also be in the form of a mixture of the nodes of the first embodiment and the nodes of this embodiment. I do not care.

FIG. 9 shows the overall configuration of the multiplex circuit in the second embodiment of the invention, and FIG. 10 shows the configuration of the selection circuit in FIG. 9.

In FIG. 9, 1o is a selection port, 11 is a data transmission circuit, 20 is a notebook, and 30 is a data multiplex line 40 is a priority indicating circuit.

In FIG. 1O, 41 is a data sending right input line 42 is a data sending right output @ 43 is a data sending request input line 44
48 is a data sending permission signal salt; 48 is a data sending priority input; 52 is a logical product; 53 is a data sending permission determination circuit; explain.

When the data sending circuit 114 is ready to send data, first send a sending request signal (RDY) to the selection circuit 10.
Output. When the data sending circuit 11 inputs the sending permission signal (OE) from the selection circuit 1O, it sends the data to the data multiplex line 3o. However, each selection circuit Ct and a plurality of nodes output the sending permission signal (OE) in the node at the same timing. control so that it does not occur. Therefore, the data sending circuit outputs of each node do not overlap on the data multiplex line 30.Hereinafter, the selection control operation by the selection circuit will be explained.

The data transmission right output line 42 of each selection circuit 1O is connected to the data transmission right input line 41 of the next adjacent selection circuit. ) and transmission permission signal (RD
If the three signals Y) and data transmission priority (PR) are both active at the determined timing (judgment timing), the transmission permission determination circuit 53 transmits the transmission permission signal (OE) to the data transmission circuit 11 in its own node. Output to.

Data transmission right output (ENo)? , t, The data transmission right and transmission priority ( PR
) The operation of each node using the data transmission right (PR) is as follows: If the data transmission priority (PR) of the own node is active, or the data transmission right (ENi) is input from the data transmission right input line 41.
If the data transmission request (RDY) of the own node is not active, the logical sum 52 output becomes active, and the data transmission right is passed to the next node (downstream). To the judgment timing Data transmission right (EN) from the data transmission right input line (from the upstream side)
i) Or, the data transmission priority (PR) is received and the data transmission circuit in the own node makes a transmission request (RDY).
If the node has issued a data transmission permission (OE), it outputs data transmission permission (OE) to the data transmission circuit in its own node. In this case, the data transmission request (RDY) is active, so
The output of the AND 51 becomes inactive, and the right to send data is not passed to the next node.

For the case where the own node has received the sending right or sending priority right but passes the sending right to the next node onwards. When the selection circuit 10 inputs the sending request (RDY), the data sending right output is immediately Even if the node becomes non-active and can deprive the nodes downstream of its own node of the data transmission right, the priority instruction circuit 40 still gives the data transmission priority to each node (
PR) is output. Priority indication circuit 4゜1 consists of, for example, a memory and a decoder, etc. Even if the node number that gives priority is written in the memory, the memory output is decoded and becomes the data transmission priority of each node. It is possible to change the node to which priority is given by sequentially changing the address of the node.By changing the data stored in memory, the frequency and distribution of sending priority to each node can be changed, and the proportion of services that select each node can be changed. can be set in detail.

As described above, according to this embodiment, the frequency and distribution of giving priority to each node can be set, and the ratio of services to each node can be finely controlled and selectively multiplexed. Furthermore, since the data transmission right signal passes through only two gates per selection circuit, it is transmitted through many selection circuits in a short period of time, allowing selection determination processing to be performed in a short period of time.

As described in detail of the invention, according to the first invention, by connecting each selection circuit with a control line, each node can be equally selected and the output data of each node can be multiplexed. Its practical effect is due to the second invention ('L
Data can be multiplexed by setting the ratio of services to each node in detail, and the practical effect is
~

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a multiplex circuit according to an embodiment of the first invention. FIG. 2 is a configuration diagram of a selection circuit existing in FIG. 1. FIG. 3 is a diagram of a second embodiment of the first invention. Overall configuration diagram of the multiplex circuit Figure 4 is an overall configuration diagram of the multiplex circuit of the third embodiment of the first invention Figure 5 is the configuration of the selection circuit existing in Figure 4 An overall configuration diagram of a multiplex circuit according to the fourth embodiment of the invention.
A configuration diagram of the data sending circuit shown in the figure.
FIG. 9 is a block diagram of the selection circuit shown in the figure. FIG. 10 is a block diagram of the selection circuit shown in FIG. 9.・Selection port 11L12...Data sending circuit 2
0-・-Node, 30...Data multiplex 40・
・・Priority indication wide 41, 45・・・・Sending right human power line 4
2, 46... Sending right output salt 43... Data sending request a 44... Data sending permission signal line 47... Subloop data sending right power machine 48... Data sending priority right input wind 51...・Logic structure 52...Logic tax 53・
...To the sending permission judgment port 54...Storage circuit

Claims (2)

[Claims] (1) A transmission permission determination circuit that determines whether or not to transmit data based on the data transmission right received from an adjacent node and the data transmission request signal of its own node, and grants transmission permission; a memory circuit that stores information about the node that last obtained permission to send data; and a storage circuit that outputs data sending rights in order to transfer the data sending rights received from an adjacent node to another adjacent node. The data transmission right output is connected to the data transmission right input of the next adjacent node, and the data transmission right output is also connected to the next node in a loop form, and the output of the data transmission circuit in each node is shared. A multiplex circuit characterized by a bus. (2) A priority instruction circuit that instructs which node has the transmission priority for each opportunity to transmit data, and a data transmission right received from an adjacent node, a data transmission request signal of the own node, and the priority. a transmission permission determination circuit that determines whether or not to transmit data from an adjacent node and grants transmission permission; a data transmission circuit that transmits data in response to the transmission permission signal; and a transmission permission determination circuit that transmits data received from an adjacent node to another adjacent node. The data transmission right output is connected to the data transmission right input of the next adjacent node, and the data transmission right output is connected to the data transmission right input of the next adjacent node. A multiplex circuit characterized in that the outputs of data sending circuits in nodes are made into a common bus.