JPH03165133A - Phase adjustment circuit - Google Patents

Abstract

PURPOSE:To realize phase adjustment circuit with low cost and simple circuit constitution by controlling the supply of an input clock fed to a communication interface control circuit so as to match the phase of a master clock and the transmission clock. CONSTITUTION:A transmission clock TCK outputted from a communication interface control circuit 11 is set to a flip-flop 13 in the falling timing of a master clock MCK. When a phase difference between the transmission clock TCK and the master clock MCK is within a half period, an output signal OK of level 1 is outputted from the flip-flop 13. In this case, a gate signal GATE of level 1 is outputted from a flip-flop 14. Thus, a clock CLK twice the master clock MCK is fed from an AND gate 15 as the input clock CK, and as a result, the communication interface control circuit 11 keeps outputting the transmission clock TCK in phase with the master clock MCK. Thus, the phase adjustment circuit with simple constitution and low cost is realized.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a phase adjustment circuit, and particularly to a communication interface control that generates a transmission clock by dividing an input clock, which is a predetermined multiple of a master clock, by a predetermined frequency. The present invention relates to a phase adjustment circuit that synchronizes a master clock and a transmission clock in a relay device equipped with the circuit.

(Prior Art) Generally, a relay device used in a communication system is provided with a plurality of communication interface control circuits. Each of these communication interface control circuits is implemented as an LSI, and receives an input clock that is, for example, double the common master clock, and divides the frequency by two to generate a transmission clock.

Although it is desirable that the transmission clocks generated from these communication interface control circuits have the same phase, in reality, the phases of the transmission clocks differ due to differences in delay time inside each LSI. Therefore, within the relay device, a phase adjustment circuit is required to synchronize the transmission clock of each communication interface control circuit with the master clock.

Conventionally, PLL circuits are commonly used as phase adjustment circuits. This PLL circuit has a digital PLL
There are two types of circuits: analog PLL circuits and analog PLL circuits, both of which have the advantage of being able to accurately adjust the position F[I. However, both digital PLL circuits and analog PLL circuits have complicated configurations.
The L circuit requires a high frequency clock, and the analog PLL circuit requires a complex circuit film with 100 circuits.
Is required. For this reason, when a phase adjustment circuit is configured using a PLL circuit, the configuration becomes complicated and the cost becomes high.

(Problems to be Solved by the Invention) Conventionally, a PLL circuit has been used as a phase adjustment circuit, which has the drawbacks of complicated configuration and high cost.

This invention was made in view of these points, and it is easy to use +1t.
The purpose of this invention is to provide a low-cost phase adjustment circuit with a simple circuit configuration.

[Structure of the Invention (Means for Solving the Problems) The phase adjustment circuit according to the present invention is provided with an input clock that is a predetermined times the master clock, divides the input clock by a predetermined frequency, and generates a transmission clock that is synchronized with the master clock. A communication interface control circuit that generates a communication interface control circuit, and a phase difference that compares the phases of the transmission clock generated by the communication interface control circuit and the master clock, and generates a predetermined detection signal when the phase difference is equal to or more than half a cycle. detection means; and clock supply control means for inhibiting the input clock from being supplied to the communication interface control circuit for a period of one clock of the input clock in response to a detection signal generated from the phase difference detection means. The master clock and the transmission clock are matched in phase by controlling supply of an input clock.

(Function) In this phase adjustment circuit, a detection signal is generated when the phase difference between the transmission clock and the master clock is equal to or more than half a cycle. When this detection signal is generated, the input clock is prohibited from being supplied to the communication interface 1 and the line circuit for a period of one clock of the input clock. For this reason, the frequency division operation of the communication interface 1111 control circuit is not performed by one pulse of the input clock, so the phase of the transmission clock is delayed by half the period. As a result, the phase difference between the transmission clock and the master clock is matched. In this way, this phase adjustment circuit has a configuration in which the phases of the master clock and the transmission clock are matched by controlling the supply of the input clock, so that 100 circuits and high frequency clocks are not required. Therefore, a low-cost phase adjustment circuit can be realized with a simple configuration.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a phase adjustment circuit according to a first embodiment of the present invention. This phase adjustment circuit uses master clock MCK
and the transmission clock T of the communication interface control circuit 11
This is to match the phase with CK, and the multiplier circuit 1
2, flip-flop 13°14, AND gate 15,
It is equipped with an inverter 18.17.

Master clock MCK is inverted by inverter 18 and supplied to clock input terminal C of flip-flop 13 and also supplied to multiplier circuit 12 . The multiplier circuit 12 multiplies the mask clock MCK by a predetermined value and generates it as a clock CLK. Multiplier circuit 12
The multiplication ratio of is determined to correspond to the frequency division ratio of the communication interface control circuit it. For example, when the communication interface control circuit 11 frequency-divides the input clock CK by two to generate the transmission clock TCK, the multiplication ratio by the multiplier circuit 12 is set to two.

Master clock MC doubled by multiplier circuit 12
K is supplied to one input of AND gate 15 as clock CLK. Further, the clock CLK is inverted by the inverter 17 and then supplied to the clock input terminal C of the flip-flop 14.

The flip-flop 13 receives the transmission clock TCK and mask clock MC from the communication interface control circuit 1.
The transmission clock TCK is supplied to its data input terminal, and the inverted mask clock MCI is supplied to its clock input terminal C. The Q output of the flip-flop 13 is supplied to the data input terminal of the flip-flop 14 as an output signal OK signal. That is, when the phase difference between the transmission clock TCK and the master clock MCI is within half a cycle, the flip-flop I3 generates a "12 level output signal OK,"
If the phase difference is more than half a cycle, an output signal OK of "0" level is generated.

The flip-flop 14 generates a gate signal GATE according to the phase comparison result of the flip-flop 13, and the clock CLK from the multiplier circuit 12 is inverted and supplied to its clock input terminal C. The Q output of the flip-flop 14 is supplied as the gate signal GATE to the other input of the AND gate 15, and is also supplied as the gate signal GA.
TE is supplied to the set input terminal S of the flip-flop 13 in an inverted state. The output signal OK of flip-flop 3 is set to ``12'' when ``1'' is supplied to the set input terminal S. Therefore, the output signal OK of flip-flop 70 is always set to ``12'' when the output signal OK is at the 11# level. 1
” level gate signal GATE is generated and the output signal is OK.
When is “0 level, the period is one cycle of clock CLK”
A gate signal GATE having a 0'' level is generated.

The AND gate 15 supplies the clock CLK as the input clock CK to the communication interface control circuit 11 when the gate signal GATE is at the "1# level", and outputs the gate signal G to the communication interface control circuit 11.
When ATE is at the "0" level, supply of the input clock CK to the communication interface control circuit 11 is prohibited.

The communication interface control circuit 11 is configured as an LS and an I, and generates a transmission clock TCK by dividing the input clock CK by two, for example.

Next, the operation of this phase adjustment circuit will be explained.

The transmission clock TCK output from the communication interface control circuit 11 is set in the flip-flop 13 at the falling timing of the master clock MCK. In the flip-flop 13, if the phase difference between the transmission clock TCK and the master clock MCK is within half a cycle,
A level output signal OK is output. At this time, the gate signal GATE of "1" level is also output from the flip-flop 14.
is output. Therefore, from the AND gate 15,
A clock CLK twice the master clock MCK is supplied as the input clock CK. As a result, the communication interface control circuit continues to output the transmission clock TCK that is in phase with the mask clock MCI.

On the other hand, as shown in the timing chart of FIG. 2, if the phase difference between the master clock MCK and the transmission clock TCK is more than half a period and these clocks are in opposite phases, the output signal OK of the flip-flop 13 is becomes “0”. In the flip-flop 14, the value of the output signal OK is set to "0" at the falling edge of the clock CLK, and the gate signal GATE becomes "0". Then, the flip-flop 13 is set by the gate signal GATE of "0 level", and the output signal OK is returned to "1". period"
A gate signal GATE of Om is generated. As a result, the input clock CK becomes a signal with one pulse missing from the clock CLK, and this is supplied to the communication interface control circuit 11. As a result, the frequency division timing of the communication interface rBlili circuit 11 is delayed, and the transmission clock TCK is changed with a delay of one cycle of the clock CLK. As a result, the same transmission clock TCK as the master clock MCI is obtained.

In this way, in this embodiment, the phase of the master clock and the transmission clock are matched by controlling the supply of the input clock to the communication interface control circuit ll, so a vCO circuit or a high-frequency clock is not required. . Therefore, a low-cost phase adjustment circuit can be realized with a simple configuration using flip-flops.

FIG. 3 shows a modification of the phase adjustment circuit shown in FIG. 1. In FIG. Here, a clock MCK' twice that of the master clock MCK is used instead of the master clock MCK. The clock MCK' is directly supplied to one input of the AND gate 15 as the clock CLK, and is also supplied to the frequency dividing circuit 2.
The frequency is divided by 2 by 0 and then supplied to the input of the inverter 16. Even in such a configuration, the input clock signal to the communication interface control circuit 11 is controlled in the same way as the circuit shown in FIG.
The supply of light can be controlled and the phase can be adjusted.

[Effects of the Invention] As described above, according to the present invention, phase adjustment can be performed without using a vCO circuit or a high-frequency clock, and a low-cost phase adjustment circuit with a simple configuration is provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a phase adjustment circuit according to an embodiment of the present invention, FIG. 2 is a timing chart illustrating the operation of the phase adjustment path shown in FIG. FIG. 3 is a circuit diagram showing a modification of the phase adjustment circuit shown in the figure. 11... Communication interface control circuit, 12...
Multiplier circuit, 13.14...Flip-flop, 15.
...AND gate, 16. 17...Inverter.

Claims (1)

[Claims] A communication interface control circuit is supplied with an input clock that is a predetermined times the master clock, and divides the input clock by a predetermined frequency to generate a transmission clock synchronized with the master clock; Compare the phase with the master clock,
phase difference detection means that generates a predetermined detection signal when the phase difference is equal to or more than half a period; and in response to the detection signal generated from the phase difference detection means, the input clock is supplied to the communication interface control circuit. clock supply control means for prohibiting the input clock from being transmitted for a period of one clock of the input clock, and adjusting the phases of the master clock and the transmission clock by controlling the supply of the input clock. circuit.