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JPH0316130A - Formation of electrode wiring by using laser flow technique - Google Patents

Formation of electrode wiring by using laser flow technique

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Publication number
JPH0316130A
JPH0316130A JP4104790A JP4104790A JPH0316130A JP H0316130 A JPH0316130 A JP H0316130A JP 4104790 A JP4104790 A JP 4104790A JP 4104790 A JP4104790 A JP 4104790A JP H0316130 A JPH0316130 A JP H0316130A
Authority
JP
Japan
Prior art keywords
film
forming
alloy film
alloy
electrode wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4104790A
Other languages
Japanese (ja)
Inventor
Shoji Madokoro
間所 昭次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP4104790A priority Critical patent/JPH0316130A/en
Publication of JPH0316130A publication Critical patent/JPH0316130A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To restrain an element including an Al wiring layer from being damaged by a method wherein an Al alloy film is formed on a contact hole and on an intermediate insulating film and a light antireflection film is formed on the Al alloy film. CONSTITUTION:Contact holes 16 are made in source and drain diffusion layers 14 by using an RIE method. A high-melting metal such as a Ta-Si film 17 and an Al-Si film 18 as barrier metals are formed one after another on the whole surface of an Si substrate 11 by using a sputtering method. In addition, a W (tungsten) film 19 as an antireflection film is formed on the Al-Si film 18. When the antireflection film 19 is applied to the Al alloy film in this manner, the light absorption efficiency of the Al alloy film is increased. Consequently, a beam size is expanded to be larger than a chip size, and a beam overlap part is set on a grid-line region. Thereby, a uniform beam intensity is obtained on an element formation region on an IC chip, and it is possible to restrain an element from being damaged.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は電極配線の形成方法に係シ、特にレーザフロー
技術を用いるAl配線の形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for forming electrode wiring, and particularly to a method for forming Al wiring using laser flow technology.

(従来の技術) 従来の配線方法を第4図及び第5図を用いて説明する。(Conventional technology) A conventional wiring method will be explained using FIGS. 4 and 5.

第4図(a)及び第4図(b)はレーザフロー技術を用
いた工程図であり、第5図はレーザフロ・−工程におけ
るビームパターン図である。
FIGS. 4(a) and 4(b) are process diagrams using the laser flow technique, and FIG. 5 is a beam pattern diagram in the laser flow process.

筐ず,第4図(.)に示すように, St基板1上の非
能動領域上にフィールド酸化膜2をLOCOS法を用い
て形成する。Si基板1の能動領域上にダート電極3を
形成する。このr−}電極3の両側方のSt基板1の表
面部にソース、ドレイン拡散層4を形成スる。ソース・
ドレイン拡散層が形成されたSi基板1上の全面に中間
絶縁膜としてのBPSG膜5を堆積する。BPSG膜5
にソース・ドレイン拡散層4との接続をとるためのコン
タクトホール6をRIE法を用いて開口する。コンタク
トホール6が形成されたBPSG膜上の全面にStを1
%含有するAA’−St膜7、及び光反射防止膜として
のアモルファスSi膜8をスノ9ツタ法を用いて順次積
層する。コンタクトホール6中にはスパッタ法による膜
7及び8が積層されにく〈膜厚が薄くなる。
First, as shown in FIG. 4(.), a field oxide film 2 is formed on the non-active region of the St substrate 1 using the LOCOS method. A dart electrode 3 is formed on the active region of the Si substrate 1. Source and drain diffusion layers 4 are formed on the surface of the St substrate 1 on both sides of the r-} electrode 3. sauce·
A BPSG film 5 as an intermediate insulating film is deposited over the entire surface of the Si substrate 1 on which the drain diffusion layer is formed. BPSG film 5
Then, a contact hole 6 for connection with the source/drain diffusion layer 4 is opened using the RIE method. 1 of St is applied to the entire surface of the BPSG film in which the contact hole 6 is formed.
% of AA'-St film 7 and an amorphous Si film 8 as a light antireflection film are sequentially laminated using the snow-nine-vine method. It is difficult for the films 7 and 8 formed by sputtering to be stacked in the contact hole 6 (the film thickness becomes thinner).

次に、81基板1に形成されたICチップ上に、波長3
 0 8 nmのXeClエキシマレーデを照射スる。
Next, on the IC chip formed on the 81 substrate 1, wavelength 3
08 nm of XeCl excimerade.

レーザ光照射は第5図に示すような、所定の径のビーム
の走査により行なう。このとき、ビームはビームサイズ
の10〜50%を他のビームに重ねて照射する。
Laser light irradiation is performed by scanning a beam of a predetermined diameter as shown in FIG. At this time, the beam is irradiated with 10 to 50% of the beam size superimposed on other beams.

これにより、第4図(b)に示すようにAl−Si膜7
はメタルフロー効果によりコンタクトホール6を埋め戻
し、コンタクトホール中にAl−Siが充填される。こ
の後、Al−Si膜7を・ゼターン化してコンタクトホ
ール6上にAl配線層を形成する。尚、メタルフローの
際、アモルファスst膜8はAl−Si g7に溶け込
む。
As a result, as shown in FIG. 4(b), the Al-Si film 7
The contact hole 6 is backfilled by the metal flow effect, and the contact hole is filled with Al--Si. Thereafter, the Al--Si film 7 is converted to zetan to form an Al wiring layer over the contact hole 6. Note that during metal flow, the amorphous ST film 8 melts into the Al-Sig 7.

(発明が解決しようとする課題) 以上のようなレーザビーム照射の場合、レーザビームを
重ねる必要があるため、ビームの重なり部分は重ならな
い部分に比べ光エネルギを余分に受けるため、Al−S
i膜7のグレーンサイズが異常に大きく成長してし1つ
たり、更に悪い場合は、AI−Si膜7が蒸発あるいは
剥離してなくなってしまう。このように、ICチップ内
に形成された素子に対するダメージが大きいという課題
がある。
(Problem to be Solved by the Invention) In the case of laser beam irradiation as described above, it is necessary to overlap the laser beams, so the overlapping part of the beams receives more light energy than the non-overlapping part, so Al-S
If the grain size of the i-film 7 grows abnormally large, or worse, the AI-Si film 7 evaporates or peels off. As described above, there is a problem in that the elements formed within the IC chip are seriously damaged.

又、Al−St膜7中にアモスファスSi膜8が溶け込
むため、A4配線8の配線抵抗が増大したり、Siノノ
ユールの増大によりマイグレーションが発生し易くなる
。このため配線寿命が著しく低下するという課題がある
Furthermore, since the amorphous Si film 8 melts into the Al--St film 7, the wiring resistance of the A4 wiring 8 increases, and migration tends to occur due to an increase in Si nanoleaves. Therefore, there is a problem that the life of the wiring is significantly reduced.

本発明の目的は、レーザビームの重なりによるICチッ
プ内の素子のダメージが抑制できる電極配線の形成方法
を提供することにある。
An object of the present invention is to provide a method for forming electrode wiring that can suppress damage to elements within an IC chip due to overlapping laser beams.

本発明の他の目的は、反射防止膜による配線膜の膜質の
低下を防止できる電極配線の形成方法を提供することに
ある。
Another object of the present invention is to provide a method for forming electrode wiring that can prevent deterioration in the quality of the wiring film due to the antireflection film.

(課題を解決するための手段) 半導体ウェハの所定部上に中間絶縁膜を積層した後、該
中間絶縁膜にコンタクトホールを開口する工程と、該コ
ンタクトホール及び上記中間絶縁膜上にht合金膜を被
着する工程と、該Al合金膜上に光反射防止膜を被着す
る工程と、上記半導体ウェハ全面に、ビームサイズがチ
ップサイズより大きく且つビーム重なり部分が上記半導
体ウェハのグリッドライン領域上に〈るように設定した
レーザビームを照射し、上記Al合金膜をメタルフロー
させ、上記Al合金膜により上記コンタクトホールを埋
め戻す工程と、上記光反射防止膜及び上記Al合金膜を
順次選択エッチングして上記コンタクトホール上に、上
面に光反射防止膜を有するAl配線層を形成する工程と
を含むものである。
(Means for Solving the Problems) After laminating an intermediate insulating film on a predetermined portion of a semiconductor wafer, forming a contact hole in the intermediate insulating film, and forming an HT alloy film on the contact hole and the intermediate insulating film. A step of depositing an anti-reflection film on the Al alloy film, a step of depositing an anti-reflection film on the Al alloy film, and a step of depositing an anti-reflection film on the entire surface of the semiconductor wafer, the beam size being larger than the chip size and the beam overlapping portion being on the grid line area of the semiconductor wafer. A step of irradiating the Al alloy film with a laser beam set to metal flow and backfilling the contact hole with the Al alloy film, and sequentially selectively etching the anti-reflection film and the Al alloy film. and forming an Al wiring layer having an anti-reflection film on its upper surface over the contact hole.

(作用) 本発明においては、Al合金膜上に光反射防止膜を被着
するので、Al合金膜の光吸収効率が高くなる。よって
、ビームサイズはチップサイズより犬き〈拡大され、ビ
ーム重なり部分はグリッドライン領域上に設定される。
(Function) In the present invention, since the light antireflection film is deposited on the Al alloy film, the light absorption efficiency of the Al alloy film is increased. Therefore, the beam size is much larger than the chip size, and the beam overlapping portion is set on the grid line area.

従って、ICチノプ上の素子形成面には均一なビーム強
度が得られ、素子ダメージが抑制される。更に、光反射
防止膜とAl合金膜とは反応しないので、Al合金膜の
特性を劣化させることがないと共に、光反射防止膜はA
l配線層の保護膜となる。
Therefore, uniform beam intensity is obtained on the element formation surface on the IC chip, and element damage is suppressed. Furthermore, since the anti-reflection film and the Al alloy film do not react, the properties of the Al alloy film will not deteriorate, and the anti-reflection film will not react with the Al alloy film.
It becomes a protective film for the l wiring layer.

(実施例) 本発明製造方法に係る一実施例を第1図乃至第3図及び
第6図に基づいて説明する。
(Example) An example of the manufacturing method of the present invention will be described based on FIGS. 1 to 3 and FIG. 6.

尚、第1図は製造工程図、第2図はビームノクターン図
及び第3図は光反射防止膜厚と光反射率との特性図を示
す。
Incidentally, FIG. 1 shows a manufacturing process diagram, FIG. 2 shows a beam nocturne diagram, and FIG. 3 shows a characteristic diagram of the thickness of the antireflection film and the light reflectance.

先ず、第1図(.)に示す如く、半導体ウェ・・(Si
基板)1ノの非能動領域上にフィールド酸化膜12をL
OCOS法を用いて形成する。又、St基板1ノの能動
領域所定部にダート電極13を形成する。その後、この
ケ9−ト電極13の両側方のSi基板11表面部にソー
ス・ドレイン拡散層l4を゛形成する。そして、Si基
板11全面に中間絶縁膜のBPSG膜15を堆積した後
、このBPSG膜15を部分的にエッチング除去してソ
ース・ドレイン拡散層14上にコンタクトホール16を
RIE法を用いて開口する。次に、Si基板1ノ全面に
、バリアメタルとしてIOOOX厚のTa−St膜17
等の高融点金属、及び0.6μm厚のfi.l−St膜
18をスi?ツタ法により順次被着形成する。更に、こ
のl’−St膜J8上に光反射防止膜としてのW(タン
グステン)膜19を300X厚形成する。
First, as shown in Figure 1 (.), a semiconductor wafer (Si
Field oxide film 12 is placed on the non-active area of substrate 1.
It is formed using the OCOS method. Further, a dart electrode 13 is formed in a predetermined part of the active region of the St substrate 1. Thereafter, source/drain diffusion layers 14 are formed on the surface of the Si substrate 11 on both sides of the gate electrode 13. After depositing a BPSG film 15 as an intermediate insulating film on the entire surface of the Si substrate 11, this BPSG film 15 is partially etched away and a contact hole 16 is opened on the source/drain diffusion layer 14 using the RIE method. . Next, a Ta-St film 17 with a thickness of IOOOX is applied as a barrier metal over the entire surface of the Si substrate 1.
etc., and 0.6 μm thick fi. The l-St film 18 is Adhesion is formed sequentially using the ivy method. Furthermore, a W (tungsten) film 19 as a light antireflection film is formed to a thickness of 300X on this l'-St film J8.

次に、以上の様な処理がなされたStウェハ31をレー
ザビームにより加熟する。
Next, the St wafer 31 that has been treated as described above is ripened by a laser beam.

第6図は、Stウェハ31をレーザにより加熱する装置
である。Siウェハをチャンバ32に設けられたXYテ
ーブルのステージ33に載置しヒータ34で加熱する。
FIG. 6 shows an apparatus for heating the St wafer 31 with a laser. A Si wafer is placed on a stage 33 of an XY table provided in a chamber 32 and heated with a heater 34 .

温度は、AIの再結晶温度(Al−Si膜18の形成方
法ごとに異なるが150℃〜200℃)以上でSiウェ
ノ・31に形成した素子に影響を与えない程度の温度範
囲とし,300℃程度が良い。チャンバ31内は不活性
ガス雰囲気とするか、真空ポンプによD10Torrに
減圧した状態とする。
The temperature should be within the range of 300°C or above the recrystallization temperature of AI (150°C to 200°C, although it varies depending on the method of forming the Al-Si film 18) and does not affect the elements formed on Si Weno 31. Good condition. The inside of the chamber 31 is made into an inert gas atmosphere or the pressure is reduced to D10 Torr by a vacuum pump.

この様にすることによう、加熱されたW膜19が酸化さ
れるのを防止できる。
By doing so, the heated W film 19 can be prevented from being oxidized.

Siウェハ31を加熱した状態でXeClレーザ35の
レーザビームをSiウェハ3l表面に照射する。
While the Si wafer 31 is heated, the surface of the Si wafer 3l is irradiated with a laser beam from the XeCl laser 35.

レーザビームは周波数1 0 0 Hz 、/?ルス幅
数10mBeC ,波長3 0 8 nmの発振をする
。レーザビームは鏡36で反射され、光学系37を通し
てSiウェハ31表面に照射する。光学系37ぱ、レン
ズ38と、各ICチップ形状と相似形の開口を有するア
パーチャ39を有し、レーザビームを後に述べるAxB
の大キさでビームエネルギ2,5〜3.OJ/crn2
に調整する。又、発振するレーザビーム強度は鏡36を
わずか通過した光をコントローラ40で検知し、XeC
lレーザ35を制御することにより調整する。レーザ光
がICチップ上に正しく照射されるかどうかは、アーク
ランf41から照射した光がわずかに光を反射する透明
板42により分割された光を光ダイオード43及びカメ
ラ44を用いて検知され、モニタ45に写し出される。
The laser beam has a frequency of 100 Hz, /? It oscillates with a pulse width of several 10 mBeC and a wavelength of 308 nm. The laser beam is reflected by a mirror 36 and passes through an optical system 37 to irradiate the surface of the Si wafer 31. The optical system 37 has a lens 38 and an aperture 39 having an opening similar to the shape of each IC chip.
The beam energy is 2.5~3. OJ/crn2
Adjust to. In addition, the intensity of the oscillated laser beam is determined by detecting the light that has slightly passed through the mirror 36 with the controller 40, and
Adjustment is made by controlling the l laser 35. To determine whether the laser beam is correctly irradiated onto the IC chip, the light emitted from the arclan F41 is split by a transparent plate 42 that slightly reflects the light, and the light is detected using a photodiode 43 and a camera 44, and then monitored. Photographed in 45.

又、この信号はXYステージコントローラ46に伝えら
れ、このコントロール信号によりXYステージ33を必
要な位置に移動させる。又、これら検知された信号はホ
ストコン♂ユータ47にも入力され、前記各コントロー
ラを制御するとともに、光学系コントローラ48も制御
し、光学系37を調節する。
This signal is also transmitted to the XY stage controller 46, and the XY stage 33 is moved to a required position by this control signal. These detected signals are also input to the host computer 47, which controls each of the controllers mentioned above, and also controls the optical system controller 48 to adjust the optical system 37.

Sifyエハ3ノの1つのICチップをレーザビームで
加熱する場合、第2図に示す様にビームサイズAXBと
ICチップのサイズaXbとの間で次式の関係を満足す
る様にする。
When heating one IC chip on three Sify wafers with a laser beam, the following relationship is satisfied between the beam size AXB and the IC chip size aXb, as shown in FIG.

A = a + C X ( 0.6〜0.8 ) X
 :2曙B=b+Cx(0.6〜0.8)X2+l!l
I(但し、Cはグリッドライン幅) このときの隣接して照射されるビーム同志のビーム重な
り寸法はCX(0.2〜08)IImである。
A = a + C X (0.6~0.8) X
:2 Akebono B=b+Cx(0.6~0.8)X2+l! l
I (where C is the grid line width) The beam overlap dimension of adjacent beams irradiated at this time is CX (0.2 to 08) IIm.

Stチッグが十分小さい場合又は、レーザ光が十分大き
い出力が得られる場合は、隣接する2つのICチップず
つ又は4つのICチップずつ加熱処理する。n行m列の
ICチップを加熱するときのビームサイズAn X B
mは、 An=na + (n−1 )C+CX(0.6〜0.
8)X2mBm=mb +( n−1 ) C+CX 
(0.6〜0.8)X2mとする。
When the Stig is sufficiently small or when the laser beam has a sufficiently large output, the heat treatment is performed on two adjacent IC chips or four IC chips at a time. Beam size An X B when heating an IC chip in n rows and m columns
m is An=na+(n-1)C+CX(0.6~0.
8)X2mBm=mb+(n-1)C+CX
(0.6-0.8)×2m.

このときに用いる光学系37のアノe−チャ39の開口
はn行m列のチッグ形状と相似形にする。
The aperture of the annocha 39 of the optical system 37 used at this time is made similar to the Chigg shape of n rows and m columns.

これにより、第1図(b)に示す如く、Al−St膜1
8のメタルフロー効果によりAl−Si膜18がコンタ
クトホール16を埋め戻す。その後、ホトリソ技術を用
いて、W膜19をCF4ガスによるRIE法で所定形状
にパターニングした後、Aj!−Si 膜18及びTa
−St膜17をB(J 3がスによるRIE法により順
次パターニングし、Al配線層20を完成する。
As a result, as shown in FIG. 1(b), the Al-St film 1
The Al--Si film 18 backfills the contact hole 16 due to the metal flow effect of 8. Thereafter, the W film 19 is patterned into a predetermined shape by RIE using CF4 gas using photolithography, and then Aj! -Si film 18 and Ta
The -St film 17 is sequentially patterned by RIE using B (J3) to complete the Al wiring layer 20.

ところで、光反射防止膜としてのW膜19は、例えば波
長3 0 8 nmの紫外光に対して光吸収係数が9X
10m  と極めて大きく、且つ第3図に示すように、
W/Aj −S i/S 10 2/S i構造におい
ては300又厚程度のW膜19でも十分に光反射率が低
減される。従って、At−Si膜18の光吸収効率が高
くなり、ビームサイズの拡大が可能となる。又、RBS
解析によれば、基板温度が300℃ではW膜19とA7
−Si膜18とは反応し難く、而も照射ビームの波長が
短いため、光透過深さは数10X程度にしかならないの
で、W膜19とAl−St膜18との反応は最小限に抑
制される。更に、バリアメタルのTa−S i膜17上
ではAIの濡れ性が良好なので、小さなビームエネルギ
でもAlフローが可能となり、Ta−Si膜17下の素
子ダメージが抑制される。
By the way, the W film 19 as a light antireflection film has a light absorption coefficient of 9X for ultraviolet light with a wavelength of 308 nm, for example.
It is extremely large at 10m, and as shown in Figure 3,
In the W/Aj-S i/S 10 2/S i structure, the light reflectance can be sufficiently reduced even with the W film 19 having a thickness of about 300 mm. Therefore, the light absorption efficiency of the At-Si film 18 is increased, and the beam size can be expanded. Also, RBS
According to the analysis, when the substrate temperature is 300°C, W film 19 and A7
- It is difficult to react with the Si film 18, and since the wavelength of the irradiation beam is short, the light transmission depth is only about several tens of times, so the reaction between the W film 19 and the Al-St film 18 is suppressed to a minimum. be done. Furthermore, since the wettability of AI is good on the barrier metal Ta-Si film 17, Al flow is possible even with a small beam energy, and element damage under the Ta-Si film 17 is suppressed.

尚、光反射防止膜はW膜19に限定されるものではなく
、Alと反応し難いTiW膜、TiN膜、Ti膜、Cu
膜又はMo膜でも良い。
Note that the anti-reflection film is not limited to the W film 19, and may include TiW film, TiN film, Ti film, Cu film, which does not easily react with Al.
It may be a film or a Mo film.

(発明の効果) 以上説明したように本発明では、Al合金膜上に光反射
防止膜を形成するので、Al合金膜の光吸収率が向上し
、ビームサイズをチップサイズより大きくすることが可
能となる。Siウェハは更にAlの再結晶温度以上に加
熱されているので、比較的小さなエネルギでもAIフロ
ーが可能となる。このとき、隣接して照射されるレーデ
ビームのMなb部分はグリッドライン領域上に設定する
ので、各ICチップ上の素子には均一な強度のレーザビ
ームが照射される。従って、Al配線層を含む素子のダ
メ一ソが抑制でき、ICの歩留が大幅に向上できる。
(Effects of the Invention) As explained above, in the present invention, an anti-reflection film is formed on the Al alloy film, so the light absorption rate of the Al alloy film is improved and the beam size can be made larger than the chip size. becomes. Since the Si wafer is further heated above the recrystallization temperature of Al, AI flow is possible even with relatively small energy. At this time, since the Mb portions of the adjacent Rade beams are set on the grid line area, the elements on each IC chip are irradiated with a laser beam of uniform intensity. Therefore, damage to elements including the Al wiring layer can be suppressed, and the yield of ICs can be greatly improved.

又、光反射防止膜とAl合金膜とは反応しないので、A
l合金膜の特性劣化が防止できる。更に、光反射防止膜
が保護膜として作用するので、Al合金膜のヒロックの
発生が防止できると共に、マイグレーション寿命が改善
できる等の特有の効果がある。
In addition, since the antireflection film and the Al alloy film do not react, A
1. Deterioration of properties of the alloy film can be prevented. Furthermore, since the anti-reflection film acts as a protective film, it has unique effects such as preventing the occurrence of hillocks in the Al alloy film and improving migration life.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)及び第1図(blは、本発明方法のレーザ
ビームによるメタルフローエ程を説明するための図で、
第2図は、本発明方法のレーザビーム照射パターンの図
で、第3図は、光反射防止膜の厚さと光反射率の関係を
示す特性図で、第4図(a)及び第4図(b)は、従来
方法のレーザビームによるメタルフローエ程を説明する
ための図で、第5図は、従来方法のレーザビームノソタ
ーンの図で,第6図は、ウェハをレーザビームで加熱す
る装置の図である。 11・・・Si基板、12・・・フィールド酸化膜、J
3・・・ダート電極,14・・・ソース・ドレイン拡散
層、15・・・BPSGg、J e;・・・コンタクト
ホール、17・・・Ta−Si膜、J 8 ・Al?−
St膜,19−W膜。 0 20    40    60 印 100 光反射防i−膜のR1厚(nm) 忙反身干p左止斤曝一児反夕博右手+生図第 3 図 従水方二P.の工禮図 第4図 ヒ一一ノでシン図 第5図
FIG. 1(a) and FIG. 1(bl) are diagrams for explaining the metal flow process using a laser beam in the method of the present invention,
Fig. 2 is a diagram of the laser beam irradiation pattern of the method of the present invention, Fig. 3 is a characteristic diagram showing the relationship between the thickness of the antireflection film and the light reflectance, and Figs. (b) is a diagram for explaining the metal flow process using a laser beam in the conventional method, FIG. 5 is a diagram of the laser beam nosoturn in the conventional method, and FIG. FIG. 2 is a diagram of the device. 11...Si substrate, 12...field oxide film, J
3... Dirt electrode, 14... Source/drain diffusion layer, 15... BPSGg, Je;... Contact hole, 17... Ta-Si film, J8/Al? −
St film, 19-W film. 0 20 40 60 Mark 100 R1 thickness (nm) of anti-reflection film (nm) Fig. 4 of the engineering drawings of Hiichiichino and Shin drawings of Fig. 5.

Claims (1)

【特許請求の範囲】 1)半導体ウェハ上に中間絶縁膜を形成する工程と、 前記中間絶縁膜にコンタクトホールを開口する工程と、 前記コンタクトホール及び前記中間絶縁膜上にAl合金
膜を形成する工程と、 前記Al合金膜上に光反射防止膜を形成する工程と、 前記光反射防止膜を形成した半導体ウェハ表面に、ビー
ムサイズがチップサイズより大きくかつ、隣接するショ
ットとのビーム重なり部分が該半導体ウェハのグリッド
ライン上になるように設定したレーザビームを照射し、
前記Al合金膜をメタルフローさせ該Al合金膜により
前記コンタクトホールを埋める工程と、 前記光反射防止膜が形成されたAl合金膜をパターニン
グして配線層を形成する工程とを有する電極配線の形成
方法。 2)前記光反射防止膜はAlと反応しにくい高融点金属
膜から成り、 前記パターニングは該高融点金属膜が前記Al合金膜上
にパターニング後も残存するように行なう請求項1記載
の電極配線の形成方法。 3)前記Al合金膜直下には高融点金属膜が形成されて
いる請求項1記載の電極配線の形成方法。 4)前記レーザビームの照射はヒータで前記半導体ウェ
ハをAlの再結晶温度以上に加熱した状態で行なう請求
項1記載の電極配線の形成方法。 5)前記レーザビームは紫外光領域の波長である請求項
1記載の電極配線の形成方法。
[Claims] 1) forming an intermediate insulating film on a semiconductor wafer; forming a contact hole in the intermediate insulating film; and forming an Al alloy film on the contact hole and the intermediate insulating film. a step of forming an anti-reflection film on the Al alloy film; and a step of forming an anti-reflection film on the surface of the semiconductor wafer on which the anti-reflection film is formed, the beam size being larger than the chip size and a beam overlapping portion with an adjacent shot. Irradiate a laser beam set to be on the grid line of the semiconductor wafer,
Forming an electrode wiring comprising: metal-flowing the Al alloy film to fill the contact hole with the Al alloy film; and patterning the Al alloy film on which the anti-reflection film is formed to form a wiring layer. Method. 2) The electrode wiring according to claim 1, wherein the light antireflection film is made of a high melting point metal film that does not easily react with Al, and the patterning is performed so that the high melting point metal film remains on the Al alloy film even after patterning. How to form. 3) The method for forming an electrode wiring according to claim 1, wherein a high melting point metal film is formed directly under the Al alloy film. 4) The method of forming electrode wiring according to claim 1, wherein the laser beam irradiation is performed with the semiconductor wafer heated to a temperature higher than the recrystallization temperature of Al using a heater. 5) The method for forming electrode wiring according to claim 1, wherein the laser beam has a wavelength in the ultraviolet region.
JP4104790A 1989-03-31 1990-02-23 Formation of electrode wiring by using laser flow technique Pending JPH0316130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4104790A JPH0316130A (en) 1989-03-31 1990-02-23 Formation of electrode wiring by using laser flow technique

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP7802189 1989-03-31
JP1-78021 1989-03-31
JP4104790A JPH0316130A (en) 1989-03-31 1990-02-23 Formation of electrode wiring by using laser flow technique

Publications (1)

Publication Number Publication Date
JPH0316130A true JPH0316130A (en) 1991-01-24

Family

ID=26380570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4104790A Pending JPH0316130A (en) 1989-03-31 1990-02-23 Formation of electrode wiring by using laser flow technique

Country Status (1)

Country Link
JP (1) JPH0316130A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355020A (en) * 1991-07-08 1994-10-11 Samsung Electronics Co., Ltd. Semiconductor device having a multi-layer metal contact
JPH08229693A (en) * 1995-02-28 1996-09-10 Toshiba Corp Laser beam irradiating equipment
JPH10135212A (en) * 1996-10-30 1998-05-22 Sgs Thomson Microelectron Inc Low temp. aluminum reflow for multilayer metallization
JP2005005461A (en) * 2003-06-11 2005-01-06 Tokyo Electron Ltd Semiconductor manufacturing device and thermal treatment method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355020A (en) * 1991-07-08 1994-10-11 Samsung Electronics Co., Ltd. Semiconductor device having a multi-layer metal contact
JPH08229693A (en) * 1995-02-28 1996-09-10 Toshiba Corp Laser beam irradiating equipment
JPH10135212A (en) * 1996-10-30 1998-05-22 Sgs Thomson Microelectron Inc Low temp. aluminum reflow for multilayer metallization
JP2005005461A (en) * 2003-06-11 2005-01-06 Tokyo Electron Ltd Semiconductor manufacturing device and thermal treatment method

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