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JPH03160513A - Reference voltage generating circuit made into semiconductor integrated circuit - Google Patents

Reference voltage generating circuit made into semiconductor integrated circuit

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Publication number
JPH03160513A
JPH03160513A JP30034189A JP30034189A JPH03160513A JP H03160513 A JPH03160513 A JP H03160513A JP 30034189 A JP30034189 A JP 30034189A JP 30034189 A JP30034189 A JP 30034189A JP H03160513 A JPH03160513 A JP H03160513A
Authority
JP
Japan
Prior art keywords
current
voltage
emitter
temperature coefficient
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30034189A
Other languages
Japanese (ja)
Inventor
Takashi Ogata
孝 尾形
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP30034189A priority Critical patent/JPH03160513A/en
Publication of JPH03160513A publication Critical patent/JPH03160513A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To suppress the absolute value dispersion of a reference voltage to be small by subtracting the current of a current generating circuit where positive temperature coefficient is large from the current of a current generating circuit where positive temperature coefficient is small and impressing a subtracted result to a reference resistor. CONSTITUTION:When resistors R2 and R1 for current set are set to be R1>R2 so as to obtain I2>I1, the temperature change of constant current sources Io2 and Io1 can obtain a characteristic with the large I1 and the small I2 for an absolute value. For the I2, the same current as the I2 is outputted from the collector of a transistor Q6 by a current mirror circuit composed of transistors Q5 and Q6, and the I2 is connected serially to the collector output I1 of the transistor Q5. Then, the current of I3=I2-I1 is outputted. In such a case, the generated current I3 with a negative temperature coefficient is added and synthesized with the current I0 of a constant current source equipped with a voltage JBE difference between the base and emitter of transistors Qo1 and Qo and the positive temperature coefficient to be set by a resistor Ro. Then, the result is impressed to a reference resistor Rref. Thus, the temperature coefficient of the reference voltage can be set to 0.

Description

【発明の詳細な説明】 〔産業上の利用分野] この発明は、半導体集積回路化C以下IC化と略す)電
子回路のなかで、温度変動、供給電源電変動等に対して
、安定で変動の少い、基準直流電圧発生回路の回路構或
に関するものであり、カメラ用ストロボ制御回路、制御
機器用回路等広く、応用できる 〔従来の技丙〕 第3図は、従来の基準電圧発生回路の回路図である。図
に訃いて(Dref)は基準ダイオード、(Ion)は
電流源、(Qo) 、(Q,or )はパイポーラ形の
トランジスタ、(Ro)は抵抗、(Rref)は基準抵
抗であるうトランジスタ(Q,o+),(Qn)は、ベ
ース共通接続されてかり、トランジスタ(Qot)のベ
ースーエレクタ間は短絡され、ダイオード構或となり、
電流源(Ion)と直列接続され、供給電源Vccと接
続される。又トヲンジヌタ(Qo.>のエミッタはGN
 O(アース)ラインと接続され、トランジスタ(Q,
o)のエミッタは、基準電流Iref設定用の抵抗(R
o)と直列接続されGND(アース)に接続される。
[Detailed Description of the Invention] [Industrial Application Field] This invention is intended for use in electronic circuits (semiconductor integrated circuits (hereinafter referred to as ICs)) that are stable and stable against temperature fluctuations, power supply fluctuations, etc. This relates to the circuit structure of a reference DC voltage generation circuit with a small amount of noise, and can be widely applied to camera strobe control circuits, control equipment circuits, etc. [Conventional technology] Figure 3 shows a conventional reference voltage generation circuit. FIG. In the figure, (Dref) is a reference diode, (Ion) is a current source, (Qo), (Q,or) are bipolar transistors, (Ro) is a resistor, and (Rref) is a reference resistor. The bases of Q, o+) and (Qn) are commonly connected, and the base and erector of the transistor (Qot) are short-circuited to form a diode structure.
It is connected in series with a current source (Ion) and connected to a power supply Vcc. Also, the emitter of Towonjinuta (Qo.> is GN)
It is connected to the O (earth) line, and the transistors (Q,
The emitter of o) is connected to a resistor (R
o) in series and connected to GND (earth).

又トランジスタ(Q,o)のコレクタは、基準抵抗(R
.ref’)、基準ダイオード(Dref’)と直列接
続され、供給電源VCCに接続される、 次に動作について説明する 図に釦いてトランジスタ(Qo I) 、(Q.o )
のそれぞれの接合面積SフhSO、及びエミッタ電流I
o1%rref’は各々異なり、特に接合面積は、SO
>SoIに設定されている,従ってトランジスタ(Q.
o+ )、(Q.O)のそれぞれのベース−エミッタ間
電圧J HE01J BEDは、各々.T R E0 
1 =k′r/l nj史−−(1)Q    So1
、Is J RF,。=kT/ In ”’         
 ・=(2)9   Sυ工8 で表わされる。ここで、T:絶対温度、k:ポIレツマ
ン定数、q:クーワン定数、工8:飽和電流である。ト
ランジスタ(Qo), (Qo+)の各ベースと、GN
D間電圧は同電位であるため JRgo+ =Jsco +RO ・Iref’   
     ・la)従って Irer=”ε111−J−BEIJ = 1 .kT
/(, (ul  . 9’J,Kg,Ro    R
o  Q  Snl−Is  Iref’=恥。kT/
 1rISo/S.. , Io 17.,,,,  
  ,,・(4)q で表わされる。ここで、Io + >> Irefであ
れば・・・(6) となり、基準電流Iref’は、JBgo+とJREの
差電圧(.;JHpo)  を、抵抗(Ro)で除算し
た値で、決定され、基準電流Irefの温度係数は、6
(式)より正の値をもつことがわかるう 第3図では、上記のT一比例基準1! i5fE Ir
efを、基準抵抗(Ref’)、基準ダイオード(Dr
ef)に流しこむこトニヨり、供給[fiVccと、基
準抵抗(Rref)の低電位点C図に示すX点)間に、
発生する電圧Jrefは .TB(Dref’)=kT/ ln−’−E!−!−
       −(7)q    Sref−Ia Jref = Iref −R ref’ +JBB(
Dref’ )        =48)で、表わされ
る。ここで、Srefは基準ダイオード(Drew)の
接合面積を、Isは飽和電流を表わす。
Also, the collector of the transistor (Q, o) is connected to the reference resistance (R
.. ref'), connected in series with the reference diode (Dref'), and connected to the supply power VCC. Next, click on the diagram to explain the operation of the transistors (Qo I), (Q.o).
The respective junction areas SfhSO and emitter current I
o1%rref' is different, especially the bonding area is SO
>SoI, therefore the transistor (Q.
o+) and (Q.O), the base-emitter voltage J HE01J BED is . T R E0
1 = k'r/l nj history -- (1) Q So1
, Is J RF,. =kT/In”'
It is expressed as ・=(2)9 SυWork8. Here, T: absolute temperature, k: PoI Retzman's constant, q: Cowan's constant, and 8: saturation current. The bases of transistors (Qo) and (Qo+) and GN
Since the voltage between D is the same potential, JRgo+ = Jsco +RO ・Iref'
・la) Therefore, Irer=”ε111-J-BEIJ=1.kT
/(, (ul. 9'J, Kg, Ro R
o Q Snl-Is Iref' = Shame. kT/
1rISo/S. .. , Io 17. ,,,,
,,・(4) It is expressed as q. Here, if Io + >> Iref...(6) The reference current Iref' is determined by dividing the difference voltage (.; JHpo) between JBgo+ and JRE by the resistance (Ro). , the temperature coefficient of the reference current Iref is 6
(Formula) shows that it has a positive value. In Figure 3, the above T-proportional criterion 1! i5fE Ir
ef, reference resistance (Ref'), reference diode (Dr
Between the supply [fiVcc and the low potential point of the reference resistor (Rref), point X shown in the diagram],
The generated voltage Jref is . TB(Dref')=kT/ln-'-E! -! −
-(7)q Sref-Ia Jref = Iref -R ref' +JBB(
Dref') = 48). Here, Sref represents the junction area of the reference diode (Drew), and Is represents the saturation current.

ここで、vHEは通常負の温度係数を、又基準抵抗(R
.ref)は通常正の温度係数を示す。
Here, vHE usually has a negative temperature coefficient and a reference resistance (R
.. ref) usually exhibits a positive temperature coefficient.

従って、(8)式において、第1項(Iref’Rre
f)は、(6)式より基準電流Irefの温度係数が正
,であることより、正の温度係数を、又第2項は負の温
度係数をもつことより、加算された基準電圧hefは温
度補償され、基準抵抗(Rref’) 、及びXrd 
%Srefの適切な設定により温度係数がほとんどない
電圧となる。
Therefore, in equation (8), the first term (Iref'Rre
Since the temperature coefficient of the reference current Iref is positive from equation (6), f) has a positive temperature coefficient, and since the second term has a negative temperature coefficient, the added reference voltage hef is Temperature compensated, reference resistance (Rref'), and Xrd
Appropriate setting of %Sref results in a voltage with almost no temperature coefficient.

[発明が解決しようとする課題] 従来の基準電圧発生回路は以上のように構威されている
ので,(8)式にかける(Iref’−Rref)項の
正の温度係数と、基準ダイオードの負の温度係数により
、温度補償された、安定な基準電圧が得られるが、(8
)式より明らかなように、電圧Jref’の値に、基準
ダイオードの絶対値が影響される構或となっている,I
Cの場合、通常基準ダイオードのベース・エミッタ間電
圧JRg(Dref’)は、不純物拡散濃度のパラツキ
等により,量産時通常±5〜±10q5の値のパヲツキ
がみられるため、基準電圧のバラツキに直接影響し、高
精度な基準電圧回路としては、改善する必娑があった,
又基準ダイオードと、(8)式の(Irer−Rref
)項、及びトランジスタ(Qo)のコレクターエミッタ
間が直列接続されているため、第3図の基準電圧発生回
路を、動作させるために必要な供給電圧Vccの最少電
圧は、ダイオード電圧(;0.6V)と(Rref’I
ref) : 0.5 〜0.6 V 11cpH(Q
o):0.2 Vの和で約1.3 〜1.4 V以上を
必要とするという欠点があった・ この発明は、上記のような問題点,欠点を解消するため
になされたもので、基準電圧の絶対値パラツキを小lも
えるとともに基準電圧発生回路の、最少供給電圧を小さ
く(lO以下)することができる基準電圧発生回路を得
ることを目的とする。
[Problems to be Solved by the Invention] Since the conventional reference voltage generation circuit is configured as described above, the positive temperature coefficient of the term (Iref'-Rref) multiplied by equation (8) and the reference diode The negative temperature coefficient provides a stable, temperature-compensated reference voltage;
), the absolute value of the reference diode is influenced by the value of the voltage Jref', I
In the case of C, the base-emitter voltage JRg (Dref') of the reference diode usually has a value of ±5 to ±10q5 during mass production due to variations in impurity diffusion concentration, etc. There was a need for improvement as a high-precision reference voltage circuit.
In addition, the reference diode and (Irer-Rref
) term and the collector-emitter of the transistor (Qo) are connected in series, so the minimum voltage of the supply voltage Vcc required to operate the reference voltage generation circuit of FIG. 3 is equal to the diode voltage (;0. 6V) and (Rref'I
ref): 0.5 ~ 0.6 V 11cpH (Q
o): There was a drawback that the sum of 0.2 V required approximately 1.3 to 1.4 V or more. This invention was made to solve the above problems and drawbacks. It is an object of the present invention to provide a reference voltage generation circuit which can reduce variations in the absolute value of the reference voltage and reduce the minimum supply voltage of the reference voltage generation circuit (to less than 1O).

〔課題を解決するための手段〕[Means to solve the problem]

この発明にかける基準電圧発生回路は、基準ダイオード
を使用せず、基準抵抗と、基準電流の積だけで、決定さ
れる構或とし基準電流の設定を、従来のJREO差( 
iJB12 )と抵抗で決定される電流に加えて、更に
追加構戒回路でJBEの差(4JBε)と抵抗で決定さ
れる電流発生回路を2回路構或し、上記電流発生回路の
差電流を、重畳させることにより温度補償を行う, 〔作用〕 この発明では、従来の回路でのJago差と抵抗で決定
される電流が(6)式より正の温度係数をもつこと金利
用していると同時にかつ、正の温度係数値は、構或され
るトランジスタの接合[fi積又ぱエミッタ電流に依存
して決定される、ベース−エミッタ間電圧の差の大きさ
により、変化することを利用し、正の温度係数の小さい
電流発生回路の電流より、正の温度係数の大きい電流発
生回路の電流を、減算することにより、上記減算電流の
温度係数を負にする。更に、上記Ioと、上記減算電流
を加算した電流を、基準電流として、基準抵抗に印加す
ることにより温度補償され、かつダイオード金使用しな
いことにより基準電圧の絶対値バヲツキの少い、低動作
電源電圧の基準電圧発生回路金得ることができる。
The reference voltage generation circuit according to the present invention does not use a reference diode and is determined only by the product of the reference resistance and the reference current, and the reference current setting is determined by the conventional JREO difference (
In addition to the current determined by iJB12) and the resistor, an additional circuit is configured with two current generating circuits determined by the difference in JBE (4JBε) and the resistor, and the difference current between the above current generating circuits is [Operation] This invention makes use of the fact that the current determined by the Jago difference and resistance in the conventional circuit has a positive temperature coefficient according to equation (6). Moreover, by utilizing the fact that the positive temperature coefficient value changes depending on the magnitude of the difference in base-emitter voltage, which is determined depending on the junction [fi product or emitter current] of the transistor to be constructed, By subtracting the current of the current generation circuit with a large positive temperature coefficient from the current of the current generation circuit with a small positive temperature coefficient, the temperature coefficient of the subtracted current is made negative. Furthermore, by applying the current obtained by adding the above Io and the above subtracted current to the reference resistor as a reference current, temperature compensation is achieved, and by not using diode gold, a low operating power supply with less fluctuation in the absolute value of the reference voltage is achieved. Voltage reference voltage generation circuit gold can be obtained.

〔実施例] 以下、この発明の一実施例を図によって説明する。第1
図は半導体集積回路化基準電圧発生回路の回路図である
。図に釦いて、(Ion) + (Qo) .(Qo+
 )+(Ro ), (R ref’ )は第3図の従
来例に示したもの同等であるので説明を省略する。(I
o2)は電流源、(Qo2 ) ,(Q3)〜(Q +
n )はトランジスタ、.R1)〜(R3)は抵抗であ
る。電流源(Io+)、共通ベース接続されたトランジ
スタ(QOI) 、(Qo) 及U }ランジスタ(Q
υ)のエミッタに接続された抵抗(RO)で構或される
回路は第3図に示した従来回路と同様である。第1図の
回路では、この他に、電流i1JA (IO2)と、ダ
イオード接続されたトランジスタ(Q,o2)、}ラン
ジスタ(Q.o2)と共通ベース接続されたトランジス
タ(q.*), (QIO)を有しトランジスタ(Q9
) . (Q.Hl)の各々のエミッタとGND間に、
電流設定用の抵抗(Rl).(R2),を接続し、トラ
ンジスタ(qo2)のベースーエミッタ間電圧JBEO
2と、トランジスタ(Q9)及び(q+o)のベース−
エミッタ間電圧JBE9、JBEIO、の差により決定
される定電流工+ , I2 k生或する,トランジス
タ(Q10 )のコレクタは、ダイオード接続されたp
Dpのトランジスタ(Q5)のコレクターベースと接続
される。又pppのトランジスタ(qs) , (Qa
)は、共通ベース、及び共通エミッタ接続された電流ミ
ラー回路を構或する。電流ミラー回路出力となるトラン
ジス/ (Q!)のコレクタは、定電流源(Iol)の
出力、即ち、npnのトランジスタ(Q9)のコレクタ
と直列接続され、その接続点(第1図に示すY点)より
、抵抗(R3)を経由して共通ベース,共通エミッタ接
続されたトランジスタ(Q?) , (Q8)で構戊さ
れる電流ミラー回路に接続される。電流ミラー回路出力
となるトランジスタ(Q8)のコレクタは定電流源(I
o1)の出力、トランジスタ(QO)のコレクタと共通
接続され基準抵抗(R〜0の一方端に接続される。基準
抵抗(Rref)の他方端は、供給電源Vccに接続さ
れる。
[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a circuit diagram of a semiconductor integrated circuit reference voltage generation circuit. Click on the diagram and select (Ion) + (Qo). (Qo+
)+(Ro) and (Rref') are the same as those shown in the conventional example of FIG. 3, so their explanation will be omitted. (I
o2) is a current source, (Qo2), (Q3) ~ (Q +
n) is a transistor, . R1) to (R3) are resistors. Current source (Io+), common base connected transistor (QOI), (Qo) and U} transistor (Q
The circuit consisting of a resistor (RO) connected to the emitter of υ) is similar to the conventional circuit shown in FIG. In the circuit of FIG. 1, in addition to this, the current i1JA (IO2), the diode-connected transistor (Q, o2), the transistor (q. QIO) and a transistor (Q9
). (Q.Hl) between each emitter and GND,
Resistor for current setting (Rl). (R2), and the base-emitter voltage JBEO of the transistor (qo2)
2 and the base of transistors (Q9) and (q+o) -
The collector of the transistor (Q10) is a diode-connected p
Connected to the collector base of the Dp transistor (Q5). Also, ppp transistors (qs), (Qa
) constitutes a common base and common emitter connected current mirror circuit. The collector of the transistor (Q!), which is the current mirror circuit output, is connected in series with the output of the constant current source (Iol), that is, the collector of the npn transistor (Q9), and the connection point (Y shown in Figure 1) is connected in series with the collector of the npn transistor (Q9). point) is connected via a resistor (R3) to a current mirror circuit constituted by transistors (Q?) and (Q8) whose common base and common emitter are connected. The collector of the transistor (Q8) that serves as the current mirror circuit output is connected to a constant current source (I
o1) is commonly connected to the collector of the transistor (QO) and connected to one end of the reference resistor (R~0).The other end of the reference resistor (Rref) is connected to the supply power Vcc.

次に動作について説明する。Next, the operation will be explained.

第1図において、第3図の従来例に相当する定電流源(
Iol)の電流は、第3図の従来例の基準電流工ref
’と同様の動作行うことより、絶対値及び温度係数は前
記(5)式,(6)式と同様にで表わされ、電流Ioの
絶対値はトランジスタ(QOI ), (Q,o)のJ
REの差及び抵抗(Ro)で決定され、Ioの温度係数
としては正であり、かつ接合面積の比(SO/So. 
)に依存して決定されることがわかる。
In Fig. 1, a constant current source (
The current of Iol) is the reference current of the conventional example shown in Fig. 3.
By performing the same operation as ', the absolute value and temperature coefficient are expressed as in equations (5) and (6) above, and the absolute value of the current Io is the transistor (QOI), (Q, o). J
It is determined by the difference in RE and resistance (Ro), the temperature coefficient of Io is positive, and the ratio of junction area (SO/So.
).

一般ニ、トランジスタのベース−エミッタ間電圧JRE
.及び、ベース−エミッタ間電圧差の温度変化を、定性
的に示すとそれぞれ第4図、第5図のようになる。J.
εの絶対値が大きいほど、JBEの負温度係数は小さく
なり、JBEo差(ノJBx) ’Ell圧が大きいほ
ど、aJHEの正の温度係数は、大きくなる。
Generally speaking, the base-emitter voltage JRE of a transistor
.. The temperature change of the base-emitter voltage difference is qualitatively shown in FIGS. 4 and 5, respectively. J.
The larger the absolute value of ε, the smaller the negative temperature coefficient of JBE, and the larger the JBEo difference (JBx) 'Ell pressure, the larger the positive temperature coefficient of aJHE.

この発明にかいては、J8εの差電圧と、抵抗により決
筐る定電流源回路につき、接合面積の比が異なる少くと
も3種類(3組)以上の回路を用意し各定電流源回路の
正の温度係数値を、3fii以上設定する。これにより
正の温度係数の小さい定電流源回路より、正の温度係数
の大きい定電流源回路電流を減算させることにより、負
の温度係数をもつ、定電流源を生戊させることを特徴と
している,第1図において、トランジスタ(Qo+),
 (Q.o) , (Qo2) ,(QQ), (Q+
n)の各ベースーエミッタの接合面積を、8111 .
 80 , 802 , Sol , S1flとする
とトランジスタ(Q,* ) , (Qca)で構或さ
れる定電流源(Io+ )、及びトランジスタ(q+n
) , (Q,02)で構或される定電流源(Io2)
の電流値は各々 ?   kT    S” 工2串4■/q1rl一チ古,〜 で表わされる。
In this invention, at least three types (three sets) of circuits with different junction area ratios are prepared for the constant current source circuit determined by the J8ε voltage difference and the resistance, and each constant current source circuit is Set a positive temperature coefficient value of 3fii or more. As a result, by subtracting the constant current source circuit current with a large positive temperature coefficient from the constant current source circuit with a small positive temperature coefficient, a constant current source with a negative temperature coefficient is generated. , In FIG. 1, the transistor (Qo+),
(Q.o) , (Qo2) , (QQ), (Q+
The base-emitter junction area of each base-emitter of 8111 .
80, 802, Sol, S1fl, a constant current source (Io+) composed of transistors (Q, *), (Qca), and a transistor (q+n
) , (Q,02) constant current source (Io2)
What is the current value of each? It is expressed as kT S" 工2 skewer 4■/q1rl ichi ko, ~.

・・・(1l) ここで、各接合面積を SIO >89>So 又  8゜゜/8。2〉〉S9/8。2とする, ・・・02) ・・(13) 今、周囲温度Taに対する電流II , I2 , I
3の変化特性を第2図に示すとき、電流設定用の抵抗(
R2), (Rl)を、I2 > I+になるようにR
l>R2に設定すれば、第2図に示すように、定電流源
(Io2), (Ion)の温度変化はItが大きく、
又絶対値は、工2が大きい特性に設定できる。
...(1l) Here, let each junction area be SIO >89>So or 8゜゜/8.2〉S9/8.2, ...02) ...(13) Now, the ambient temperature Ta Currents II, I2, I
When the change characteristics of No. 3 are shown in Figure 2, the current setting resistor (
R2), (Rl) so that I2 > I+
If l>R2 is set, as shown in Fig. 2, the temperature change of the constant current sources (Io2) and (Ion) is large, and
Further, the absolute value can be set to a characteristic that has a large factor 2.

上記のように設定された工2を、トランジスタ(Ql1
)(qs)により構威される電流ミラー回路により工2
と同じ電流をトランジスタ(Q6)のコレクタより出力
シ、又トランジスタ(Q5)のコレクタ出力工1と直列
接続し、抵抗(R3),及びトランジスタ(Q7 ’)
 , (Q8 )で構或される電流ミラー回路より工3
:工2−41の電流を出力する, ここで、I3は第2図より明らかなように、温度上昇に
対して、減少する負の温度係数をもつことになる。
Transistor (Ql1
)(qs)
Output the same current from the collector of the transistor (Q6), and connect it in series with the collector output terminal 1 of the transistor (Q5), resistor (R3), and transistor (Q7').
, (Q8) From the current mirror circuit constructed by
:Outputs the current of 2-41.Here, as is clear from FIG. 2, I3 has a negative temperature coefficient that decreases as the temperature rises.

このようにして生或された電流I3と、トランジスタ(
Q,o+ ) , (Qo)のJOE差と抵抗(RO)
の値で設定される、正の温度係数をもつ定電流源の電流
IOが、第1図に示す点にて、加算合成され、基準抵抗
(Hrer)に印加される。従って基準抵抗(Rrer
) rlfii端に発生する基準電圧Jref’は Jrer =rrer−Rref’=Rref’( I
ロ+I3).Rre c(kT/q..4 1rlS,
’.’,.Jd’/. l41.1,.S.’.へ’i
”n又設定基準電圧Jrerの温度係数は aJr e ラtT$k/q( R.r.e rlrl
乳冒一R,re Cm .4 +R.r.e ’In 
S n. , ) , ,・i15 ) これより 工・In世+土・ト辷=1・1n鉦     ・・・(
16)R2  902 }10  801  RI  
Sn2の条件をみたすようにC,II,I2の電流設定
を行えば、この発明にかける基準電圧の温度係数はほぼ
零に設定することができる, このようにして構或された、基準電圧発生回絡は、第3
図の従来回路にみられるような基準ダイオード(nre
r)もなく、又(14)式で示されるごとく、設定1[
圧d、ffi 抗ノ比(Rref/R2, Rr”/H
, . ”’/,o) 及び、接合面積の比で設定され
る構或のため、バヲツキが少く、安定な基準電圧発生回
路を提供できると同時に、動作最少電圧も供給tfiV
cc及びGND間に直列接続される能動素子か、トラン
ジスタ1個のベースーエミッタ間電圧、とコレクターエ
ミッタ間電圧の和で構或されるため、約1v以下と、従
来回路に比べ,大幅に改善できる,なか、上記実施例は
ロpo}ランジスタを基本とした、JBE差(J.TH
E)と抵抗による定電流回路について説明したが、pn
p}ランジスタを、基本とした定電流源回路の組み合わ
せでも実現可能であり、又fIpT3トランジスタを基
本とした定電流源回路と.pnp}ヲンジスタを基本と
した定電流源回路の組み合わせでも実現及び応用可能で
ある。
The current I3 generated in this way and the transistor (
JOE difference of Q, o+ ), (Qo) and resistance (RO)
The currents IO of the constant current sources having a positive temperature coefficient, which are set at the value of , are summed and combined and applied to the reference resistance (Hrer) at the points shown in FIG. Therefore, the reference resistance (Rrer
) The reference voltage Jref' generated at the rlfii terminal is Jrer = rrer - Rref' = Rref' ( I
B+I3). Rre c(kT/q..4 1rlS,
'. '、. Jd'/. l41.1,. S. '. He'i
``The temperature coefficient of the set reference voltage Jrer is aJre tT$k/q (R.r.e rlrl
Nyuuichi R, re CM. 4 +R. r. e'In
Sn. , ) , ,・i15) From this, Engineering・Insei + Earth・Tosho = 1・1n gong ・・・(
16) R2 902 }10 801 RI
By setting the currents of C, II, and I2 so as to satisfy the conditions of Sn2, the temperature coefficient of the reference voltage applied to this invention can be set to almost zero. The circuit is the third
A reference diode (nre) as seen in the conventional circuit shown in the figure
r), and as shown in equation (14), setting 1 [
Pressure d, ffi Anti-noise ratio (Rref/R2, Rr”/H
, . ``'/,o) Since the structure is set by the ratio of the junction area and the junction area, it is possible to provide a stable reference voltage generation circuit with little fluctuation, and at the same time, it can also supply the minimum operating voltage.
Since it is composed of an active element connected in series between CC and GND, or the sum of the base-emitter voltage of one transistor and the collector-emitter voltage, the voltage is approximately 1 V or less, which is a significant improvement compared to conventional circuits. However, the above embodiment is a JBE difference (J.TH) based on a Ropo} transistor.
E) and a constant current circuit using a resistor were explained, but pn
It can also be realized by a combination of a constant current source circuit based on p} transistors, or a constant current source circuit based on fIpT3 transistors. It can also be realized and applied by a combination of constant current source circuits based on pnp transistors.

又この発明での・t子とするVBgの差電圧と抵抗のに
より設定する電流源を組み合わせる方法は、樋OS一ト
ランジスタのスレツシホールド電圧の差と、抵抗素子に
より設定する電流源をつかう場合にも広く応用できる。
In addition, in this invention, the method of combining the voltage difference between VBg and the current source set by the resistor is as follows: It can also be widely applied.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、ダイオード電圧の絶
対値の包かない、抵抗比、及び接合面積比だけで、ほと
んど決定できる基準電圧回路を提供でき、絶対値の製造
パヲツキが極端に抑えられ、高精度な基準電圧かえられ
る。又同時に、正、負温度係数の岨み合わせにより、完
全に温度補直された基準電圧となり、最少動作電圧も、
従来回路より約0.5v下げることが可能であり、バッ
テリエースの機器等低電源電圧の用途には最適である。
As described above, according to the present invention, it is possible to provide a reference voltage circuit that can be almost determined only by the resistance ratio and the junction area ratio, which does not include the absolute value of the diode voltage, and the manufacturing deviation of the absolute value can be extremely suppressed. , high precision reference voltage can be changed. At the same time, by adjusting the positive and negative temperature coefficients, the reference voltage is completely temperature compensated, and the minimum operating voltage is also
It is possible to lower the voltage by about 0.5v compared to the conventional circuit, making it ideal for applications with low power supply voltage such as Battery Ace equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による半導体集積回路化基
準電圧発生回路の回路図、第2図tI′i第1図の回路
にかいてぽ流fit, i2 , I3の周囲温度Ta
に対する変化特性を示すグラフ、第3図は従来の基準醒
圧発生回路の回路図、第4図は一般のバイポーラトラン
ジスタのベースエミッタ間電圧VBEの温度係数を示す
グラフ、第5図は一般のバイポーラトランジスタのベー
スエミッタ間電圧差jVRεの温度係数を示すグラフで
あろう 因にかいて(In+).(Io2)は電流源、<Qa)
 , (Q,or ) , (Q,o2) , (Q3
) 〜(Q】O>はトランジスタ. (RO) 〜(R
3社抵抗(Rret”)は基準抵抗であろう なお、 図中、 同一符号は同一、 又は相当部分を 示す。 代 理 入 大 岩 増 雄 正 書(自発) 平戒 @@2年2月19日 事件の表示 平 持願@l−300341号 3.補正をする者 事件との関係 特許出願人 住 所    東京都千代田区丸の内二丁目2番3号名
 称  (601)三菱電機株式会社代表者 志 岐 
守 哉 4.代理人 住所 東京都千代田区丸の内二丁目2番3号 5.補正の対象 明細書の発明の詳細な説明の欄、及び図面。 6.補正の内容 (1)  明細書第3頁第1行の「ランジスタ(Qo1
)、(QD)は、」を「ランジスタ(QOI )、(Q
O)は、」と訂正する0 (2)  明細書第4頁第2行の「q:クーワン定数、
」を「q:クーロン定数、」と訂正する。 (3〉  明細書第6頁第19行の「(10以下)」を
「( 1.0V以下)」と訂正する。 (4)  明細書第9頁第11行の「定電流源(Io1
)Jを「定電流源(I1) Jと訂正する0(5)明細
書第11頁第11行の「定電流源(Io!)、」を「定
電流源(工1)、」と訂正する。 (6)明細書第11頁第12行の「定電流源(IO2)
」を「定電流源(I2) Jと訂正する0(7)明細書
第11頁第18行〜第19行の「810)89)So 
         ・・・○又  810/s02》s
o/802           ・ Q3 Jを 「S9)810:>So            −(
Inl又  S 10 /So 2 (( 8 e/ 
So 2         − Q3 Jと訂正する。 (8)明細書第12頁第4行の「定電流源(Io2),
(Ion) Jを「定電流源(I2).(It) Jと
訂正する。 (9)  明細書第12頁第10行の「又トランジスタ
(Qs)Jを「又トランジスタ(Qo) Jと訂正する
0αO 図面中第1図を別紙のとレ9訂正する。 7.添付書類の目録 (1)  訂正図面(第1図)       1通以上 第1図 JOT, IO2・宅洗源 Q6,Qo+,Qoz,Qs〜Olo : }ランジス
タ尺0〜尺j 才氏おt Rref 基準#,杭
FIG. 1 is a circuit diagram of a semiconductor integrated circuit reference voltage generating circuit according to an embodiment of the present invention, and FIG.
3 is a circuit diagram of a conventional reference voltage generation circuit. 4 is a graph showing the temperature coefficient of the base-emitter voltage VBE of a general bipolar transistor. 5 is a graph showing the temperature coefficient of the base-emitter voltage VBE of a general bipolar transistor. This is a graph showing the temperature coefficient of the base-emitter voltage difference jVRε of a transistor (In+). (Io2) is a current source, <Qa)
, (Q,or) , (Q,o2) , (Q3
) ~(Q]O> is a transistor. (RO) ~(R
The resistance of the three companies (Rret) is probably the standard resistance, and in the diagram, the same reference numerals indicate the same or corresponding parts. Substitute Masao Oiwa Masao (self-motivated) Heikai@@2 February 19 Incident Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4. Agent address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo 5. Detailed description of the invention and drawings in the specification to be amended. 6. Contents of amendment (1) “Ran resistor (Qo1
), (QD) is ``ransistor (QOI), (Q
O) is corrected as 0 (2) "q: Kuwan's constant," on page 4, line 2 of the specification.
" is corrected to "q: Coulomb's constant,". (3> Correct “(10 or less)” on page 6, line 19 of the specification to “(1.0V or less)”. (4) “Constant current source (Io1)” on page 9, line 11 of the specification
) Correct J to “Constant current source (I1) J” 0 (5) Correct “Constant current source (Io!),” on page 11, line 11 of the specification to “Constant current source (I1),” do. (6) “Constant current source (IO2)” on page 11, line 12 of the specification
” to “Constant current source (I2) J” 0 (7) Specification page 11, lines 18 to 19 “810) 89) So
・・・○Also 810/s02》s
o/802 ・Q3 J to “S9)810:>So −(
Inl or S 10 /So 2 (( 8 e/
Correct it as So 2 − Q3 J. (8) “Constant current source (Io2),
(Ion) J is corrected as ``constant current source (I2). 0αO Correct Figure 1 of the drawings in the attached sheet. 7. List of attached documents (1) Corrected drawings (Figure 1) 1 or more copies of Figure 1 JOT, IO2/Takuraigen Q6, Qo+, Qoz ,Qs~Olo : }Rangister scale 0~shaku j Saijit Rref Reference #, Pile

Claims (1)

【特許請求の範囲】[Claims] エミッタ、ベース、コレクタを備えたバイポーラトラン
ジスタ、アノード、カソードを備えたダイオード、抵抗
素子等を、同一半導体基板上に集積化してなるバイポー
ラ型半導体集積回路において、集積化トランジスタのベ
ース、エミッタ間接合面積、又は、エミッタ電流値を、
異なる少くとも三種類以上の値に設定し、少くとも三種
類以上のベース−エミッタ間電圧J_B_E_nをもつ
トランジスタをもち、共通ベース接続された該、異なる
ベース−エミッタ間電圧をもつ2個のトランジスタのベ
ース−エミッタ間電圧J_B_E_nの差電圧ΔJ_B
_E_nと、該2個のトランジスタの一方のエミッタに
抵抗素子を直列接続し、コレクタより電流を出力する電
流発生回路Anを、少くとも3組以上有してなる、基準
電圧発生回路において、該1組の電流発生回路Aoの出
力電流I_0と、該2組の電流発生回路A_1A_2の
各々の出力電流I_1、I2を減算した後、決定される
電流(I_n−I_2)とを、加算した後出力される基
準電流(Iref=I_0+I_1−I_2)を発生さ
せることを特長とし、該、基準電流Irefを電圧設定
用抵抗素子に印加し、該電圧設定用抵抗素子の両端電圧
を基準電圧とすることを特徴とする半導体集積回路化基
準電圧発生回路。
In a bipolar semiconductor integrated circuit in which a bipolar transistor with an emitter, a base, and a collector, a diode with an anode and a cathode, a resistive element, etc. are integrated on the same semiconductor substrate, the junction area between the base and emitter of the integrated transistor , or the emitter current value,
The transistors are set to at least three different values and have at least three different base-emitter voltages J_B_E_n, and the two transistors with different base-emitter voltages are connected to a common base. Differential voltage ΔJ_B of base-emitter voltage J_B_E_n
_E_n, and at least three current generating circuits An each having a resistive element connected in series to the emitter of one of the two transistors and outputting a current from the collector. After subtracting the output current I_0 of the set of current generating circuits Ao and the output currents I_1 and I2 of the two sets of current generating circuits A_1A_2, the determined current (I_n-I_2) is added and output. The reference current Iref is applied to a voltage setting resistance element, and the voltage across the voltage setting resistance element is set as the reference voltage. A semiconductor integrated circuit reference voltage generation circuit.
JP30034189A 1989-11-17 1989-11-17 Reference voltage generating circuit made into semiconductor integrated circuit Pending JPH03160513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30034189A JPH03160513A (en) 1989-11-17 1989-11-17 Reference voltage generating circuit made into semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30034189A JPH03160513A (en) 1989-11-17 1989-11-17 Reference voltage generating circuit made into semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH03160513A true JPH03160513A (en) 1991-07-10

Family

ID=17883609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30034189A Pending JPH03160513A (en) 1989-11-17 1989-11-17 Reference voltage generating circuit made into semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH03160513A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102591401A (en) * 2012-03-16 2012-07-18 北京经纬恒润科技有限公司 Built-in digital power circuit
JP2023042059A (en) * 2021-09-14 2023-03-27 ウィンボンド エレクトロニクス コーポレーション Temperature compensation circuit and semiconductor integrated circuit using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102591401A (en) * 2012-03-16 2012-07-18 北京经纬恒润科技有限公司 Built-in digital power circuit
JP2023042059A (en) * 2021-09-14 2023-03-27 ウィンボンド エレクトロニクス コーポレーション Temperature compensation circuit and semiconductor integrated circuit using the same
US11809207B2 (en) 2021-09-14 2023-11-07 Winbond Electronics Corp. Temperature compensation circuit and semiconductor integrated circuit using the same

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