JPH03160498A - Speech recognizing device - Google Patents

Abstract

PURPOSE:To necessitate just one input pattern memory and to obtain the inexpensive speech recognizing device by providing plural matching sections. CONSTITUTION:This device is provided with an auxiliary control section 11 which has the one input pattern memory 5 to store the characteristic quantity of matching as input pattern data and an address counter 6 to assign an address to the input pattern memory 5 and executes the control to clear the address counter 6 by receiving the matching start signal from a control section 9 and to send the input pattern data to the matching sections 8a, 8b by reading the data out of the input pattern memory 5. The matching sections 8a, 8b are fully synchronized to read the input pattern data from the one input pattern memory at the time of reading of the input pattern data. The just one input pattern memory is necessitated in this way even if the matching sections are plural. The cost is thus reduced and the less space is occupied over the entire part of the matching sections.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speech recognition device for word speech, and particularly to one that performs multiple matchings in parallel.

[Prior Art] FIG. 2 is a block diagram showing conventional speech recognition. In the figure, 1 is a microphone, 2 is a preprocessing unit that performs a spectrum analysis of the audio input from the microphone 1, 3 is an extraction unit that detects a voice section from the audio data spectrally analyzed by the preprocessing unit 2, and 4 is a A feature amount calculating section 5a and 5b calculates a matching feature amount from the audio data of the audio section detected by the extraction section 3, and input pattern memories 5a and 5b store the matching feature amount calculated by the feature amount calculating section 4 as input pattern data. 5a and 6b are human caper tan memory 5
Address counter pointing to address a, 5b, 7a, 7
8a is a standard pattern memory that stores the standard pattern of the matching characteristic in two parts, and 8a is the input pattern data of the input pattern memory 5a and the standard pattern memory 7a.
A matching unit 8b performs matching with a standard pattern and outputs the distance to the standard pattern, and 8b is a combination of the input pattern data of the input pattern memory 5b and the standard pattern memory 7.
A matching section 9 performs matching with the standard pattern b and outputs the distance from the standard pattern; 9 a control section that calculates the category name with the minimum distance value from the distance values sent from each matching section 8a and 8b; lO is a display section that displays the category name determined by the control section 9.

A conventional speech recognition device is configured as described above. For example, word speech input from the microphone 1 is processed by the preprocessing section 2 into the L
Spectrum analysis such as PC chevstral analysis or filter bank is performed. Then, the cutout section 3 detects a speech section from the speech data subjected to spectrum analysis by the preprocessing section 2 . The audio data extracted as audio sections by the extraction unit 3 is sent to the feature amount calculation unit 4. The feature amount calculation unit 4 calculates matching feature amounts used during matching, such as the amount of spectrum change and the power DP value, from the audio data of the audio section sent from the extraction unit 3. The matching feature amount calculated by the feature amount calculation unit 4 is addressed by address counters 5a and 5b, respectively, and stored as input pattern data in input pattern memories 5a and 5b, respectively. Input pattern memories 5a and 5b
The matching features stored in the ma-noting unit 8a,
8b. In the matching units 8a and 8b, input pattern memories 5a. Matching is performed between the input pattern data of 5b and the standard patterns shared by standard pattern memories 7a and 7b, respectively, and distance values with respect to the standard patterns are output to the control unit 9, respectively. In the control section 9, a matching section 8a. The category name having the minimum distance value is determined from among the distance values sent from the distance values 8b, and the category name is outputted to the display section 10, and the category name is displayed on the display section IO.

In this way, a plurality of matching units 8a, 8 . b, and a plurality of matching parts 8
Since a and 8b share the calculation of matching distance values between the input pattern data and the standard pattern and perform parallel processing, speech recognition processing for many words can be performed in a short time. In addition, in this conventional example, the matching part is 8a,
8b, but the number is not limited to two, and as long as it has a large number of matching units, it becomes possible to perform word speech recognition processing even more quickly.

[Problems to be Solved by the Invention] However, in the speech recognition device having the above structure, since there are two matching units 8a and 8b that match input pattern data and a standard pattern, each matching unit 8a
, 8b are required to input the input pattern data, and the matching section as a whole is expensive and requires a large amount of space.

The present invention has a plurality of matching sections as described above, thereby eliminating the disadvantage that a plurality of input pattern memories are required, which makes the entire matching section expensive and requires a large amount of space. The purpose of the present invention is to provide an inexpensive speech recognition device that requires only a few steps.

[Means for Solving the Problems] The present invention provides a speech recognition device that includes one input pattern memory that stores, as input pattern data, matching feature quantities calculated by a feature quantity calculation unit from speech data of a speech interval; and an input pattern memory. In response to the matching start signal from the control section and the address counter that specifies the address, the address counter is cleared, and in synchronization with a specific clock synchronization signal, input pattern data is read from the input pattern memory and sent to each matching section. A sub-control unit is provided to control the transmission.

[Function] According to the present invention, since the speech recognition device is configured as described above, the sub-control unit receives the matching start signal from the control unit, clears the address count, and at the same time stores data in one input pattern memory. Since the input pattern data, which is the stored matching feature amount, is read out in synchronization with a specific clock signal and sent to each matching section, each matching section can match the input pattern data with the standard pattern. Therefore, the above problem can be eliminated.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart of the sub-control section. In the figure, the same configuration as the conventional example is designated by the same reference numeral LI! The explanation of the restored structure will be omitted. 5 is one input pattern memory, the output side of which is connected to matching sections 8a and 8b, respectively. 6 is one address counter corresponding to the input pattern memory 5, and 11 is a sub-control section connected to the input pattern memory 5, address counter 6, matching sections 8a, 8b, and one control section.

Next, the operation of the above embodiment will be explained in detail with reference to FIGS. 1 and 3.

The word speech input from the microphone 1 is subjected to spectrum analysis in the preprocessing section 2, and the speech section is detected from the spectrum-analyzed speech data in the extraction section 3. A matching feature amount is calculated from the voice data of the voice section thus obtained, and the matching feature amount is stored in the input pattern memory 5 as input pattern data.

The procedure from inputting a word sound to the microphone 1 to storing input pattern data in the input pattern memory 5 is the same as in the conventional example. Therefore, a step-by-step explanation will be given starting from the time when the matching start signal A is given from the control section 9 to the sub-control section l1.

First, as shown in FIGS. 1 and 3, when the matching start signal A is input from the control unit 9 to the sub-control unit l1, the sub-control unit 11 synchronizes with t1 of the clock C in the sub-control unit 11. The switching state signal B in 11 becomes "1". Note that each switching section 8a, 8b operates in synchronization with clock C. Further, the sub-control unit 1l outputs a counter clear signal by differentiating the rising edge of the matching start signal A, and clears the address counter 6 pointing to the address of the input pattern memory 5 shown in FIG. Furthermore, as shown in FIG.
The input pattern memory read signal E is obtained by inverting the logical product with the state of "1", and the input pattern memory read signal E is output to the input pattern memory 5, and the input pattern memory read signal E is in the state of "0". At this time, the input pattern data from the input pattern memory 5 is transferred to each matching section 8.
It is output to a and 8b. Each matching section 8a. 8b is synchronized with the clock C from the sub-control unit l1, so after the input pattern data is output to each matching unit 8a, 8b, each matching unit 8a, 8b combines the input pattern data with each standard pattern memory 7a, 7b. Matching with the shared standard pattern begins.

Further, in the sub-control section 11, as shown in FIG. 3, the input pattern memory readout signal E is delayed to generate a counter up signal, which is input to the address counter 6 to set the address value of the input pattern memory 5 to +1.

The above operations are executed in synchronization with the clock C, and the contents of the input pattern memory 5 are sequentially transferred to the matching section 8a. 8b. Then, in the matching units 8a and 8b, the input pattern data and each standard pattern memory 7a,
Matching with the target pattern 7b is performed sequentially.

When the matching is completed, a signal indicating the completion of matching is input from the matching units 8a and 8b to the control unit 9, and the control unit 9 receives this signal and inputs a matching stop signal to the sub-control unit 1l as shown in FIG. do.

Although the above description applies the present invention to a voice recognition device, it goes without saying that the present invention can also be applied to an OCR or image recognition device that performs a large amount of matching processing using a plurality of matching units.

[Effects of the Invention] As described in detail above, according to the present invention, there is provided one input pattern memory that stores a matching feature amount as input pattern data, an address counter that specifies an address to the input pattern memory, and a control unit. and a sub-control section that clears an address counter upon receiving a matching start signal from the matching section, and controls the input pattern data to be read from the input pattern memory and sent to each matching section in synchronization with a specific clock synchronization signal. , we have one input pattern memory, all matching units are synchronized, and input pattern data is read from one input pattern memory when input pattern data is read, so even if there are multiple matching units, the input pattern memory Since only one is required, it can be expected that a voice recognition device can be obtained which is cheaper than the conventional one and does not require much space for the matching section as a whole.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional speech recognition device, and FIG. 3 is a time chart of a sub-control unit. 5... Input pattern memory, 6... Address counter, 8a, 8b... Matching section, 9... Control section,
11... Sub-control unit.

Claims (1)

[Scope of Claims] A preprocessing unit performs spectrum analysis of input speech, an extraction unit detects a speech interval from the spectrum-analyzed speech data, and a feature quantity calculation unit calculates matching features from the speech data of the speech interval. In a speech recognition device, a plurality of matching units perform matching between a trace amount and a standard pattern during matching, and a control unit determines a category name that has the smallest distance value from the distance values output from each matching unit. , one input pattern memory that stores the matching feature amount as input pattern data, an address counter that specifies an address in the input pattern memory, and receives a matching start signal from the control unit to clear the address counter and perform a specific input pattern. A speech recognition device comprising: a sub-control unit configured to read input pattern data from an input pattern memory and send it to each matching unit in synchronization with a clock synchronization signal.