JPH0316041B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital delay circuit, and more particularly to a digital delay circuit that delays one or two channels of digital signals by a desired time using a digital memory circuit.

Conventional technology Digital delay circuits have been used for various purposes. For example, when applied to a reverberation sound adding device, an analog shift register such as a BBD (bucket brigade device) is used as a delay circuit. compared to the signal-to-noise ratio (S/
N), various characteristics such as frequency characteristics, distortion rate, and dynamic range can be improved. FIG. 7 shows a block diagram of an example of a reverberation sound adding device having this digital delay circuit. In the figure, the analog audio signal of the first channel inputted to the input terminal 1a passes through a buffer amplifier 2a and a low-pass filter 3a, respectively, and then passes through an A/D integration circuit 4a and a 16-bit A/D conversion section 5a. For example, a cascade integration type A/D conversion circuit (the timing of its sampling ratio is determined by the terminal of the control circuit 6).
Determined by the conversion command from CC1. ) after being sampled and quantized into digital data with, for example, 32 bits per sampling point (sampling frequency, e.g. 44.056 kHz).
It is applied to the data input terminal D.IN of the control circuit 6.
On the other hand, the analog audio signal of the second channel enters the input terminal 1b, and in the same manner as above, the buffer amplifier 2b, the low-pass filter 3b, the A/D integration circuit 4B, and the 16-bit A/D converter 5b (its sample (The timing of the conversion is determined by the conversion command rather than the terminal CC2 of the control circuit 6.)
After being converted into digital data, the data is applied to the data input terminal D.IN of the control circuit 6. The control circuit 6 receives two channels of input digital data alternately for each channel and in a time-division manner every half period of the sampling period.

The control circuit 6 serially inputs the above 32-bit digital data to the first-stage D.RAM ₇₁ of n dynamic random access memories (D.RAM) ₇₁ to _7o (where n is any natural number). Lead from output terminal DDOUT. In addition to outputting within the write cycle time (for example, within 20 μs), D.
It outputs an 8-bit address signal to the RAMs ₇₁ to _7o , and also outputs a write control signal and a strobe signal, respectively. Digital data is delayed by sequentially transferring each address of D.RAM ₇₁ to _7o , but the 64k bit D.
The delay time τ for one RAM is - the number of quantization bits of the sample point is x, and the read/write cycle time is t.
(second) is expressed as (2 ⁸ × 2 ⁸ ) × t/x (unit second).

The delay time can be controlled by a first method in which the data selector 8 combines and outputs the outputs of any P.RAM among the D.RAMs ₇₁ to _7o , and a first method in which the data selector 8 outputs a combination of the outputs of any P.RAM from among the D.RAMs 71 to 7o. ,
A second method is performed by controlling the combination of 8 bits of column address, and variable resistor 1.
There is a third method in which the frequency of the bit clock B.CLK is controlled by 0 to change the period of the read/write cycle. The digital data delayed by the desired time in this manner is transferred to the control circuit 6.
The signal is input to the input terminal DDIN of , and is further connected to, for example, a simultaneous integration type D/A conversion circuit consisting of a 16-bit D/A conversion section 11 and a D/A integrator/glitch circuit 12 via its output terminal D.OUT. It is then converted back to an analog signal.

The delayed analog audio signal taken out from the D/A integrator/glitch circuit 12 is supplied to switch circuits 13 and 14, respectively. 16 bit D/
The symmetrical square wave with the sampling period taken out from the A converter 11 is directly supplied to the switch circuit 13, while the symmetrical square wave with the opposite phase is supplied to the switch circuit 1.
4 and are turned on and off alternately every half of the sampling period. As a result, the delayed analog audio signal of the first channel is taken out from the switch circuit 14, and the delayed analog audio signal of the first channel is taken out from the switch circuit 14.
6a, buffer amplifier 17a, variable resistor 18
a, buffer amplifier 2a after passing through amplifier 19a
is supplied to the input terminal 1a, where it is mixed with the original analog audio signal from the input terminal 1a. On the other hand, the second channel delayed analog audio signal is taken out from the switch circuit 13, and is supplied to the buffer amplifier 2b via the low-pass filter 16b, buffer amplifier 17b, variable resistor 18b, and amplifier 19b in the same manner as described above. Thereafter, the same operation as above is repeated, and a multiplexed signal of the delayed analog audio signal and the original analog audio signal is outputted to the output terminals 20a and 20b for each channel.

Problems to be Solved by the Invention However, in the above device, when trying to add an analog audio signal with a desired delay time to the analog audio signal of one channel (when using one channel), the above two channels are also added. As with the simultaneous processing of signals, each operation of the A/D conversion circuit and D/A conversion circuit and the D.RAM7 ₁ to 7 _o
Since all control processing is performed in phase synchronization with the output bit clock B.CLK of the control circuit 6, the data processing speed per channel of P.RAM ₇₁ to _7o is equivalent to the A/D/D/A conversion cycle. twice (i.e. half the period of the sampling period)
It's getting old. Therefore, when using one channel, half of the read/write cycle time is
P.RAM7 ₁ to 7 _o does not contribute to the actual delay of digital data and reduces its storage capacity.
The problem was that it was not 100% used and was uneconomical.

Therefore, the present invention provides a digital delay circuit that solves the above problems by alternately repeating writing and reading of D.RAM and pausing its operation every half period of the sampling period when one channel is used. The purpose is to

Means for Solving the Problems FIG. 1 is a block diagram showing the configuration of the main part of the present invention, and shows a circuit corresponding to the main part of the control circuit 6 shown in FIG. The digital delay circuit includes first and second A/D conversion circuits, a single D/A conversion circuit,
It is roughly composed of a first and second switch circuit that distributes the D/A conversion output into two systems, n digital memories such as D.RAM, and a control circuit that controls them. It has the same configuration as the figure. In FIG.
outputs a constant frequency bit clock B.CLK. The timing clock circuit 26 is supplied with the bit clock and a signal indicating the number of channels of input digital data and the type of channel, and has a symmetrical period equal to the sampling period of the input digital data generated by dividing the bit clock. In addition to outputting a frequency-divided pulse that is a square wave, when the number of channels of input digital data is two, a pulse synchronized in phase with the bit clock is always output as a gate, and when the input digital data is only the first channel, the pulse is synchronized in phase with the bit clock. A synchronized pulse is gated out for a period when the frequency-divided pulse is at a first logic level, and when the input digital data is only on the second channel, a pulse synchronized in phase with the bit clock is output at a period when the frequency-divided pulse is at a second logic level. Gate output for a certain period.
The control timing circuit 27 is a circuit that generates various clock pulses for controlling the A/D conversion circuit and the D/A conversion circuit. First and second A/D conversion clock pulses are output as signals and are supplied to the first and second A/D conversion circuits, respectively, when the input digital data is of two channels.
AD-1 and AD-2, and the first and second pulses DA-1 and DA-2, which are the switching signals of the first and second switch circuits that distribute the output signals of the D/A conversion circuit into two systems. Output each. However, when the input digital data is one channel, the control timing circuit 27 outputs pulses AD-1 and DA-1 (or AD-2 and DA-1).
2) The synchronization signal LRCK and bit clock B.
Output with CLK, pulse AD-2 and DA-2
(or AD-1 and DA-1) are not output.

Further, the read/write control circuit 28 is supplied with a pulse synchronized in phase with the bit clock output from the gate from the timing clock circuit 26, and outputs a write/read control signal for the digital memory circuit, and also outputs a read/write control signal for the digital memory circuit.
1 bit (for example, n is 7) address signal A ₀ ~
Output A _o . However, in the present invention, when the input digital data is 2 channels, the address signals A ₀ to A _o are sequentially output at approximately half of the sampling period, whereas when the input digital data is 1 channel, the address signals The output of the address signals A ₀ to A _o and the suspension of the output are alternately repeated approximately every half cycle. Note that when the output of the address signal is stopped, the output of the write/read control signal is also stopped.

Function When the input digital data is one channel, the address signal and the write/read control signal are output only when the digital data of the first (or second) channel is synchronized, and the address signal is output when the second (or first) channel is synchronized. Since the output of the write and read control signals is stopped, the digital memory circuit performs write and read operations only when the first (or second) channel is synchronized, and operates at a sampling period synchronized with the input digital data of the first channel. This allows 100% of the storage capacity of the digital memory circuit to be used efficiently. Hereinafter, the circuit of the present invention will be explained along with examples.

Embodiment FIG. 2 shows a circuit diagram of essential parts of an embodiment of the circuit of the present invention. In the figure, the same components as in FIG. 1 are designated by the same reference numerals. In FIG. 2, the clock generator 25 generates and outputs a symmetrical square wave of, for example, 1.5 MHz, and outputs this as a bit clock B.CLK through the control timing circuit 27, while the waveform shaping/differentiating circuit in the timing clock circuit 26 30 and 1/32 frequency dividers 31, respectively. The waveform shaping/differentiating circuit 30 generates a narrow pulse that falls in phase synchronization with, for example, the falling edge of the bit clock B.CLK, and supplies this pulse to one input terminal of the NAND circuit 34. Further, the 1/32 frequency divider 31 generates a frequency division pulse with a period equal to the sampling period of the digital data to be delayed, and this frequency division pulse is passed through the exclusive OR circuit 41 and the OR circuit 33 to the NAND circuit 34. supply to the other input terminal, and also the A/D input terminal.
The third
It is output as a synchronization signal LRCK as shown in FIG. C and FIG. 5A.

The 1-channel/2-channel control circuit 32 is a circuit that generates signals according to the number of channels, and is composed of two switches S ₁ and S ₂ , an exclusive OR circuit 38, and inverters 39 and 40, and is a circuit that generates signals according to the number of channels. When there are two channels, switches S ₁ and S ₂ are both turned on; when the data to be delayed is one channel and it is the first channel, only switch S 1 is turned on; when it is the second channel, only switch S ₁ is turned on; Only switch _S2 is turned on.
First, we will explain the case where two channels of digital data are delayed.
2 channel control circuit 32 is a switch
Since both S ₁ and S ₂ are turned on, the inverter 39 supplies a high level signal to the OR circuit 32 and the inverter 40 supplies a high level signal to the exclusive OR circuit 41. As a result, the signal supplied from the OR circuit 33 to the NAND circuit 34 is always at a high level. This results in
From the NAND circuit 34, the waveform shaping/differentiation circuit 30
A pulse having the opposite phase of the output pulse of
The signals are respectively supplied to the address counter control circuit 37.

As a result, the D.RAM read/write control circuit 36 outputs the strobe signal shown in FIG. 4B, which is phase synchronized with the bit clock B.CLK shown in FIG. A write control signal shown in , a signal WE having the opposite phase to this signal, and an XY address signal that determines the output timing of the row address and column address are output, respectively. At the same time, the circuit 37 outputs 8-bit address signals _A0 to _A7 in parallel. This address signal A ₀ ~ A ₇
is a signal indicating an 8-bit row address or an 8-bit column address. Here, address signals A ₀ to _{A 7}
The row address and column address of , as shown in FIG. 4C, are switched by the XY address signal in accordance with the strobe signals shown in FIG. 4B and D. As shown in FIG. 3D, the circuit 37 outputs an 8-bit row address and an 8-bit column address alternately, 32 times in total, at approximately half the sampling period. In other words, the D.RAM address defined by the 8-bit row address and 8-bit column address changes sequentially 16 times in approximately half the sampling period, and the address counter (not shown) changes 16 times in approximately half the sampling period.
Count.

D.RAM receives the row address signal 8 when the strobe signal falls as shown in FIG. 4B and C.
When the bit is input and the strobe signal falls as shown in figure D, 8 bits of the column address signal are input, and after a certain period of time after the strobe signal falls, the write control signal is input as shown in figure E. before writing the input digital data to the address specified by the above 8 bits of column address and 8 bits of row address.
The configuration is such that the digital data previously stored at the same address is read out. Note that the signals shown in FIGS. 4F and 4G represent signals read from D.RAM and input digital data supplied to D.RAM, respectively. Further, the numerical value at the top of the waveform of bit clock B.CLK shown in FIG. 4A indicates the generation timing of a clock obtained by multiplying bit clock B.CLK by eight.

Further, the A/DD/A control circuit 35 is
The first and second A/D conversion clock pulses AD-1 and AD-2 shown in FIGS. 3A and B, which are equal to the sampling period and have opposite phases to each other (these are CC1 and CC2 in FIG. 7) ), and also generates and outputs the first and second pulses as shown in E and F of the same figure.
Generates and outputs DA-1 and DA-2, respectively. Two A/D conversion circuits (corresponding to 4a and 4b in FIG. 7) to which two channels of digital data are supplied separately have a sampling period from the rising edge of clock pulses AD-1 and AD-2 to the next rising edge. Samples and quantizes the input analog signal. here,
Clock pulses AD-1 and AD-2 are shown in Figure 3A,
As can be seen from B, since the phases are opposite to each other, the two A/D conversion circuits perform A/D conversion operations with a difference of half a sampling period from each other. Further, the first and second pulses DA-1 and DA-2 are passed through a D/A converter (corresponding to 11 in FIG. 7), respectively, to two switch circuits (corresponding to 11 in FIG. 7) provided at the output end of the D/A converter circuit. (corresponding to 13 and 14 in FIG. 7) as switching signals, which are turned on during the high level period and turned off during the low level period. As a result, it is possible to perform the desired delay of the two-channel digital data, similar to the conventional method described with reference to FIG.

Next, we will explain the case where the input digital data is one channel.
In the two-channel control circuit 32, when the digital data of one channel is the first channel, the switch _S1 is turned on and the switch _S2 is turned off.
Further, when the digital data of the first channel is the second channel, the switch _S1 is turned off and the switch _S2 is turned on. Now, assuming that the digital data of the first channel is delayed, the inverter 3
9 outputs a low level signal, and inverter 40 outputs a high level signal.

Therefore, the exclusive OR circuit 41 takes out a pulse with the opposite phase to the output pulse of the 1/32 frequency divider 31, and since the output signal of the inverter 39 is at a low level, the NAND circuit 34 is taken out from the OR circuit 33. The signal supplied to the 1/32 frequency divider 31 is a pulse having an opposite phase to the output pulse of the 1/32 frequency divider 31. Therefore, the NAND circuit 34 always outputs a high-level signal during the high-level period of the synchronizing signal LRCK, which is the output of the 1/32 frequency divider 31 shown in FIG. The output signal of the shaping/differentiating circuit 30 is gate-outputted. As a result, D.RAM read/
The write control circuit 36 uses a write/read control signal only during the low level period of the synchronization signal LRCK.
Generates and outputs RAS, etc., and synchronizes the signal.
This control signal is not generated and output during the high level period of LRCK. The A/DD/A conversion control circuit 35 also outputs a first clock pulse AD/1 as shown in FIG. 5A and a first clock pulse AD/1 as shown in FIG.
Generates only DA/1, second clock pulse
AD-2 and second pulse DA-2 are not generated or output, respectively.

Furthermore, D.RAM address counter. The control circuit 37 receives a synchronizing signal as shown in FIG.
Address signal A ₀ ~ only during low level period of LRCK
_A7 is generated and the address signal is not generated and output during the next high level period, which is repeated alternately. As a result, only the digital data of one of the two channels of digital data transmission paths is A/DD/A converted, and is also written to and read out from the D.RAM at the sampling period.

Note that when the digital data of the second channel is delayed, the switch _S1 is turned off and the switch _S2 is turned on, so that the output signal of the inverter 39 becomes low level and the output signal of the inverter 40 becomes low level. Therefore, from the exclusive OR circuit 41, the synchronization signal which is the output signal of 1/32 period 31
A signal in phase with LRCK (shown in FIG. 6B) is taken out and supplied to a NAND circuit 34 through an OR circuit 33. Therefore, in this case, as can be easily inferred from the above explanation, the address signal is activated as shown in FIG. 6C during the high level period of the synchronization signal LRCK.
A ₀ to A ₇ are generated, and a second clock pulse AD-2 as shown in A of the same figure and a second clock pulse DA-2 as shown in D of the same figure are generated and output.

It goes without saying that the present invention can also be used for applications other than the reverberation sound adding device.

Effects of the Invention As described above, according to the present invention, in a circuit that delays two channels of digital data separately for a desired time, one channel of digital data can be processed with half the amount of memory used when two channels are used. Therefore, by using the digital memory circuit 100% efficiently, it is possible to obtain a delay time up to twice as much as when using two channels.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing the main part of the configuration of the circuit of the present invention, FIG. 2 is a circuit system diagram showing the main part of an embodiment of the circuit of the invention, and FIGS. FIG. 6 is a signal waveform diagram for explaining the operation of the circuit of the present invention, and FIG. 7 is a block system diagram showing an example of a two-channel reverberation sound adding device to which the circuit of the present invention can be applied. 1a, 1b...Analog audio signal input terminal, 4a, 4b...A/D integration circuit, 5a, 5b...
16-bit A/D converter, 6...control circuit, 7 ₁ to 7 _o
...Dynamic random access memory (D.RAM), 11...16-bit D/A converter, 12
...D/A integrator/glitch circuit, 20a, 20b
...Analog audio signal output terminal, 25...Clock generator, 26...Timing clock circuit, 2
7... Control timing circuit, 28... Read/write control circuit, 30... Waveform shaping, differentiation circuit, 31... 1/32 frequency divider, 32... 1 channel.
2 channel control circuit, 35...A/D.
D/A conversion control circuit, 36...D.RAM read. Light control circuit, 37...D.RAM
Address counter control circuit.

Claims (1)

[Claims] 1. Writing and reading of one or two channels of digital data obtained by sampling and quantizing one or two channels of analog signals using an A/D conversion circuit into a digital memory circuit. A digital delay circuit that outputs digital data delayed from the memory circuit to a D/A conversion circuit by sequentially passing through each address, the clock generator outputting a bit clock of a constant frequency; A signal indicating the number of channels and the type of channel and the bit clock are respectively supplied, and the bit clock is divided to generate a divided pulse which is a symmetrical square wave with a period equal to the sampling period of the input digital data. At the same time, when the number of channels of the input digital data is two, a pulse synchronized in phase with the bit clock is always gated out,
When the input digital data is only on the first channel, a pulse synchronized in phase with the bit clock is gated out while the frequency-divided pulse is at the first logic level, and when the input digital data is on the second channel only, the gate is output. a timing clock circuit for gate-outputting a pulse whose phase is synchronized with a bit clock for a period when the frequency-divided pulse is at a second logic level; In addition, when the input digital data is of two channels, the first and second A/D conversion clock pulses for obtaining two channels of digital data, and the delayed analog signal of two channels are outputted as a synchronization signal of the D. The first and second pulses used as switching pulses of the switch circuit are distributed and outputted from the output terminal of the /A conversion circuit, and when the input digital data is one channel, the first or second A a control timing circuit that outputs only the clock pulse for /D conversion and the first or second pulse, and a pulse that is phase-synchronized with the bit clock outputted from the gate by the timing clock circuit, and the input digital data is divided into two channels. When , the write/read control signal of the digital memory circuit is outputted, and the address signal of the digital memory circuit is sequentially outputted approximately every half period of the sampling period, and when the input digital data is one channel, the sampling signal is outputted. A digital delay circuit comprising a read/write control circuit that alternately repeats outputting and pausing the output of the write/read control signal and address signal approximately every half cycle.