JPH03159126A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03159126A JPH03159126A JP29832689A JP29832689A JPH03159126A JP H03159126 A JPH03159126 A JP H03159126A JP 29832689 A JP29832689 A JP 29832689A JP 29832689 A JP29832689 A JP 29832689A JP H03159126 A JPH03159126 A JP H03159126A
- Authority
- JP
- Japan
- Prior art keywords
- electrode material
- material layer
- silicon film
- thin silicon
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 title claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- 239000007772 electrode material Substances 0.000 claims abstract description 32
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 229910018125 Al-Si Inorganic materials 0.000 claims abstract 2
- 229910018520 Al—Si Inorganic materials 0.000 claims abstract 2
- 239000010409 thin film Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 8
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 abstract description 7
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- 230000003628 erosive effect Effects 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 34
- 239000010408 film Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 8
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 125000001165 hydrophobic group Chemical group 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 235000021419 vinegar Nutrition 0.000 description 1
- 239000000052 vinegar Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はアルミとレジストとの密着性が悪いことに起因
するアルミ層上部の所謂“虫食い′”の防止に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to the prevention of so-called "worm-eaten" on the upper part of the aluminum layer due to poor adhesion between aluminum and resist.
（ロ）従来の技術
ＩＣ，ＬＳＩの製造においては、個々の素子を結線する
ための電極配線の形成が必要不可欠である。電極材料と
してはＡＩアルミニウム）、又はＡＮ−Ｓｉ（アルミニ
ウムーシリコン）が主に用いられ、材料の堆積とホトエ
ッチによるパターニングにより前記電極配線が形成され
る。電極材料のホトエツチングには等方性と異方性との
２通りがあって、異方性の方が微細加工に適するものの
、側面が傾斜し平坦化に有利なことから、等方性エツチ
ングは欠かせない存在である。また、両者の利点を活か
して上半分を等方、下半分を異方性で行うことも行われ
ている。(B) Conventional Technology In the manufacture of ICs and LSIs, it is essential to form electrode wiring for connecting individual elements. As the electrode material, AI (aluminum) or AN-Si (aluminum-silicon) is mainly used, and the electrode wiring is formed by depositing the material and patterning by photoetching. There are two types of photoetching for electrode materials: isotropic and anisotropic. Although anisotropic is more suitable for microfabrication, isotropic etching is more suitable for flattening because the sides are inclined. It is an essential presence. Furthermore, taking advantage of the advantages of both, the upper half is isotropic and the lower half is anisotropic.
第２図（Ａ）（Ｂ）は上記電極配線のホトエツチング工
程を示し、先ず絶縁層（１）上に１電極材料層（２）を
蒸着又はスパッタにより堆積し、その表面にホトレジス
トによるレジスト層（３）を形成し、このレジスト層（
３）をマスクとして第２図Ｂに示す如く電極材料層〈２
）をウェットエツチングすることにより電極配線（４）
を形成する（例えば、特開昭６４−３９０２６号公報）
。FIGS. 2(A) and 2(B) show the photoetching process of the electrode wiring. First, one electrode material layer (2) is deposited on the insulating layer (1) by vapor deposition or sputtering, and a resist layer (of photoresist) is formed on the surface of the electrode material layer (2). 3) and this resist layer (
3) as a mask, the electrode material layer <2
) by wet etching the electrode wiring (4)
(For example, Japanese Patent Application Laid-open No. 64-39026)
.
そして、前記ホトレジストは従来のネガ型に替り微細化
が有利なポジ型が主流になっている。As for the photoresists, positive type photoresists, which are advantageous in miniaturization, have become mainstream instead of the conventional negative type.
（ハ）発明が解決しようとする課題
しかしながら、ポジ型レジストと電極材料のアルミとは
密着性が悪いという難点がある。そのため、レジスト層
（３）と電極材料層（３）との密着部にエツチング液が
侵入して、第３図に示すように電極配線（４）の上部（
トップ）に材料がオーバーエッチされた欠け、所謂虫食
い（５）が発生し、電極配線（４）の信頼性低下を招く
欠点があった。(c) Problems to be Solved by the Invention However, there is a drawback in that the positive resist and the aluminum electrode material have poor adhesion. Therefore, the etching solution enters into the close contact between the resist layer (3) and the electrode material layer (3), and as shown in FIG.
There was a problem in that the material was over-etched and chipped (so-called moth bite (5)) occurred on the top (top), leading to a decrease in the reliability of the electrode wiring (4).
（ニ）課題を解決するための手段
本発明は上記従来の欠点に鑑み成されたもので、電極材
料層（１１）の表面にシリコン薄膜（１３）を堆積し、
この表面にレジスト層（１４）を形成してウェットエツ
チングを行うことにより虫食い現象を防止した半導体装
置の製造方法を提供するものである。(d) Means for Solving the Problems The present invention was made in view of the above-mentioned conventional drawbacks, and consists of depositing a silicon thin film (13) on the surface of the electrode material layer (11),
The present invention provides a method for manufacturing a semiconductor device in which the worm-eaten phenomenon is prevented by forming a resist layer (14) on this surface and performing wet etching.
（ホ）作用
本発明によれば、シリコン薄膜（１３）とレジスト層（
１４）とが良好な密着性を示し、且つシリコン薄膜（１
３）と電極材料層（１１）との密着性はレジスト層（１
４）と電極材料層（１１）とのそれよりは大きいので、
電極材料層（１１）界面へのエツチング液の侵入を防止
できる。(E) Function According to the present invention, the silicon thin film (13) and the resist layer (
14) shows good adhesion, and the silicon thin film (1
3) and the electrode material layer (11).
4) and the electrode material layer (11),
It is possible to prevent the etching solution from entering the interface of the electrode material layer (11).
（へ）実施例
以下に本発明の一実施例を第１図（Ａ）（Ｂ）を用いて
詳細に説明する。(F) Example An example of the present invention will be described below in detail with reference to FIGS. 1(A) and 1(B).
第１図Ａはレジストパターンの形成が終了した断面を示
している。電極材料層（１１）は、素子形成が終了した
シリコンウェハ表面を覆うＳｉＯｔ等から成る絶縁膜（
１２）上に設けられ、１２（アルミニウム）又はシリコ
ンを数％含有するＡＮ−Ｓｉ（アルミニウムーシリコン
）を蒸着又はスパッタ法により堆積することで得られる
。膜厚は０．５〜２．０μである。尚、絶縁膜（１２）
には下層の配線又は素子を構成する拡散領域とコンタク
トするためのコンタクトホール（図示せず）が設けられ
ている。FIG. 1A shows a cross section after formation of a resist pattern is completed. The electrode material layer (11) is an insulating film (made of SiOt, etc.) that covers the surface of the silicon wafer on which element formation has been completed.
12) and is obtained by depositing AN-Si (aluminum-silicon) containing several percent of 12 (aluminum) or silicon by vapor deposition or sputtering. The film thickness is 0.5 to 2.0μ. In addition, the insulating film (12)
A contact hole (not shown) is provided for contacting the underlying wiring or the diffusion region constituting the element.
その後、電極材料層（１１）の表面にスパッタ法により
膜厚５００〜２０００人のノンドープ、Ｎ型、Ｐ型のシ
リコン薄膜（１３）を堆積する。Thereafter, a non-doped N-type, P-type silicon thin film (13) is deposited on the surface of the electrode material layer (11) to a thickness of 500 to 2000 by sputtering.
尚、シリコン薄膜（１３）の堆積の前に、電極材料層（
１１）の表面をポジレジストの現像液のような、アルカ
リ水溶液で処理することにより、電極材料層（１１）の
表面に自然酸化により形成されたアルミナ（ＡＱｇｏｓ
）を除去できるのでシリコン薄膜（１３）との密着性を
一層向上できる。また、電極材料層（１１）がＡｆｆｉ
−Ｓｉであればこれらの工程は比較的簡単な工程で済
ませることができる。つまり、電極材料Ｊｆｆｉ（１１
）として使用するアルミ・シリコン（ＡＮ −Ｓｉ）形
成用のスパッタ装置に、アルミ・シリコン（１２−Ｓｉ
）とシリコン（Ｓｉ）との２つのターゲットを持たせ、
先ず八ρ−Ｓｉのターゲットで電極材料層（１１）を堆
積し、続いてシリコン（Ｓｉ）ターゲットだけに切換え
てシリコン薄膜（１３）を積層することにより、同一装
置内の１回の処理で積層構造にできる。Note that before depositing the silicon thin film (13), the electrode material layer (
By treating the surface of the electrode material layer (11) with an alkaline aqueous solution such as a positive resist developer, alumina (AQgos) formed by natural oxidation is formed on the surface of the electrode material layer (11).
) can be removed, further improving the adhesion with the silicon thin film (13). Further, the electrode material layer (11) is Affi
-Si, these steps can be completed with relatively simple steps. In other words, the electrode material Jffi (11
) to form aluminum silicon (AN-Si).
) and silicon (Si),
First, the electrode material layer (11) is deposited using a target of 8ρ-Si, and then the silicon thin film (13) is deposited by switching only to a silicon (Si) target, so that the electrode material layer (11) can be deposited in a single process in the same device. It can be made into a structure.
続いてシリコン薄膜（１３）の表面に有機シランの一種
であるＨＭＤＳ（ヘキサメチルジシラザン）を塗布し、
表面にポジ型レジスト層（１４）をスピンオン塗布する
。ＨＭＤＳはシリコン表面に吸着した水分に対して親水
性の基を配向し、疎水性の基を上側に配向して疎水性の
ホトレジストとの密着性を向上させるものである。前記
ホトレジストは、例えばＡＺ−２４００（商品名）やＰ
ＦＲ７７６０（商品名）等を利用し、４，０００ｒｐｍ
、６０秒で塗布し膜厚２．０〜４．０μｍに形成した。Next, HMDS (hexamethyldisilazane), which is a type of organic silane, is applied to the surface of the silicon thin film (13).
A positive resist layer (14) is spin-on applied to the surface. HMDS orients hydrophilic groups with respect to water adsorbed on the silicon surface, and orients hydrophobic groups upward to improve adhesion to hydrophobic photoresist. The photoresist is, for example, AZ-2400 (trade name) or P
Using FR7760 (product name) etc., 4,000 rpm
The coating was applied in 60 seconds to form a film with a thickness of 2.0 to 4.0 μm.
ソフトベークは、１００℃、数分間で行った。Soft baking was performed at 100°C for several minutes.
次にウェハをステッパ等の露光装置にセットし、所望の
パターンを描画したホトマスクによってレジスト層〈１
４）を露光する。露光はＤｅｅｐＵＶ（遠紫外線）を照
射した。露光後、アルカリ水溶液から成る現像液でレジ
スト層（１４）を現像し、１２０℃、数十分間のハード
ベークを行う。Next, the wafer is set in an exposure device such as a stepper, and a resist layer <1
4) Expose. Exposure was performed using Deep UV (far ultraviolet rays). After exposure, the resist layer (14) is developed with a developer consisting of an alkaline aqueous solution, and hard baked at 120° C. for several tens of minutes.
尚、露光時に電極材料層（１１〉の表面をシリコン薄膜
（１３）が覆っているので、その膜厚を適宜選択するこ
とによりＡ２表面の露光光の反射（ハレーション）防止
被膜として利用できる。膜厚は、露先光の波長に鑑みシ
リコン薄膜（１３）内で反射光が相殺されるような厚み
に設定しておけば良い。ハレーション防止被膜として利
用すれば、レジストパターンの線幅減少を防止できるの
で正確なレジストパターンを形成できる。Since the silicon thin film (13) covers the surface of the electrode material layer (11>) during exposure, it can be used as an anti-reflection (halation) film for the exposure light on the A2 surface by appropriately selecting the film thickness. The thickness should be set to such a value that the reflected light is canceled out within the silicon thin film (13) in consideration of the wavelength of the exposure light.If used as an anti-halation film, it will prevent line width reduction of the resist pattern. Therefore, accurate resist patterns can be formed.
そして第１図Ｂに示すように、先ずシリコン薄膜（１３
）を除去し続いて電極材料層（１１）を等方工・ノチン
グする。シリコン薄膜（１３）のエツチングはＣＤＥ（
ケミカルドライエッチ〜−）やＲＩＥ（リアクティブイ
オンエツチング）の完全異方性エツチングでレジストパ
ターンを忠実に再現する。その後、レジスト層（１４）
およびシリコン薄膜（１３）をマスクとして例えばリン
酸（ｕｓｐｏａ ） ：酢＃（Ｃ１，Ｃ００Ｈ）：硝酸
（ＨＮＯ，＞溶液でスプレーエツチングすることにより
、レジストパターンに対応したパターンの電極配線（１
５）を形成する。エツチングモードは等方性であるから
、膜厚方向への侵食が進むと同時に横方向への侵食も進
む。結果、電極配線（１５）の断面は側面が傾斜した台
形状となる。Then, as shown in FIG. 1B, first a silicon thin film (13
) is removed, and then the electrode material layer (11) is isotropically etched and notched. The silicon thin film (13) is etched using CDE (
Completely anisotropic etching such as chemical dry etching (--) or RIE (reactive ion etching) faithfully reproduces resist patterns. After that, the resist layer (14)
Then, by spray etching with a solution of, for example, phosphoric acid (uspoa): vinegar # (C1, C00H): nitric acid (HNO) using the silicon thin film (13) as a mask, the electrode wiring (1) is patterned in a pattern corresponding to the resist pattern.
5) Form. Since the etching mode is isotropic, the erosion progresses in the lateral direction as well as in the film thickness direction. As a result, the cross section of the electrode wiring (15) becomes trapezoidal with inclined sides.
そして最後に、レジスト層（１４）とシリコン薄膜（１
３）を順次除去して次のステップへと移行する。And finally, resist layer (14) and silicon thin film (1
3) are sequentially removed and the process moves to the next step.
レジスト層（１４）の除去は硝酸によるエツチング、シ
リコン薄膜（１３）の除去はＣＤＥ（ケミカルドライエ
ツチャー）で行った。次のステップとは、層間絶縁膜と
上層配線の形成や、パッシベーション被膜の形成等を指
す。The resist layer (14) was removed by etching with nitric acid, and the silicon thin film (13) was removed by CDE (chemical dry etcher). The next step refers to the formation of an interlayer insulating film and upper layer wiring, the formation of a passivation film, etc.
以上に説明した本発明の方法によれば、電極材料層（１
１）のアルミニウムとシリコン薄膜（１３〉のジノコン
とが良好な密着性を有するので、電極材料層（１１〉の
ウェットエツチング時にエツチング液が両者の界面に侵
入することが無く、従って電極配置（１５）の上部（ト
ップ）が部分的に欠落する“虫食い°”現象の発生を防
止できる。According to the method of the present invention explained above, the electrode material layer (1
Since the aluminum of 1) and the dinocon of the silicon thin film (13>) have good adhesion, the etching solution does not enter the interface between the two during wet etching of the electrode material layer (11>). ) can prevent the occurrence of the "moth-eaten °" phenomenon in which the top part of the product is partially missing.
（ト）発明の効果
以上に説明した如く、本発明によればシリコン薄膜（１
３）を設けることによって電極配線（１５）の“虫食い
′”不良を防止できるので、信頼性の高い電極配線（１
５）を形成できる利点を有する。(g) Effects of the invention As explained above, according to the present invention, the silicon thin film (1
3) can prevent "worm-eaten" defects in the electrode wiring (15), resulting in highly reliable electrode wiring (15).
5).
また、シリコン薄膜（１３）をハレーション防止被膜と
しても用いることにより、レジストの線幅減少をも防止
できる他、工程の簡略化を図れる。Further, by using the silicon thin film (13) as an antihalation coating, it is possible to prevent a decrease in the line width of the resist and also to simplify the process.
第１図Ａと第１図Ｂは本発明を説明するための断面図、
第２図Ａと第２図Ｂは従来例を説明するための断面図、
第３図は従来例を説明するための平面図である。
第１図Ａ
１４レジヅ１FIG. 1A and FIG. 1B are cross-sectional views for explaining the present invention,
FIG. 2A and FIG. 2B are cross-sectional views for explaining the conventional example,
FIG. 3 is a plan view for explaining a conventional example. Figure 1 A 14 Regizu 1
Claims (3)
薄膜を堆積する工程、 前記シリコン薄膜の表面にレジスト層を形成し、これを
露光、現像する工程、 前記レジスト層をマスクとして前記シリコン薄膜を除去
し、続いて前記電極材料層をウェットエッチングする工
程とを具備することを特徴とする半導体装置の製造方法
。(1) A step of depositing a silicon thin film on the surface of the electrode material layer to be patterned, a step of forming a resist layer on the surface of the silicon thin film, exposing and developing it, and removing the silicon thin film using the resist layer as a mask. and, subsequently, wet etching the electrode material layer.
を特徴とする半導体装置の製造方法。(2) A method for manufacturing a semiconductor device, wherein the electrode material layer is Al or Al-Si.
徴とする請求項第１項に記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the resist layer is a positive resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29832689A JPH03159126A (en) | 1989-11-16 | 1989-11-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29832689A JPH03159126A (en) | 1989-11-16 | 1989-11-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03159126A true JPH03159126A (en) | 1991-07-09 |
Family
ID=17858212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29832689A Pending JPH03159126A (en) | 1989-11-16 | 1989-11-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03159126A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008182198A (en) * | 2006-12-12 | 2008-08-07 | Asml Netherlands Bv | Method of manufacturing lithographic device, lithographic cell, and computer program |
-
1989
- 1989-11-16 JP JP29832689A patent/JPH03159126A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008182198A (en) * | 2006-12-12 | 2008-08-07 | Asml Netherlands Bv | Method of manufacturing lithographic device, lithographic cell, and computer program |
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