JPH03155640A - Manufacturing method of MOS type semiconductor device - Google Patents

Abstract

PURPOSE:To improve yield, electrical characteristics and reliability by forming the sidewall spacer of the gate electrode, etc., of a MOS transistor in the laminated structure of a silicon nitride film and a silicon oxide film and preventing the over-etching of a field oxide film and a gate oxide film when the spacer is shaped. CONSTITUTION:A silicon nitride film 27 is grown in a gas atmosphere containing SiH4 and NH3, and a silicon oxide film 17 acquired by vapor-phase reacting SiH4 and O2 at approximately 400 deg.C is laminated. A spacer 18 is formed on the sidewall of a gate electrode 14 through anisotropic etch-back by a reactive dry etcher containing C2F6 and CHF3 gas. The emission spectrum 337nm of N from the foundation silicon nitride film 27 is received and desired over-etch is conducted for the time of the reception in the detection of an end point at the time of the anisotropic etch-back of the silicon oxide film 17 at that time, but etch-back is performed positively because the silicon nitride film 27 is shaped onto the whole foundation surface while a selection ratio is taken to the silicon nitride film 27, thus preventing the etching of a field oxide film 12 and a gate oxide film 13 on a source and a drain.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a MOS type semiconductor device having an insulating film spacer formed on the side wall of a gate electrode by anisotropic etch-back.

[Conventional technology]

BACKGROUND ART In order to increase the integration and multifunctionality of MOS-LSIs and the like, advances are being made in multilayer wiring structures and miniaturization of transistors. M
In order to improve the hot carrier resistance characteristics associated with the miniaturization of OS transistors, LDD (LLight 1y-Doped-
Drain) and DDD (Double-Diffu
Semiconductor devices have been proposed that have a sed-drain (sed-drain) structure to alleviate the electric field at the drain.As shown in FIG. 15 in area
After forming a gate oxide film 13 of 0 to 200 people and adjusting the threshold voltage by ion implantation, about 4000A of Poly-St, which is thermally decomposed of 5tH4, is grown in a vapor phase, and the gate electrode 14 and wiring 30 are formed by photoetching. are formed at the same time. Next, source and drain low concentration impurity layers 15.1
After ion-implanting phosphorus or the like to about 1 to 5 x 10"cm-2 into 6, about 5000 people made a silicon oxide film 17 by reacting SiH4 and 02 at about 400°C (see Fig. 3).
a)) Next, anisotropic etching is performed using a reactive dry etcher containing a gas such as CF4, C2Fb or CHF to form a spacer 18 on the side wall of the gate electrode (FIG. 3(b)). . Next, arsenic is ion-implanted at a level of 1 to 8 x 10"am-' into the high concentration impurity layers 19 and 20 such as the source and drain, and after activation, Si is used as the first interlayer insulating film 21.
Silicon oxide film or P made by gas phase reaction of H, and 02
A SG (phosphor glass) film of about 6000A is laminated, and the coated glass 22 is spin-coded for planarization and annealed at a temperature of about 800°C. Next, after opening a contact hole, the sputtered A1 alloy is patterned to a thickness of about 0.6 μm to form the first metal wiring 23 (Fig. 3 (C)).
. Next, a vapor-grown silicon oxide film is deposited as a second interlayer insulating film 24, and the coated glass 25 is spin-coded for flattening and annealed at a temperature of about 400°C, followed by opening through holes. .A sputtered to a thickness of about 8 μm
1 alloy to form a second metal wiring 26 and a third metal wiring 26.
After that, a plasma-grown silicon nitride film or the like is laminated as a protective film, and a bonding pad is opened.

[Problem to be solved by the invention]

However, in the conventional technology, when the anisotropic etch-back is performed to form the spacer 18, the end point of the anisotropic etch-back is to filter the plasma emitted when the gate electrode 14 and the poly-Si of the wiring 30 are exposed through a filter that transmits a specific wavelength. For example, we are trying to determine the emission spectrum of SiF (442 nm) or F (685 nm) by determining the change in the received light intensity through the process, but the area of patterned Po1y-St is overwhelmingly smaller than the field oxide film, and the change in emission intensity is It is difficult to grasp and determine the end point. Also, the silicon oxide 11i at the bottom of the patterned Po1y-8i space
The film thickness of the field oxide film 17 is reduced by cusping during vapor phase growth, and when the Po1y-3L surface is exposed, the field oxide film 12 made of the same material as the spacer is largely overetched, and the source and drain regions of the active region are The gate oxide film on the surface of the silicon is also removed, and the silicon surface is hit and damaged. The same thing can be said even if we try to control it by fixed time etching. As a result, the causes of gate film breakdown and channel leakage of transistors, and field oxide film 1
2 becomes thinner by 2 to 2,500 people, and in addition to the increase in interlayer capacitance,
The feature size and aspect ratio of the side of the Po1y-8t wiring 30 on the field oxide film 12 become large, which impairs the flatness and coverage of wiring and interlayer films that cross over this, and reduces reliability due to voids 29, etc. There were many defects. However, the present invention solves such problems, and in particular, M
By preventing over-etching when forming sidewall spacers such as gate electrodes of oS transistors, the purpose is to ensure a stable supply of microscopic multifunctional semiconductor devices and to improve quality with reliability.

[Means to solve the problem]

The method for manufacturing an MO3 semiconductor device of the present invention includes at least the following steps:
A process of forming a gate film and a gate electrode, a process of forming a low concentration impurity layer such as a source and a drain, a process of stacking a silicon nitride film and a silicon oxide film by vapor phase growth, and an anisotropic etchback process to form a sidewall of the gate electrode. The method is characterized by comprising a step of forming a spacer made of the laminated film, and a step of forming a high concentration impurity layer such as a source and a drain.

〔Example〕

An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below.
This will be explained in detail using FIG.

Stage-MO8- with submicron rule multilayer wiring structure
When applied to LSI, for example, silicon substrate 1
1, a field oxide film 12 of approximately 550 OA was formed by selective oxidation, a gate oxide film 13 of approximately 180 Å was formed in the active region, and the threshold voltage was adjusted by ion implantation. about 400
Gate electrode 1 was formed by 0A vapor phase growth and photoetching.
4 and wiring 30 were formed at the same time. Next, using the gate electrode 14 and field oxide film 12 as a mask, apply approximately 2×10 13 phosphorus or the like to the low concentration impurity layers 15 and 16 of the source and drain.
Ions were implanted to the extent of cm-'.

Next, silicon nitride 1! in a gas atmosphere containing SiH4 and NH. [27 was grown to 800~12ooA, and then Si
A 5000A silicon oxide film 17 made by subjecting H4 and 02 to a gas phase reaction at about 400° C. was laminated (FIG. 1(a)). Next, spacers 18 were formed on the side walls of the gate electrode 14 by anisotropic etching back using a reactive dry etcher containing gases such as C2F and CHF (FIG. 3(b)). At this time, the end point of anisotropically etching back the silicon oxide 817 was detected by receiving the N emission spectrum of 337 nm from the underlying silicon nitride 11!27. silicon nitride film 27
Since etching is carried out reliably and a high selectivity can be achieved with respect to the silicon nitride JII 27, the field oxide film 12 and the gate oxide film 13 on the source and drain will not be etched. Next, 16
The silicon nitride film 27 was wet-etched by immersing it in phosphoric acid at 0 to 180° C. for about 15 minutes (Fig. 1 (C)).
.

Next, approximately 5×1015 cm-2 of arsenic was ion-implanted into the high-concentration impurity layers 19.20 of the source and drain, and the temperature was increased to 950°C.
After annealing, SiH4 is used as the first interlayer insulating film 21.
A silicon oxide film and a PSG film obtained by vapor-phase reaction of 02 and PH were laminated with a total thickness of about 6000 A, and the coated glass 22 was spin-coded for planarization and annealed at a temperature of about 800°C. Next, a contact hole is opened and the diameter is 0.6 μm.
The sputtered A1 alloy was patterned to a thickness of 1 to form the first metal wiring 23 (FIG. 1(C)). Next, approximately 6,000 silicon oxide films made of 5tH4 and 02 are deposited in a vapor phase as the second interlayer insulation@24, and coated glass 25 is spin-coded for planarization and annealed at a temperature of about 400°C. , a through hole was opened, and sputtered A1 alloy was buttered to a thickness of about 0.8 μm to form the second metal wiring 26 (FIG. 1(d)). After that, a silicon nitride film was plasma grown as a protective film. were laminated and a bonding pad was drilled.

In the semiconductor device manufactured in this manner, field oxidation II!
112 and the gate oxide film 13 on the source and drain are not etched, thereby eliminating damage to the MOS transistor and increasing the speed of the device. In addition, Po1y-3 on the field oxide film 12
The working size of the side of the i-wire 30 is also suppressed, improving the ease of handling, and eliminating voids in the interlayer insulating films 21, 24, resulting in improvements in yield, reliability, etc.

As another example, it was applied to the manufacture of a semiconductor device having metal silicide in self-alignment in impurity layers such as the gate electrode and the source and drain. For example, as shown in FIG. After forming the spacer 18 of the nitride film 27 and silicon oxide film 17 (FIG. 2(a)),
The gate oxide film 13 remaining on the surface of the impurity layers 19.20 such as the source and drain is removed with an HF aqueous solution, and titanium 28 is sputtered thereon (Fig. 2(b)). Thereafter, the film is heated at about 700°C using a halogen lamp. Nitrogen annealing is performed for 30 seconds to monosilicide the titanium 28 in contact with the impurity layer 19, 20 and the silicon surface of the gate electrode 14.
Titanium nitride was formed on the field oxide film 12 and the spacer 18 made of silicon oxide film, and this was immersed in a 2=1 mixture of hydrogen peroxide and ammonia water to remove only the titanium nitride, and then heated again with a halogen lamp at 800°C. After nitrogen annealing, the remaining monosilicide was made into titanium disilicide 31 having a sheet resistance of about 3 Ω/hole (FIG. 2(C)).

The spacer 19 is also removed to some extent by the HF etching at this time, but since the silicon nitride film 27 is present, the gate electrode 14, one impurity layer, and the silicide 31 on the surface of the 20 can be separated more reliably than before. As a result, we were able to dramatically improve yield.

In addition, the first and second interlayer insulating films 21 and 24 are
A vapor-phase grown silicon oxide film made by a plasma reaction of OS and 02 or a thermal reaction of TEOS and 03 was applied to the device, but because there is no cusp, it is flatter than a silicon oxide film made by a vapor-phase reaction of SiH4 and 02. I was able to improve my sexuality.

In addition, in the example, NchMO3-LSI with multilayer metal interconnection
However, single-layer metal wiring and 6MO3-LSI
In addition, the metal wiring is not limited to pure AI or an alloy single layer containing Cu%Si%PtSCo, etc., but also barrier metal and cap metal for preventing halation can be used as A1 alloy wiring. It can also be applied to a structure in which it is laminated above or below.

〔Effect of the invention〕

As described above, according to the present invention, the sidewall spacer such as the gate electrode of a MOS transistor has a laminated structure of a silicon nitride film and a silicon oxide film, and by preventing overetching of the field oxide film and the gate oxide film when forming the spacer, This improves yield, electrical characteristics, and reliability, and contributes to the stable supply of more integrated and multifunctional semiconductor devices.

[Brief explanation of the drawing]

Figures 1 (a) to (d) and Figures 2 (a) to (d) are
1 is a schematic cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention. FIGS. 3(a) to 3(d) are schematic cross-sectional views relating to a conventional method of manufacturing a semiconductor device. 11th...Silicon substrate 12...Field oxide film 13...Gate oxide film 14th...Gate electrode 15.16.Low concentration impurity layer 17...Silicon oxide film 18ΦΦFist spacer 19.20・High concentration impurity layer 21・・φ・First interlayer insulating film 22.25・Coated glass 23・・First metal wiring 24・・Second interlayer insulating film 26・・War・Second metal wiring 27φ φ ・ 28・ Competition 29・ ・ ・ 30・ Bone ・ 31 ・ ・ ・ Silicon nitride film titanium void wiring silicide or more

Claims (1)

[Claims] At least a step of forming a gate film and a gate electrode,
A step of forming a low concentration impurity layer such as a source and a drain,
A step of laminating a silicon nitride film and a silicon oxide film by vapor phase growth, a step of forming a spacer made of the laminated film on the side wall of the gate electrode by anisotropic etchback, a source,
1. A method for manufacturing a MOS type semiconductor device, comprising a step of forming a high concentration impurity layer such as a drain.