JPH03155206A - Oscillator circuit - Google Patents
Oscillator circuitInfo
- Publication number
- JPH03155206A JPH03155206A JP29552889A JP29552889A JPH03155206A JP H03155206 A JPH03155206 A JP H03155206A JP 29552889 A JP29552889 A JP 29552889A JP 29552889 A JP29552889 A JP 29552889A JP H03155206 A JPH03155206 A JP H03155206A
- Authority
- JP
- Japan
- Prior art keywords
- capacitance
- oscillation
- capacitor
- variable
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は通信分野などにおける高精度発振器の発振周波
数調整方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for adjusting the oscillation frequency of a high-precision oscillator in the communication field and the like.
従来の水晶発振回路の発振周波数調整は、発振の安定性
、調整の簡易の点から、第2図に示す様な、可変ドレイ
ン容量、又は可変ゲート容量によって行っていた。1は
水晶振動子、2は発振帰還抵抗、3は反転増幅器、4は
反転増幅器のゲート信号、5はドレイン信号、20はゲ
ート容量、21は可変ドレイン容量で、容量可変装置2
2によりドレイン容量21を変化させ、発振周波数の調
整を行う。The oscillation frequency adjustment of conventional crystal oscillation circuits has been carried out using variable drain capacitance or variable gate capacitance as shown in FIG. 2 from the viewpoint of oscillation stability and ease of adjustment. 1 is a crystal resonator, 2 is an oscillation feedback resistor, 3 is an inverting amplifier, 4 is a gate signal of the inverting amplifier, 5 is a drain signal, 20 is a gate capacitance, 21 is a variable drain capacitor, and a capacitance variable device 2
2, the drain capacitance 21 is changed to adjust the oscillation frequency.
通常の特性として、ドレイン容量の逆数に比例して発振
周波数は下がってゆき、−船釣な周波数可変範囲は要求
仕様として±50 [PPM]〜±100[PPM]が
必要とされる。As a normal characteristic, the oscillation frequency decreases in proportion to the reciprocal of the drain capacitance, and a reasonable frequency variable range of ±50 [PPM] to ±100 [PPM] is required as a required specification.
しかしながら、従来の方式では周波数可変範囲を広くと
る為にはドレイン容量(又はゲート容量)の可変範囲も
大きくせねばならなかった。However, in the conventional system, in order to widen the frequency variable range, the variable range of the drain capacitance (or gate capacitance) must also be widened.
その為
■可変容量の値が大きく部品として大型になり発振器の
小型軽量化が難かしい。Therefore, ■The value of the variable capacitance is large, making it a large component, making it difficult to make the oscillator smaller and lighter.
■ドレイン容量(又はゲート容量)が大きくなり過ぎる
と発振そのものが起こりにくくなり低い電圧(例えば電
池駆動)での動作が難しい。■If the drain capacitance (or gate capacitance) becomes too large, oscillation itself becomes difficult to occur, making it difficult to operate at low voltage (for example, battery-driven).
■ドレイン容量が大きくなりすぎると、反転増幅器の出
力充放電電流は
I a ” f aac ” ”D ’ c。■If the drain capacitance becomes too large, the output charging/discharging current of the inverting amplifier will be I a ``f aac '' ``D ' c.
とドレイン容量にほぼ比例する為、発振回路の消費電流
が増加してしまう
などの問題点を有していた。Since this is almost proportional to the drain capacitance, there have been problems such as an increase in the current consumption of the oscillation circuit.
本発明は上記問題点を克服する為、従来よりも少ない可
変容量値で、発振周波数調整範囲を広げ、さらに発振起
動性をあまり犠牲にせず、又ドレイン容量が増加したこ
とによる発振回路の動作電流を極力抑えるということを
目的としている。In order to overcome the above-mentioned problems, the present invention expands the oscillation frequency adjustment range with a smaller variable capacitance value than the conventional one, does not significantly sacrifice the oscillation start-up performance, and also increases the operating current of the oscillation circuit due to the increased drain capacitance. The aim is to suppress as much as possible.
本発明の水晶発振回路は、反転増幅器の入力側に接続さ
れた第1の容量と、出力側に接続された第2の容量を有
し、第1の容量と第2の容量を同時に変化させることに
より発振周波数の調整を行うことを特徴とする。The crystal oscillation circuit of the present invention has a first capacitor connected to the input side of an inverting amplifier and a second capacitor connected to the output side, and changes the first capacitance and the second capacitance simultaneously. It is characterized in that the oscillation frequency is adjusted by this.
〔実 施 例〕 第1図に本発明の水晶発振回路を示す。〔Example〕 FIG. 1 shows a crystal oscillation circuit of the present invention.
1は水晶振動子、2は帰還抵抗、3は反転増幅器、4は
反転増幅器のゲート信号、5は反転増幅器のドレイン信
号、6.7は各々可変ゲート容量、可変ドレイン容量、
で、容量可変装置9からの制御信号8により容量の鎮が
決められ、さらにゲート容量、ドレイン容量は同時に同
量づつ変化する。1 is a crystal oscillator, 2 is a feedback resistor, 3 is an inverting amplifier, 4 is a gate signal of the inverting amplifier, 5 is a drain signal of the inverting amplifier, 6 and 7 are variable gate capacitance, variable drain capacitance,
The capacitance level is determined by the control signal 8 from the capacitance variable device 9, and the gate capacitance and drain capacitance are changed simultaneously by the same amount.
第1図の細部について詳しく説明する。The details of FIG. 1 will be explained in detail.
第3図は本発明の特徴を最もよく表わす図で、容量変化
による周波数緩急特性である。ゲート容量の変化値を八
CG、ドレイン容量の変化値をΔCoとした時、周波数
の変化値Δ((lj位は[PPMIのオーダー)と容量
変化値の和△C(−ACG+ΔCo)との相関を示すの
が曲線25である。もしゲート容量を固定にして、ドレ
イン容量のみ可変とした発振回路の場合、容量変化値の
和はへ〇−へCDとなり、この時の周波数緩急特性曲線
は26となる。同じ△Cの値で比較すると本発明の発振
回路の方が、緩急特性が4〜5倍となっており、周波数
調整範囲が広くとれることを示している。逆に言えば従
来の容量可変方式に比べ容量の変化量ΔCを1/4〜1
15の少ない値で、従来必要とされていた周波数調整範
囲を得ることが可能となる。FIG. 3 is a diagram that best represents the characteristics of the present invention, and is a diagram showing the frequency fluctuation characteristics due to capacitance changes. When the gate capacitance change value is 8CG and the drain capacitance change value is ΔCo, the correlation between the frequency change value Δ((lj is on the order of [PPMI)] and the sum of the capacitance changes ΔC(-ACG+ΔCo) Curve 25 shows this.If the gate capacitance is fixed and only the drain capacitance is variable, the sum of the capacitance changes will be CD, and the frequency curve will be 26. When compared with the same value of △C, the oscillation circuit of the present invention has 4 to 5 times the slowing and fastening characteristics, indicating that the frequency adjustment range can be wider. The amount of change in capacitance ΔC is 1/4 to 1 compared to the variable capacitance method.
With a small value of 15, it is possible to obtain the frequency adjustment range that was conventionally required.
次に可変容量値が少なくて良いことの利点をいくつかで
掲げてみる。Next, let's list some of the advantages of having a small variable capacitance value.
第4図は水晶発振回路で一般的な特性であるドレイン容
量−発振消費電流特性の一例である。縦軸は消費電流増
加の割合を示し、ドレイン容量の変化量ΔCo =O[
PF]の時を0[%]とした相対値で表わしである。ゲ
ート容量の増加が消費電流に与える影響はドレイン容量
の増加に比べ極くわずかなので、本発明の発振回路を用
いれば消費電流の増加を抑えることが可能である。FIG. 4 shows an example of drain capacitance-oscillation current consumption characteristics, which are common characteristics in crystal oscillation circuits. The vertical axis shows the rate of increase in current consumption, and the amount of change in drain capacitance ΔCo = O[
It is expressed as a relative value with the time of PF] being 0 [%]. Since an increase in gate capacitance has a very small effect on current consumption compared to an increase in drain capacitance, it is possible to suppress an increase in current consumption by using the oscillation circuit of the present invention.
第5図はゲート容量とドレイン容量変化量の和−発振開
始電圧特性である。八C−0[PF]の時を0[%]と
した相対値で縦軸を示している。FIG. 5 shows the sum of gate capacitance and drain capacitance variation versus oscillation start voltage characteristic. The vertical axis is a relative value with 8C-0 [PF] being 0 [%].
これより、八〇は少ない程発振開始電圧を低く押えられ
発振起動性が良くなる。From this, the less 80, the lower the oscillation start voltage and the better the oscillation start-up performance.
本実施例では水晶振動子について述べてきたがセラミッ
ク振動子等の振動子でも同様の特性が得られ、本発明は
有効である。In this embodiment, a crystal resonator has been described, but similar characteristics can be obtained with a resonator such as a ceramic resonator, and the present invention is effective.
又、第1図の容量可変装置9の構成としては、−船釣に
はトリマコンデンサがあるが、電圧制御によるバリアプ
ルキャパシタ、等も適応可能である。Further, as for the configuration of the capacitance variable device 9 shown in FIG. 1, a trimmer capacitor is used for boat fishing, but a barrier pull capacitor using voltage control or the like is also applicable.
次に本発明を半導体集積装置上に形成した例を示す。Next, an example in which the present invention is formed on a semiconductor integrated device will be shown.
第6図はMOS型半導体集積装置におけるゲート・ドレ
イン容量同時可変方式による発振周波数調整回路である
。この中で最も特徴的な部分は、DO〜D3の4ビット
デジタル信号(信号57.58.59.60)によりN
型トランジスタをオンさせる回路と、cao−cciの
分割ゲート容量(70,71,72,73)と、CDo
”” Cl)3の分割ドレイン容量(74,75,76
,77)を備え、上記デジタル信号により、分割ゲート
容量と分割ドレイン容量を同時に同量づつ変化させてゆ
くことである。FIG. 6 shows an oscillation frequency adjustment circuit using a simultaneous variable gate/drain capacitance method in a MOS type semiconductor integrated device. The most characteristic part of this is that N
The circuit that turns on the type transistor, the divided gate capacitance (70, 71, 72, 73) of cao-cci, and the CDo
"" Cl) 3 divided drain capacitance (74, 75, 76
, 77), and the divided gate capacitance and the divided drain capacitance are simultaneously changed by the same amount by the digital signal.
今、CGO−CDO−1[PF]
Cat−C3l−2[PF]
CO2−CD2−4 [PF]
Ca1−Co3”8 [PF]
と容量値を設定しておくとゲート容ffi (CG )
、ドレイン容!(CD)の値はDO−D3により次の様
な関数となる。Now, if we set the capacitance value as CGO-CDO-1 [PF] Cat-C3l-2 [PF] CO2-CD2-4 [PF] Ca1-Co3”8 [PF], the gate capacitance ffi (CG)
, Drain Yong! The value of (CD) becomes the following function by DO-D3.
Ca =Do +2D1 +402+8Di [PF
lCD−Do + 2 D + + 4 D2 + 8
D3 [P F ]但し、DO〜D3は信号が“H
”の時1、信号が“Loの時0の値とする。Ca = Do +2D1 +402+8Di [PF
lCD-Do + 2 D + + 4 D2 + 8
D3 [P F ] However, the signal is “H” for DO to D3.
”, the value is 1, and when the signal is “Lo”, the value is 0.
従ってデジタル信号4ビツトによりCa、Coは1〜1
5[PF]まで1 [PF]で、同時に可変可能となる
。よって出力信号55には周波数調整されたサイン波形
が得られる。Therefore, with 4 bits of digital signal, Ca and Co are 1 to 1.
It is possible to change up to 1 [PF] up to 5 [PF] at the same time. Therefore, the output signal 55 has a frequency-adjusted sine waveform.
さらにゲート容量・ドレイン容量の値は同量づつでなく
ても良く、振動体の持つ特性に合わせて変えても良い。Further, the values of the gate capacitance and the drain capacitance do not have to be the same each, and may be changed according to the characteristics of the vibrating body.
−船釣にはドレイン容量を若干大きめにして、Co+−
1,2Cc+(i−0,1,2,3)程度にするとより
発振安定性は高まる。-For boat fishing, the drain capacity should be slightly larger, and Co+-
Oscillation stability is further improved when the value is set to about 1,2Cc+(i-0,1,2,3).
以上述べた様に、本発明の発振回路は、従来のドレイン
容量可変方式(又はゲート容量可変方式)に比べ、少な
い可変容量値で、周波数可変範囲を広く取ることができ
、高精度発振器としての特性が高まる。As described above, the oscillation circuit of the present invention can widen the frequency variable range with a smaller variable capacitance value than the conventional variable drain capacitance method (or variable gate capacitance method), and can be used as a high-precision oscillator. Characteristics increase.
又、可変容量値を少なくできるということは、次の様な
利点を生み出す。Furthermore, being able to reduce the variable capacitance value produces the following advantages.
まず発振消費電流の増加を抑え、発振器としての低パワ
ー化に役立つ。First, it suppresses the increase in oscillation current consumption, helping to reduce the power of the oscillator.
そして発振に必要な電源電圧も低くて済み、発振器とし
ての起動性が良くなり、電池などの低電圧駆動により適
した発振器となる。The power supply voltage required for oscillation is also low, and the start-up performance as an oscillator is improved, making the oscillator more suitable for low-voltage drive such as batteries.
さらに半導体集積化した際に、トータル容量が少なくて
済む為、発振回路の面積を小さくすることがてき、半導
体としてより集積度を上げることが可能となる。Furthermore, when integrated into a semiconductor, since the total capacitance is small, the area of the oscillation circuit can be reduced, and the degree of integration as a semiconductor can be increased.
第1図は本発明によるゲート・ドレイン容量同時可変方
式による発振回路を示す図。
第2図は従来のドレイン容量可変方式による発振回路を
示す図。
第3図は発振容量変化量に対する発振周波数変化の図。
第4図はドレイン容量変化回にχ・Iする発振消費電流
の図。
第5図は発振容量変化量に対する発振開始電圧の図。
第6図は半導体集積上に応用した本発明の発振回路図。
1・・・水晶振動子
2・・・発振帰還抵抗
3・・・反転増幅器
6・・・ゲート側可変容量
7・・・ドレイン側可変容量
8・・・ゲート容量及びドレイン容量可変制御信号
9・・・容量可変装置
以上
−20]
20
第
図
第
図
’ilQ
0
第
図FIG. 1 is a diagram showing an oscillation circuit using a simultaneous variable gate/drain capacitance method according to the present invention. FIG. 2 is a diagram showing an oscillation circuit using a conventional variable drain capacitance method. FIG. 3 is a diagram of the change in oscillation frequency with respect to the amount of change in oscillation capacitance. FIG. 4 is a diagram of the oscillation current consumption depending on χ·I when the drain capacitance changes. FIG. 5 is a diagram of oscillation start voltage with respect to the amount of change in oscillation capacitance. FIG. 6 is a diagram of an oscillation circuit of the present invention applied to a semiconductor integrated circuit. 1... Crystal resonator 2... Oscillation feedback resistor 3... Inverting amplifier 6... Gate side variable capacitor 7... Drain side variable capacitor 8... Gate capacitance and drain capacitance variable control signal 9.・Capacity variable device or more -20] 20 Figure Figure 'ilQ 0 Figure
Claims (1)
1の容量(コンデンサ)と、出力側に接続された第2の
容量を有し、第1の容量と第2の容量を同時に変化させ
ることにより発振周波数の調整を行うことを特徴とする
発振回路。In an oscillation circuit, having a first capacitor (capacitor) connected to the input side of an inverting amplifier and a second capacitor connected to the output side, and changing the first capacitance and the second capacitance simultaneously. An oscillation circuit characterized in that the oscillation frequency is adjusted by.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29552889A JPH03155206A (en) | 1989-11-14 | 1989-11-14 | Oscillator circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29552889A JPH03155206A (en) | 1989-11-14 | 1989-11-14 | Oscillator circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03155206A true JPH03155206A (en) | 1991-07-03 |
Family
ID=17821792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29552889A Pending JPH03155206A (en) | 1989-11-14 | 1989-11-14 | Oscillator circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03155206A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5602713A (en) * | 1994-05-31 | 1997-02-11 | Asahi Kasei Kogyo Kabushiki Kaisha | Electronic delay detonator |
US7009460B2 (en) * | 2004-07-21 | 2006-03-07 | Sony Ericsson Mobile Communications Ab | Method and apparatus for reducing the start time of a VCXO |
JP2012195974A (en) * | 2012-07-12 | 2012-10-11 | Asahi Kasei Electronics Co Ltd | Oscillator |
-
1989
- 1989-11-14 JP JP29552889A patent/JPH03155206A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5602713A (en) * | 1994-05-31 | 1997-02-11 | Asahi Kasei Kogyo Kabushiki Kaisha | Electronic delay detonator |
US7009460B2 (en) * | 2004-07-21 | 2006-03-07 | Sony Ericsson Mobile Communications Ab | Method and apparatus for reducing the start time of a VCXO |
JP2012195974A (en) * | 2012-07-12 | 2012-10-11 | Asahi Kasei Electronics Co Ltd | Oscillator |
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