JPH03149823A - Semiconductor device of multilayer interconnection structure - Google Patents
Semiconductor device of multilayer interconnection structureInfo
- Publication number
- JPH03149823A JPH03149823A JP1288005A JP28800589A JPH03149823A JP H03149823 A JPH03149823 A JP H03149823A JP 1288005 A JP1288005 A JP 1288005A JP 28800589 A JP28800589 A JP 28800589A JP H03149823 A JPH03149823 A JP H03149823A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- copper
- multilayer
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000007769 metal material Substances 0.000 claims abstract description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052802 copper Inorganic materials 0.000 claims abstract description 15
- 239000010949 copper Substances 0.000 claims abstract description 15
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 8
- 239000000956 alloy Substances 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 230000008018 melting Effects 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 230000001902 propagating effect Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 17
- 238000009792 diffusion process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的Ｊ
（産業上の利用分野）
この発明は多層配線構造の半導体装置に係り、特にそれ
ぞれが金属材料を用いて構成された二層以上の配線層を
有する半導体装置に関する。[Detailed Description of the Invention] [Objective of the Invention J (Industrial Field of Application) This invention relates to a semiconductor device having a multilayer wiring structure, and particularly to a semiconductor device having two or more wiring layers each made of a metal material. Related to semiconductor devices.
（従来の技術）
ゲートアレイやＣＰＵ （中央演算処理ユニット）等、
近年のＬＳＩ（大規模集積回路）では、集積度を上げる
ために二層以上の配線が用いられている。ＬＳＩで用い
られる配線は、素子に電力を供給するための電源線と、
信号を伝搬するための信号線とに分けられる。例えば、
第３図に示すように、ＰチャネルのＭＯＳＦＥＴ３１と
ＮチャネルのＭＯＳＦＥＴ３２とからなるＣＭＯＳイン
バータが設けられたＣＭＯＳ−ＬＳＩ （ＣＭＯＳ型集
積回路）において、図中、実線の太線で示す配線が電源
線３３であり、破線の太線で示す配線が信号線３４であ
る。上記電源線３３には直流電圧が印加され、直流電流
が流れているか、素子のオン、オフに伴い電流が断続す
るような直流のパルス電流が流れており、一般に電源線
には一定の方向にのみに電流が流れている。これに対し
て信号線３４、特にＣＭＯＳ−ＬＳ Ｉの信号線には、
容量性負荷に対する充放電電流である双方向のパルス電
流が流れている。(Conventional technology) Gate arrays, CPUs (central processing units), etc.
In recent LSIs (Large Scale Integrated Circuits), two or more layers of wiring are used to increase the degree of integration. The wiring used in LSI includes a power line for supplying power to the elements,
It is divided into signal lines for transmitting signals. for example,
As shown in FIG. 3, in a CMOS-LSI (CMOS integrated circuit) equipped with a CMOS inverter consisting of a P-channel MOSFET 31 and an N-channel MOSFET 32, the wiring shown by the solid thick line in the diagram is the power supply line 33. The wiring indicated by the thick broken line is the signal line 34. A DC voltage is applied to the power line 33, and either a DC current is flowing, or a DC pulse current is flowing intermittently as the element turns on and off, and generally the power line flows in a fixed direction. Current is flowing only through it. On the other hand, the signal line 34, especially the CMOS-LSI signal line,
A bidirectional pulsed current, which is a charging/discharging current for a capacitive load, is flowing.
従来の多層配線構造の半導体装置では、多層配線に用い
る金属材料はアルミニウム又はその合金のみであり、多
層配線を用いる場合のレイアウトにおいても特に電源線
と信号線とを区別していなかった。In a conventional semiconductor device having a multilayer wiring structure, the metal material used for the multilayer wiring is only aluminum or its alloy, and even in the layout when using the multilayer wiring, power lines and signal lines are not particularly distinguished.
（発明が解決しようとする課！ｉ）
ところで、半導体装置において、配線に流すことができ
る最大電流はエレクトロマイグレーションと呼ばれる磨
耗不良に左右され、通常、この規格値は直流電流を配線
に流す試験によって決定されており、この値は例えば１
ｘ １０ （Ａ／ｃｄ）程度である。そして、素子
に電力を供給するために使用される電源線には比較的大
きな電流が流れるため、従来では電源線の幅をできるだ
け太くしている。しかしながら、素子が微細化されるに
つれ、電源線において直流電流で決められた規格値を満
足させることが困難になってきた。−さらに、従来では
、内部の素子や配線が微細化されてもチップサイズ自体
の大きさが変わらないこと、すなわち電源線の長さにほ
とんど変化がないこと、、また電源電圧自体が素子の微
細化につれて小さくなっていくため、電源線における電
圧降下による素子の誤動作が大きな問題となってきてい
る。(The problem that the invention aims to solve! i) By the way, in semiconductor devices, the maximum current that can be passed through the wiring is affected by a wear failure called electromigration, and this standard value is usually determined by a test in which a direct current is passed through the wiring. For example, this value is 1
x 10 (A/cd). Since a relatively large current flows through the power supply line used to supply power to the element, conventionally the width of the power supply line is made as wide as possible. However, as elements become finer, it has become difficult to satisfy the standard value determined for DC current in power supply lines. -Furthermore, in the past, even if the internal elements and wiring were miniaturized, the chip size itself did not change, that is, the length of the power supply line did not change much, and the power supply voltage itself was As devices become smaller and smaller, malfunctions of devices due to voltage drops in power supply lines have become a major problem.
一方、従来から金属材料のエレクトロマイグレーション
耐性と融点については相関関係があることが良く知られ
ているが、配線材料としてタングステンのような高融点
金属材料を用いるとすると、信号線の場合は、集積回路
の微細化につれて１つのスイッチング素子に対する信号
線の長さも短くなる傾向にあり、配線抵抗による信号伝
搬遅れ時間はほとんど問題にはならない。しかし、電源
線の場合には、その抵抗がアルミニウムに比べて数桁高
く、前記の電圧降下による動作不良が間通となり、電源
線に用いることは困難である。On the other hand, it has long been well known that there is a correlation between the electromigration resistance and melting point of metal materials, but if a high melting point metal material such as tungsten is used as a wiring material, in the case of signal lines, As circuits become finer, the length of a signal line for one switching element tends to become shorter, and signal propagation delay time due to wiring resistance hardly becomes a problem. However, in the case of power supply lines, its resistance is several orders of magnitude higher than that of aluminum, and malfunctions due to the voltage drop described above are common, making it difficult to use as power supply lines.
この発明は上記のような事情を考慮してなされたもので
あり、その目的は、高信頼性を有する多層配線構造の半
導体装置を提供することにある。The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a highly reliable semiconductor device having a multilayer wiring structure.
［発明の構成］ −
（課題を解決するための手段）
この発明の多層配線構造の半導体装置は、各スイッチン
グ素子に電力を供給するための第１配線と、スイッチン
グ素子相互間で信号を伝搬するための第２配線とを互い
に異なる金属材料を用いて構成したことを特徴とする特
＊作用）
この発明によれば、各スイッチング素子に電力を供給す
るための第１配線と、スイッチング素子相互間で信号を
伝搬するための第２配線層とを異なる金属材料を用いて
構成する。つまり、第１配線には抵抗″率が小さく、か
つ融点が高い金属材料を用いることにより、第１配線の
エレクトロマイグレーション耐性の向上と電圧降下の低
減とを図ることができる。[Structure of the Invention] - (Means for Solving the Problems) A semiconductor device with a multilayer wiring structure of the present invention includes a first wiring for supplying power to each switching element and a signal propagating between the switching elements. According to the present invention, the first wiring for supplying power to each switching element and the second wiring for supplying power to each switching element are constructed using different metal materials. The second wiring layer and the second wiring layer for transmitting signals are formed using different metal materials. That is, by using a metal material with a low resistivity and a high melting point for the first wiring, it is possible to improve the electromigration resistance of the first wiring and reduce the voltage drop.
（実施例）
以下、図面を参照してこの発明を実施例により説明する
。(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.
第１図はこの発明を、Ｐチャネル及びＮチャネルのＭＯ
ＳＦＥＴからなり、前記第１図に示すようなＣＭＯＳイ
ンバータが設けられたＣＭＯＳ−ＬＳＩに実施した場合
の素子構造を示す断面図である。FIG. 1 shows the present invention in a P-channel and N-channel MO
FIG. 2 is a cross-sectional view showing an element structure when implemented in a CMOS-LSI consisting of SFETs and provided with a CMOS inverter as shown in FIG. 1.
図において、１１はＮ型のシリコン半導体基板、１２は
素子分離を行うフィールド酸化膜、１３はＰ型のウェル
領域、１４．１５はＰチャネルＭＯＳＦＥＴのソース、
ドレイン領域となるＰ＋型拡散領域、１６、１７はＮチ
ャネルＭＯＳＦＥＴのソース、ドレイン領域となるＰ＋
型拡散領域、１８．１９は多結晶シリコン層からなり、
Ｐチャネル及びＮチャネルＭＯＳＦＥＴのゲート電極と
なる第１配線、２０はＰチャネルＭＯＳＦＥＴのドレイ
ン領域であるＰ＋型拡散領域１５とＮチャネルＭＯＳＦ
ＥＴのドレイン領域であるＰ＋型拡散領域１４とを接続
し、第１層目の金属材料を用いて構成された第２配線、
２１、２２はそれぞれＰチャネルＭＯＳＦＥＴのソース
領域であるＰ＋型拡散領域１４及びＮチャネルＭＯＳＦ
ＥＴのソース領域であるＰ＋型拡散領域１４それぞれに
接続され、第２層目の金属材料を用いて構成された第３
配線であり、２３及び２４はそれぞれは層間絶縁膜であ
る。In the figure, 11 is an N-type silicon semiconductor substrate, 12 is a field oxide film for element isolation, 13 is a P-type well region, 14.15 is a source of a P-channel MOSFET,
P+ type diffusion regions that will become the drain region, 16 and 17 are P+ type diffusion regions that will become the source and drain regions of the N-channel MOSFET.
The type diffusion region, 18.19, consists of a polycrystalline silicon layer;
The first wiring becomes the gate electrode of the P-channel and N-channel MOSFETs, 20 is the P+ type diffusion region 15 which is the drain region of the P-channel MOSFET, and the N-channel MOSFET.
a second wiring connected to the P+ type diffusion region 14, which is the drain region of the ET, and configured using the first layer metal material;
21 and 22 are a P+ type diffusion region 14 and an N channel MOSF, which are source regions of a P channel MOSFET, respectively.
A third layer is connected to each of the P+ type diffusion regions 14, which are the source regions of the ET, and is constructed using the metal material of the second layer.
These are wirings, and 23 and 24 are interlayer insulating films, respectively.
上記第２配線２０は、図示しない他のＣＭＯＳインバー
タ等、ＣＭＯＳゲートとの間で相互に信号を伝搬するた
めの信号線として使用されるものであり、この第２配線
２０は従来と同様にアルミニウム、又はアルミニウムに
シリコン、銅等を添加した合金を用いて構成されている
。これに対して、第３配！１２１、２２はこのＣＭＯＳ
インバータに電源電圧及び接地電圧をそれぞれ供給する
ための電源線として使用されるものであり、この画策３
配線２１、２２は銅を用いて構成されている。The second wiring 20 is used as a signal line to mutually propagate signals to and from a CMOS gate such as another CMOS inverter (not shown), and the second wiring 20 is made of aluminum as in the conventional case. , or an alloy of aluminum to which silicon, copper, etc. are added. On the other hand, 3rd place! 121 and 22 are this CMOS
It is used as a power line to supply power supply voltage and ground voltage to the inverter, and this plan 3
The wirings 21 and 22 are made of copper.
すなわち、上記実施例装置では、電源線を銅からなる第
２層目の金属材料を用いて構成し、信号線はアルミニウ
ム、又はアルミニウムにシリコン、銅等を添加した合金
からなる第１層目の金属材料を用いて構成したものであ
る。That is, in the above embodiment device, the power supply line is constructed using a second layer of metal material made of copper, and the signal wire is constructed using a first layer of metal material made of aluminum or an alloy of aluminum with silicon, copper, etc. It is constructed using a metal material.
ところで、多層配線を用いたＬＳＩを実現する場合、各
配線層の下の絶縁膜を平坦化する必要があることから、
一般に下層の配線層の方が薄膜化、微細化に適している
。従って、第２配！１２０は、配線の抵抗による信号の
遅延があまり問題にならず、その配線に流れる電流が双
方向のパルス電流であるためにエレクトロマイグレーシ
ョン耐性に関してはあまり問題にならない信号線として
用いることができる。このため、このＭ２配線２０は、
十分に薄膜化でき、加工限界で決まる最小寸法で形成す
ることかできる。By the way, when realizing an LSI using multilayer wiring, it is necessary to flatten the insulating film under each wiring layer.
Generally, the lower wiring layer is more suitable for thinning and miniaturization. Therefore, second place! 120 can be used as a signal line in which signal delay due to wiring resistance does not pose much of a problem, and since the current flowing through the wiring is a bidirectional pulse current, electromigration resistance does not pose much of a problem. Therefore, this M2 wiring 20 is
It can be made sufficiently thin and can be formed with minimum dimensions determined by processing limits.
これに対し、電源線はエレクトロマイグレーション耐性
が高い、すなわち融点の高い銅を使用して構成している
ため、直流電流のエレクトロマイグレーションに十分耐
え得ることができる。しかも、抵抗率が低い銅を用いて
構成されているので、電源線における電圧降下が少なく
、素子の誤動作を防止することができる。On the other hand, since the power supply line is made of copper having high electromigration resistance, that is, a high melting point, it can sufficiently withstand direct current electromigration. Moreover, since it is constructed using copper with low resistivity, there is little voltage drop in the power supply line, and malfunction of the element can be prevented.
第３図は配線に直流電流を流したときと、交流パルス電
流を流したときのエレクトロマイグレーション耐性を比
較したものであり、横軸は経過時間（時間）を、縦軸は
試験する配線４０本のうち断線せずに残っている配線の
数（本）をそれぞれ示している。なお、比較条件は温度
が共に２５０℃、電流密度が共に２．Ｑｘ１０ Ａ／ｃ
ｍ２であり、交流パルス電流の繰り返し周波数は１ＫＨ
ｚである。図示のように、交流パルス電流を流した配線
の特性Ａは、直流電流を流した配線の特性Ｂに比べて大
幅にエレクトロマイグレーションによる断線が少なくな
っている。このため、交流パルス電流が流れる上記第２
配線２０は、エレクトロマイグレーション耐性について
ほんど考慮する必要がなく、従来と同様にアルミニウム
、又はアルミニウムにシリコン、銅等を添加した合金か
らなる金属材料を用いて、十分に薄膜化され、かつ最小
寸法の配線を形成ができる。Figure 3 compares the electromigration resistance when DC current is passed through the wiring and when AC pulse current is passed through the wiring, where the horizontal axis represents the elapsed time (hours) and the vertical axis represents the 40 wirings to be tested. The number of wires (wires) remaining without disconnection is shown. The comparison conditions were a temperature of 250°C and a current density of 2. Qx10 A/c
m2, and the repetition frequency of the AC pulse current is 1KH.
It is z. As shown in the figure, the characteristic A of the wiring in which an alternating current pulse current is passed has significantly fewer disconnections due to electromigration compared to the characteristic B of the wiring in which a direct current is passed. Therefore, the second
The wiring 20 does not need to take into account electromigration resistance, and as in the past, it is made of a metal material made of aluminum or an alloy of aluminum with silicon, copper, etc., and is made sufficiently thin and has the minimum dimensions. wiring can be formed.
なお、この発明は上記実施例に限定されるものではなく
、種々の変形が可能であることはいうまでもない。例え
ば、上記実施例では、電源線として使用される第３配線
２１、２２を銅により構成する場合について説明したが
、これは銅の他に、融点が高くエレクトロマイグレーシ
ョン耐性が高く、かつ抵抗率が低い金属材料、例えば金
、銀又は金、銀、銅等を主成分とした合金を用いて構成
することもできる。It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications are possible. For example, in the above embodiment, the case where the third wirings 21 and 22 used as power supply lines are made of copper has been described. It can also be constructed using a low-metallic material such as gold, silver, or an alloy containing gold, silver, copper, or the like as a main component.
さらに、上記実施例では、第２層目の金属材料を用いて
電源線を構成し、第１層目の金属材料を用いて信号線を
構成する場合について説明したが、これは第１層目の金
属材料を用いて電源線を構成し、第２層目の金属材料を
用いて信号線を構成するようにしてもよい。なお、この
場合も、電源線は融点が高くエレクトロマイグレーショ
ン耐性が高く、抵抗率が低い金属材料を用いることはも
ちろんである。Furthermore, in the above embodiment, a case was explained in which the power supply line is configured using the second layer metal material and the signal line is configured using the first layer metal material. The power line may be configured using a metal material of the second layer, and the signal line may be configured using a second layer metal material. In this case as well, it goes without saying that the power supply line should be made of a metal material that has a high melting point, high electromigration resistance, and low resistivity.
また、この発明は上記した２層配線構造の半導体装置に
限らず、これ以上の配ＳａＷを有する半導体装置や、Ｃ
ＭＯＳ半導体装置以外のものにも実施が可能であること
はいうまでもない。Further, the present invention is not limited to the semiconductor device with the above-mentioned two-layer wiring structure, but also applies to semiconductor devices having a wiring structure of more than 100% SaW, and C
It goes without saying that the present invention can be implemented in devices other than MOS semiconductor devices.
［発明の効果］
以上説明したようにこの発明によれば、電源線を銅等か
らなり融点が高くかつ抵抗率が低い金属材料を用いて構
成するようにしたので、高信頼性を有する多層配線構造
の半導体装置を提供することができる。[Effects of the Invention] As explained above, according to the present invention, the power supply line is constructed using a metal material such as copper, which has a high melting point and low resistivity, so that multilayer wiring with high reliability can be achieved. A semiconductor device having the structure can be provided.
第１図はこの発明の一実施例装置の構成を示す断面図、
第２図はこの発明を説明するための特性図、第３図はＣ
ＭＯＳ−ＬＳＩの回路図である。
１１・・・Ｎ型のシリコン半導体基板、１２・・・フィ
ールド酸化膜、１３・・・Ｐ型のウェル領域、１４．１
５−・・Ｐ＋型拡散領域、１６．１フー・・Ｐ＋型拡散
領域、１８．１９・・・第１配線、２０・・・第２配線
、２１、２２・・・第３配線、２３゜２４・・・層間絶
縁膜。FIG. 1 is a sectional view showing the configuration of an apparatus according to an embodiment of the present invention;
Figure 2 is a characteristic diagram for explaining this invention, Figure 3 is C
It is a circuit diagram of MOS-LSI. 11... N-type silicon semiconductor substrate, 12... Field oxide film, 13... P-type well region, 14.1
5-...P+ type diffusion region, 16.1 Fu...P+ type diffusion region, 18.19...first wiring, 20...second wiring, 21, 22...third wiring, 23° 24...Interlayer insulating film.
Claims (6)
イッチング素子を多層の配線を用いて接続するようにし
た多層配線構造の半導体装置において、 上記各スイッチング素子に電力を供給するための第１配
線と、上記スイッチング素子相互間で信号を伝搬するた
めの第２配線とを互いに異なる金属材料を用いて構成し
たことを特徴とする多層配線構造の半導体装置。(1) In a semiconductor device having a multilayer wiring structure in which a plurality of switching elements are formed and these switching elements are connected using multilayer wiring, a first wiring for supplying power to each of the switching elements; A semiconductor device having a multilayer wiring structure, characterized in that the second wiring for propagating signals between the switching elements is constructed using different metal materials.
の配線で構成されている請求項１記載の多層配線構造の
半導体装置。(2) A semiconductor device having a multilayer wiring structure according to claim 1, wherein the first wiring and the second wiring are formed of wiring in different layers.
られている請求項１記載の多層配線構造の半導体装置。(3) A semiconductor device having a multilayer wiring structure according to claim 1, wherein the first wiring is provided in a layer above the second wiring.
第２配線を構成する金属材料のそれよりも低くされてい
る請求項１記載の多層配線構造の半導体装置。(4) A semiconductor device having a multilayer wiring structure according to claim 1, wherein the resistivity of the metal material forming the first wiring is lower than that of the metal material forming the second wiring.
２配線を構成する金属材料のそれよりも高くされている
請求項１記載の多層配線構造の半導体装置。(5) A semiconductor device having a multilayer wiring structure according to claim 1, wherein the melting point of the metal material forming the first wiring is higher than that of the metal material forming the second wiring.
にシリコン及び銅を添加した合金を用いて構成され、記
第１配線が銅、金、銀のいずれかもしくは銅、金、銀の
いずれかを主成分とした合金を用いて構成されている請
求項１記載の多層配線構造の半導体装置。(6) The second wiring is made of aluminum or an alloy of aluminum with silicon and copper added, and the first wiring is made of copper, gold, or silver, or mainly of copper, gold, or silver. 2. A semiconductor device with a multilayer wiring structure according to claim 1, which is constructed using an alloy as a component.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1288005A JPH03149823A (en) | 1989-11-07 | 1989-11-07 | Semiconductor device of multilayer interconnection structure |
| KR1019900017929A KR930009019B1 (en) | 1989-11-07 | 1990-11-07 | Semiconductor device of multilayer interconnection structure |
| US08/096,844 US5365110A (en) | 1989-11-07 | 1993-07-26 | Semiconductor device with multi-layered wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1288005A JPH03149823A (en) | 1989-11-07 | 1989-11-07 | Semiconductor device of multilayer interconnection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03149823A true JPH03149823A (en) | 1991-06-26 |
Family
ID=17724577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1288005A Pending JPH03149823A (en) | 1989-11-07 | 1989-11-07 | Semiconductor device of multilayer interconnection structure |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH03149823A (en) |
| KR (1) | KR930009019B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6489689B2 (en) | 2000-05-29 | 2002-12-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5488778A (en) * | 1977-12-26 | 1979-07-14 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of fabricating complementary mos transistor |
| JPS62118540A (en) * | 1985-11-18 | 1987-05-29 | Nec Corp | Semiconductor integrated circuit |
| JPS62237747A (en) * | 1986-04-08 | 1987-10-17 | Nec Corp | Semiconductor integrated circuit |
-
1989
- 1989-11-07 JP JP1288005A patent/JPH03149823A/en active Pending
-
1990
- 1990-11-07 KR KR1019900017929A patent/KR930009019B1/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5488778A (en) * | 1977-12-26 | 1979-07-14 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of fabricating complementary mos transistor |
| JPS62118540A (en) * | 1985-11-18 | 1987-05-29 | Nec Corp | Semiconductor integrated circuit |
| JPS62237747A (en) * | 1986-04-08 | 1987-10-17 | Nec Corp | Semiconductor integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6489689B2 (en) | 2000-05-29 | 2002-12-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR910010692A (en) | 1991-06-29 |
| KR930009019B1 (en) | 1993-09-18 |
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