JPH03148894A - hybrid integrated circuit - Google Patents
hybrid integrated circuitInfo
- Publication number
- JPH03148894A JPH03148894A JP28811389A JP28811389A JPH03148894A JP H03148894 A JPH03148894 A JP H03148894A JP 28811389 A JP28811389 A JP 28811389A JP 28811389 A JP28811389 A JP 28811389A JP H03148894 A JPH03148894 A JP H03148894A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- wiring layer
- layer
- film wiring
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
混成集積回路の構造に関し、
混成集積回路の銅薄膜配線層を高価な金に代えて、安価
な金属からなる多層薄膜配線層にすることによって、混
成集積回路全体の価格を低減することを目的とし、
基板上に少なくとも銅薄膜配線層が形成され、前記銅薄
膜配線層とチップ部品の電極端子部とが導電性接着材層
により接着され、前記銅薄膜配線層とＩＣベアチップの
電極端子部との間、および前記銅薄膜配線層とリードフ
レーム内端子との間がワイヤボンディングにより接続さ
れてなる混成集積回路において、前記銅薄膜配線層が少
なくとも銅薄膜配線層と、銅薄膜バリヤ層と、
アルミニウム薄膜配線層の積層膜からなり、前記銅薄膜
配線層の露出部とチップ部品の電極端子部とを導電性接
着材層により接着接続し、前記アルミニウム薄膜配線層
のボンディングパッドとＩＣベアチップの電極端子部と
の間、および前記アルミニウム薄膜配線層のボンディン
グパッドとリードフレーム内端子との間をワイヤボンデ
ィングにより接続して混成集積回路を構成する。
〔崖業上の利用分野〕
本発明は混成集積回路、と（に、薄膜金属導体配線層を
有する混成集積回路または薄膜／厚膜混成導体配線層を
有する混成集積回路の薄膜金属導体配線層の構成の改良
に関する。
近年、混成集積回路の集積度が増加し大規模化するに従
い、それに使用する基板も大形化する傾向がますます強
くなってきた。
それに伴い、これに使用する導体配線パターンを構成す
る材料の価格も混成集積回路の全体の価格を押し上げる
要因となっている。とくに、チップ部品とＩＣベアチッ
プを搭載する薄膜または薄膜／厚膜混成集積回路におい
ては、通常金（Ａｕ）薄膜配線層を用いるために価格へ
の影響が大きく、価格低減のために新規な銅薄膜配線層
による混成集積回路の開発が求められていた。
〔従来の技術〕
第３図は従来の混成集積回路の例を示す断面図で、薄膜
／厚膜混成集積回路の場合の部分的断面である。
図中、■はセラミック基板、８は基板ｌ上に印刷配線さ
れた厚膜導体層、９は絶縁層で厚膜回路部分とその上に
形成される薄膜回路部分を分離するためのものである。
２００は銅薄膜配線層で。
たとえば、ＮｉＣｒの銅薄膜密着層２０１と金（八〇）
蒲謳
膜配線層２０２から構成れている。３は抵抗あるいはコ
ンデンサなどのチップ部品、４は半導体ベースのをＣベ
アチップ（外装されていない裸のＩＣチップ）である。
５は導電性接着材層で、たとえば、銀ペーストであり、
金（Ａｕ）薄膜配線層上チップ部品３の電極端子部との
間を接着固定して電気的に接続する。また、同時に導電
性接着材層５は【Ｃベアチップ４を基板ｌ上に、たとえ
ば、金（Ａｕ） 薄膜配線層２０２の一部に設けた所定
ランドを介して搭載固定するためにも用いられる。
６はリードフレームの内端子で、金（＾ｕ）Ｆｌ膜配線
層２０２のボンディングパッドとの間をワイヤフ。
たとえば、金（Ａｕ）線により接続される。そのほかに
、ワイヤフはＩＣベアチップ４の電極端子部と金（＾ｕ
）Ｆｌ膜配線層２０２のボンディングパッドとの間を電
気的に接続する。
すなわち、このような混成集積回路では銅薄膜配線層２
００と、搭載部品、たとえば、チップ部品３あるいはＩ
Ｃベアチップ４との接続はワイヤボンディングおよび導
電性接着材という全く異なる接続技術を用いて行われて
いる。
銅薄膜配線層２００の接続露出層、すなわち、金（Ａｕ
）薄膜配線層２０２のボンディングパッドのＡｕ露出面
はその両方を容易に実現できることから広く使用されて
きた。
〔発明が解決しようとする課題〕
しかし、上記従来例において用いる金（Ａ（１）Ｔｅｌ
膜配線層は極めて高価であり、混成集積回路の価格も高
くなるという問題がある。また、より低価格で資源的に
も豊富な金属、たとえば、アルミニウム（＾ｆｆｉ）
ｔｌ膜を使用することが考えられるが、この場合にはワ
イヤボンディングは金（＾ｕ）１１膜と同様に可能であ
るが、導電性接着材層による接続での接続抵抗は金（Ａ
ｕ）薄膜の場合２０ｍΩ程度であるのに、一方、アルミ
ニウム（Ａ ｆ ）薄膜に対しては１．５Ω以上と約２
桁も大きく、製品性能上使用することができないといっ
た問題があり、それらの解決が求められていた。
〔課題を解決するための手段〕
上記の課題は、基板ｌ上に少なくとも銅薄膜配線層２が
形成され、前記銅薄膜配線層２とチップ部品３の電極端
子部とが導電性接着材層５により接着され、前記銅薄膜
配線層２とＩＣベアチップ４の電極端子部との間、およ
び前記銅薄膜配線層２とリードフレーム内端子６との間
がワイヤボンディングにより接続されてなる混成集積回
路において、前記銅薄膜配線層２が少なくとも銅薄膜配
線層２２と、銅薄膜バリヤ層２３と、アルミニウム薄膜
配線層２４の積層膜からなり、前記銅薄膜配線層２２の
露出部とチップ部品３の電極端子部とを導電性接着材層
５により接着接続し、前記アルミニウム薄膜配線層２４
のボンディングパッドとＩＣベアチップ４の電極端子部
との間、および前記アルミニウム薄膜配線層２４のボン
ディングパッドとリードフレーム内端子６との間をワイ
ヤボンディングにより接続して混成集積回路を構成する
ことによって解決することができる。
〔作用〕
本発明の混成集積回路の銅薄膜配線層２は、金（＾Ｕ）
を全（使用せず、少なくとも銅薄膜配線層２２と、銅薄
膜バリヤ層２３と、アルミニウム薄膜配線１１２４の積
層膜から構成されている。したがうて、ワイヤボンディ
ングする配線層部分にはアルミニウム薄膜配線１１２４
の露出部であるボンディングパッドを用い、アルミニウ
ム薄膜とは低接触抵抗で接続できない導電性接着材層に
より接続する配線層部分には銅薄膜配線層２２の露出部
を用いることにより、実質的に従来の金（Ａｕ） ＊膜
配線層の場合と同様に、チップ部品３やＩＣベアチップ
４を搭載接続することができる。なお、銅薄膜配線層２
２とアルミニウム薄膜配線層２４の間に、必要に応じて
両金属の拡散を防止するために、クロム（Ｃｒ）などの
銅薄膜バリヤ層を設けておけばよい。
〔実施例〕
第１図は本発明実施例を示す斜視図である。図中、２４
″はアルミニウム薄膜配線層のボンディングパッドで、
たとえば、ＩＣベアチップ４の電極端子部との間および
リードフレーム内端子６との間をワイヤフで接続するた
めのアルミニウム薄膜配線層２４の露出部である。
なお、前記従来例の図面で説明したものと同等の部分に
ついては同一符号を付し、かつ、同等部分についての説
明は省略する。
第２図は本発明実施例の構成を示す断面図で。
薄膜／厚膜混成集積回路の場合の部分的断面である。
図中、ｌはセラミック基板で、たとえば、大きさ２３ｍ
ｍＸ２３ｍｍ、厚さ０．６ｍｍである。８は基板ｌ上に
印刷配線された厚膜導体層、たとえば、Ａｇ／Ｐｄから
なる厚膜導体配線層で、こ＼には図示してない厚膜抵抗
体などに接続され、必要により薄膜配線層とはスルーホ
ールを介して接続されている。
９は絶縁層で厚膜回路部分とその上に形成される薄膜回
路部分を分離するためのもので、たとえば、スピンコー
ティングによる厚さ２０ｐｍのポリイミド樹脂層からな
り、必要によりこ＼には図示されてないスルーホールが
設けられる。
２は銅薄膜配線層で本発明の心臓部をなすものであり、
必要により絶縁層との密着性をよくするための銅薄膜密
着層２１゜たとえば、厚さ５０ｎｍのＣｒｉｌｌｉと、
その上に形成された厚さ２．５μｍのｍｉｌｌ膜配線層
２２と、さらにその上に形成された銅薄膜バリヤ層、た
とえば、厚さ５０ｎｍのＣｒ薄膜と、さらにその上に形
成された厚さ１μｍのアルミニウム薄膜配線層２４と、
さらにその上に必要に応じて形成された銅薄膜保護Ｎ２
５．たとえば、厚さｌＱＯｎｍのＣｒ薄膜とからなり、
この積層膜を形成するには、たとえば、連続スパッタ法
を用いればよい、また、薄膜導体配線パターンは通常の
ホトエッチング法を使用し、この時、同時にチップ部品
３の接続のためのｇ！薄膜配線層の露出部やＩＣベアチ
ップ４の電極端子部とのワイヤボンディングのためのア
ルミニウふ薄膜配線層のボンディングパッド２４”など
も所要の位置に所要の個数を形成する。
５は導電性接着材層で、たとえば、銀ペーストであり、
上記のごとく予め形成された銅（Ｃｏ） ＦＩ［膜配線
１１２２の露出部とチップ部品３の電極端子部との間を
接着固定して電気的に接続する。また、同時に導電性接
着材層５はＩＣベアチップ４を基板ｌ上に、たとえば、
アルミニウム薄膜配線層２４の露出部を介して搭載固定
（いわゆる。ダイボンディング）するためにも用いられ
る。
ＩＣベアチップ４の電極端子部と、ＩＣベアチップ４の
搭載部分の周囲のアルミニウム薄膜配線層２４の一部に
設けられているボンディングパッド２４との間はワイヤ
７、たとえば、２５μｍφの金（Ａｕ）線を用い、たと
えば、熱圧着超音波ボンディングにより接続される。
６はリードフレームの内端子で、基板１の周辺のアルミ
ニウム薄膜配線層２４の一部に設けられている他のボン
ディングパッド２４ との間を、同じ（ワイヤフで同様
の方法によりボンディングし、外装、たとえば、トラン
スファー樹脂モールドパッケージを施したのち、試験し
て本発明の混成集積回路を完成する。
このようにして作成された混成集積回路の導体配線抵抗
は充分に小さく実用上全く問題がなく、搭載部品との接
続抵抗も従来の金（＾Ｕ）薄膜配線層の場合と比較して
何ら遜色がなかった。また、温度サイクル試験・振動試
験などにおいても安定な品質を持つことが確認された。
なお、本実施例では＊Ｍ／ ＦＪ膜混成構造の場合−の
例を示したが、薄膜だけから構成される混成集積回路に
おいても、全く同様に本発明が適用できることは言うま
でもない。
また、銅薄膜配線層２のうち、銅薄膜配線層２１．銅薄
膜バリヤ層２３．銅薄膜保護層２５は全体の構成条件に
よっては、その一部または全部を省略除去してもよい。
以上述べた実施例は一例を示したもので、本発明の趣旨
に添うものである限り、使用する材料や部品、および構
成など適宜好ましいもの、あるいはその組み合わせを用
いることができることは勿論である。
〔発明の効果〕
以上述べたように、本発明の混成集積回路における銅薄
膜配線層２は、金（Ａｕ）を全く使用せずに、安価な銅
薄膜配線層２２とアルミニウアルミニウム薄膜配線層２
４を主体として構成されており。
しかも、ワイヤボンディングする配線層部分にはアルミ
ニウム薄膜配線層２４の露出部であるボンディングパッ
ドを用い、導電性接着材層により接続する配線層部分に
は銅薄膜配線層２２の露出部を用いることにより、実質
的に従来の金（＾ｕ）１３１１膜配線層の場合と同様に
、チップ部品３やＩＣベアチップ４を搭載接続すること
ができる。したがって、混成集積回路の価格低減に寄与
するところが極めて大きい。[Detailed Description of the Invention] [Summary] Regarding the structure of a hybrid integrated circuit, by replacing the copper thin film wiring layer of the hybrid integrated circuit with expensive gold and using a multilayer thin film wiring layer made of an inexpensive metal, the hybrid integrated circuit can be realized. For the purpose of reducing the overall price, at least a copper thin film wiring layer is formed on the substrate, and the copper thin film wiring layer and the electrode terminal portion of the chip component are bonded with a conductive adhesive layer, and the copper thin film wiring In a hybrid integrated circuit in which the copper thin film wiring layer and the electrode terminal portion of the IC bare chip are connected by wire bonding, and the copper thin film wiring layer and the terminal in the lead frame are connected by wire bonding, the copper thin film wiring layer is at least the copper thin film wiring layer. , a copper thin film barrier layer, and an aluminum thin film wiring layer, the exposed portion of the copper thin film wiring layer and the electrode terminal portion of the chip component are adhesively connected by a conductive adhesive layer, and the aluminum thin film wiring layer A hybrid integrated circuit is constructed by connecting by wire bonding between the bonding pad of the aluminum thin film wiring layer and the electrode terminal portion of the IC bare chip, and between the bonding pad of the aluminum thin film wiring layer and the terminal within the lead frame. [Field of Industrial Application] The present invention relates to a hybrid integrated circuit, and (in particular, to a hybrid integrated circuit having a thin film metal conductor wiring layer or a thin film metal conductor wiring layer of a hybrid integrated circuit having a thin film/thick film hybrid conductor wiring layer). Concerning improvements in configuration.In recent years, as the degree of integration and scale of hybrid integrated circuits has increased, there has been a strong tendency for the substrates used there to also become larger.Accompanying this, the conductor wiring patterns used in these circuits have become larger. The price of the materials that make up the integrated circuit is also a factor pushing up the overall price of hybrid integrated circuits.In particular, thin film or thin film/thick film hybrid integrated circuits that mount chip components and IC bare chips usually use gold (Au) thin film. The use of wiring layers has a large impact on price, and in order to reduce the price, there has been a need to develop hybrid integrated circuits using new copper thin film wiring layers. [Conventional technology] Figure 3 shows a conventional hybrid integrated circuit. This is a partial cross section of a thin film/thick film hybrid integrated circuit. In the figure, ■ is a ceramic substrate, 8 is a thick film conductor layer printed on the substrate l, and 9 is an insulation layer. The layer is for separating the thick film circuit part and the thin film circuit part formed thereon. 200 is a copper thin film wiring layer. For example, a copper thin film adhesion layer 201 of NiCr and gold (80) are used.
It is composed of a capping film wiring layer 202. 3 is a chip component such as a resistor or a capacitor, and 4 is a semiconductor-based C bare chip (a bare IC chip that is not packaged). 5 is a conductive adhesive layer, for example, silver paste;
The gold (Au) thin film wiring layer and the electrode terminal portion of the chip component 3 are adhesively fixed and electrically connected. At the same time, the conductive adhesive layer 5 is also used to mount and fix the C bare chip 4 onto the substrate 1 via a predetermined land provided on a part of the gold (Au) thin film wiring layer 202, for example. 6 is an inner terminal of the lead frame, and a wire is connected between it and the bonding pad of the gold(^u)Fl film wiring layer 202. For example, they are connected by gold (Au) wires. In addition, the wires are made of gold (^u
) The bonding pads of the Fl film wiring layer 202 are electrically connected. That is, in such a hybrid integrated circuit, the copper thin film wiring layer 2
00 and a mounted component, for example, chip component 3 or I
The connection with the C bare chip 4 is made using completely different connection techniques: wire bonding and conductive adhesive. The connection exposed layer of the copper thin film wiring layer 200, that is, the gold (Au
) The exposed Au surface of the bonding pad of the thin film wiring layer 202 has been widely used because it can easily achieve both of these requirements. [Problem to be solved by the invention] However, the gold (A(1) Tel
There is a problem in that the membrane wiring layer is extremely expensive and the price of the hybrid integrated circuit is also high. In addition, metals that are cheaper and more abundant in resources, such as aluminum (^ffi)
It is conceivable to use a tl film, but in this case wire bonding is possible in the same way as with the gold (^u) 11 film, but the connection resistance when connected by a conductive adhesive layer is
u) For thin films, it is about 20 mΩ, but on the other hand, for aluminum (A f ) thin films, it is about 1.5 Ω or more, which is about 2 mΩ.
There was a problem that the size of the product was too large, making it impossible to use the product due to its performance, and a solution was needed. [Means for Solving the Problem] The above problem is solved by forming at least the copper thin film wiring layer 2 on the substrate l, and connecting the copper thin film wiring layer 2 and the electrode terminal portion of the chip component 3 to the conductive adhesive layer 5. In a hybrid integrated circuit in which the copper thin film wiring layer 2 and the electrode terminal portion of the IC bare chip 4 are bonded by wire bonding, and the copper thin film wiring layer 2 and the lead frame internal terminal 6 are connected by wire bonding. , the copper thin film wiring layer 2 is composed of a laminated film of at least a copper thin film wiring layer 22, a copper thin film barrier layer 23, and an aluminum thin film wiring layer 24, and the exposed portion of the copper thin film wiring layer 22 and the electrode terminal of the chip component 3 are connected to each other. The aluminum thin film wiring layer 24 is adhesively connected to the conductive adhesive layer 5.
This problem is solved by connecting the bonding pads of the aluminum thin film wiring layer 24 and the terminals 6 in the lead frame by wire bonding to form a hybrid integrated circuit. can do. [Function] The copper thin film wiring layer 2 of the hybrid integrated circuit of the present invention is made of gold (^U).
It is composed of a laminated film of at least a copper thin film wiring layer 22, a copper thin film barrier layer 23, and an aluminum thin film wiring 1124. Therefore, the aluminum thin film wiring 1124 is used in the wiring layer portion to be wire bonded.
By using the bonding pad which is the exposed part of the copper thin film wiring layer 22 and using the exposed part of the copper thin film wiring layer 22 for the wiring layer part that is connected by the conductive adhesive layer which cannot be connected to the aluminum thin film with low contact resistance, it is substantially possible to Gold (Au) *Similar to the case of the film wiring layer, chip components 3 and IC bare chips 4 can be mounted and connected. Note that the copper thin film wiring layer 2
If necessary, a copper thin film barrier layer such as chromium (Cr) may be provided between the aluminum thin film wiring layer 2 and the aluminum thin film wiring layer 24 in order to prevent diffusion of both metals. [Embodiment] FIG. 1 is a perspective view showing an embodiment of the present invention. In the figure, 24
″ is a bonding pad of aluminum thin film wiring layer,
For example, it is an exposed portion of the aluminum thin film wiring layer 24 for connecting with the electrode terminal portion of the IC bare chip 4 and the terminal 6 in the lead frame with a wire. Note that the same reference numerals are given to the same parts as those explained in the drawings of the conventional example, and the explanation of the same parts will be omitted. FIG. 2 is a sectional view showing the configuration of an embodiment of the present invention. 1 is a partial cross-section of a thin film/thick film hybrid integrated circuit. In the figure, l is a ceramic substrate, for example, 23 m in size.
The size is m×23 mm and the thickness is 0.6 mm. Reference numeral 8 denotes a thick film conductor layer printed on the substrate 1, for example, a thick film conductor wiring layer made of Ag/Pd, which is connected to a thick film resistor etc. (not shown), and thin film wiring if necessary. The layers are connected via through holes. Reference numeral 9 denotes an insulating layer for separating the thick film circuit part and the thin film circuit part formed thereon, and is made of, for example, a 20 pm thick polyimide resin layer formed by spin coating. A through-hole is provided. 2 is a copper thin film wiring layer that forms the heart of the present invention;
Copper thin film adhesion layer 21° for improving adhesion with the insulating layer if necessary, for example, 50 nm thick Crillium,
A mill film wiring layer 22 with a thickness of 2.5 μm formed thereon, a copper thin film barrier layer further formed thereon, for example, a Cr thin film with a thickness of 50 nm, and a thin film wiring layer 22 formed thereon with a thickness of 2.5 μm. a 1 μm aluminum thin film wiring layer 24;
Furthermore, copper thin film protection N2 is formed on top of it as necessary.
5. For example, it consists of a Cr thin film with a thickness of lQOnm,
To form this laminated film, for example, a continuous sputtering method may be used, and the thin film conductor wiring pattern may be formed using an ordinary photoetching method, and at the same time, g! A required number of bonding pads 24'' of the aluminum thin film wiring layer for wire bonding with the exposed portion of the thin film wiring layer and the electrode terminal portion of the IC bare chip 4 are also formed at the required positions. 5 is a conductive adhesive material. layer, for example silver paste,
As described above, the exposed portion of the copper (Co) FI [membrane wiring 1122 and the electrode terminal portion of the chip component 3 are bonded and fixed to electrically connect. At the same time, the conductive adhesive layer 5 is used to attach the IC bare chip 4 onto the substrate l, for example.
It is also used for mounting and fixing (so-called die bonding) via the exposed portion of the aluminum thin film wiring layer 24. A wire 7, for example, a 25 μmφ gold (Au wire) is connected between the electrode terminal part of the IC bare chip 4 and the bonding pad 24 provided on a part of the aluminum thin film wiring layer 24 around the mounting part of the IC bare chip 4. For example, they are connected by thermocompression, ultrasonic bonding, etc. Reference numeral 6 denotes an inner terminal of the lead frame, which is bonded to another bonding pad 24 provided in a part of the aluminum thin film wiring layer 24 around the substrate 1 by a similar method using the same wire. For example, after applying a transfer resin mold package, the hybrid integrated circuit of the present invention is completed by testing. The connection resistance with components was also comparable to that of conventional gold (^U) thin film wiring layers.It was also confirmed to have stable quality in temperature cycle tests and vibration tests. Although this example shows an example of *M/FJ film hybrid structure, it goes without saying that the present invention can be applied in exactly the same way to a hybrid integrated circuit composed only of thin films. Of the thin film wiring layer 2, part or all of the copper thin film wiring layer 21, the copper thin film barrier layer 23, and the copper thin film protective layer 25 may be omitted and removed depending on the overall structural conditions. The above is an example, and it is of course possible to use suitable materials, parts, and configurations, or combinations thereof, as long as they comply with the spirit of the present invention. [Effects of the Invention] As described above, the copper thin film wiring layer 2 in the hybrid integrated circuit of the present invention does not use gold (Au) at all, and is composed of an inexpensive copper thin film wiring layer 22 and an aluminum/aluminum thin film wiring layer 2.
It is mainly composed of 4. Moreover, by using the bonding pad, which is the exposed part of the aluminum thin film wiring layer 24, in the wiring layer part to be wire-bonded, and by using the exposed part of the copper thin film wiring layer 22 in the wiring layer part, which is connected by the conductive adhesive layer. , chip components 3 and IC bare chips 4 can be mounted and connected substantially in the same way as in the case of the conventional gold (^u) 1311 film wiring layer. Therefore, it greatly contributes to reducing the price of hybrid integrated circuits.
第１図は本発明の実施例を示す斜視図、第２図は本発明
実施例の構成を示す断面図、第３図は従来の混成集積回
路の例を示す断面図である。
図において、
１は基板、
２・は銅薄膜配線層、
３はチップ部品、
４はＩＣベアチップ、
５導電性接着材層、
６はリードフレーム内端子、
７はワイヤ、
２１は銅薄膜密着層、
２２は銅薄膜配線層、
２３は銅薄膜バリヤ層、
２４はアルミニウム薄膜配線層、
２５は銅薄膜保護層である。
＄Ｚ明の失旗例ΣＴ％丁斜纜図
第１ 図
７ ｌ ｌ Ｉ
Ｉ門−一→杢完明大棚別の情成と示す断面図
２０２金（Ａｕ）尊腰配線看
ｚｏｏ ：金ｘｓｇ１Ｍ！蒜Ｅ
従来の混威１！積回路の例）Ｒ示１１１面図％ ５図
FIG. 1 is a perspective view showing an embodiment of the present invention, FIG. 2 is a sectional view showing the configuration of the embodiment of the invention, and FIG. 3 is a sectional view showing an example of a conventional hybrid integrated circuit. In the figure, 1 is a board, 2 is a copper thin film wiring layer, 3 is a chip component, 4 is an IC bare chip, 5 is a conductive adhesive layer, 6 is a terminal in the lead frame, 7 is a wire, 21 is a copper thin film adhesive layer, 22 is a copper thin film wiring layer, 23 is a copper thin film barrier layer, 24 is an aluminum thin film wiring layer, and 25 is a copper thin film protective layer. Example of lost flag of $Z Ming ΣT% diagonal diagram 1st Figure 7
Imon-1 → Cross-sectional diagram showing the information of another large shelf 202 Gold (Au) ZOO: Gold xsg1M! Garlic E Traditional mix 1! Example of product circuit) R diagram 111 view% 5
Claims (1)
成され、前記金属薄膜配線層（２）とチップ部品（３）
の電極端子部とが導電性接着材層（５）により接着され
、前記金属薄膜配線層（２）とＩＣベアチップ（４）の
電極端子部との間、および前記金属薄膜配線層（２）と
リードフレーム内端子（６）との間がワイヤボンディン
グにより接続されてなる混成集積回路において、 前記金属薄膜配線層（２）が少なくとも銅薄膜配線層（
２２）と、金属薄膜バリヤ層（２３）と、アルミニウム
薄膜配線層（２４）の積層膜からなり、前記銅薄膜配線
層（２２）の露出部とチップ部品（３）の電極端子部と
を導電性接着材層（５）により接着接続し、 前記アルミニウム薄膜配線層（２４）のボンディングパ
ッドとＩＣベアチップ（４）の電極端子部との間、およ
び前記アルミニウム薄膜配線層（２４）のボンディング
パッドとリードフレーム内端子（６）との間をワイヤボ
ンディングにより接続することを特徴とした混成集積回
路。[Claims] At least a metal thin film wiring layer (2) is formed on a substrate (1), and the metal thin film wiring layer (2) and a chip component (3) are formed on the substrate (1).
is bonded to the electrode terminal portion of the IC bare chip (4) by a conductive adhesive layer (5), and between the metal thin film wiring layer (2) and the electrode terminal portion of the IC bare chip (4), and between the metal thin film wiring layer (2) and the electrode terminal portion of the IC bare chip (4). In a hybrid integrated circuit which is connected to a terminal (6) in a lead frame by wire bonding, the metal thin film wiring layer (2) has at least a copper thin film wiring layer (
22), a metal thin film barrier layer (23), and an aluminum thin film wiring layer (24). adhesively connected by the adhesive layer (5), between the bonding pad of the aluminum thin film wiring layer (24) and the electrode terminal part of the IC bare chip (4), and between the bonding pad of the aluminum thin film wiring layer (24). A hybrid integrated circuit characterized in that it is connected to a terminal (6) in a lead frame by wire bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28811389A JPH03148894A (en) | 1989-11-06 | 1989-11-06 | hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28811389A JPH03148894A (en) | 1989-11-06 | 1989-11-06 | hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03148894A true JPH03148894A (en) | 1991-06-25 |
Family
ID=17725971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28811389A Pending JPH03148894A (en) | 1989-11-06 | 1989-11-06 | hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03148894A (en) |
-
1989
- 1989-11-06 JP JP28811389A patent/JPH03148894A/en active Pending
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